 @@ -1,14 +1,14 @@
-/*	$NetBSD: ehci.c,v 1.154.4.2 2010/06/12 01:05:44 riz Exp $ */
+/*	$NetBSD: ehci.c,v 1.154.4.2.4.1 2011/01/07 02:50:47 matt Exp $ */
 /*
  * Copyright (c) 2004-2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net), Charles M. Hannum and
  * Jeremy Morse (jeremy.morse@gmail.com).
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -42,27 +42,27 @@
 /*
  * TODO:
  * 1) hold off explorations by companion controllers until ehci has started.
+ *
  * 2) The hub driver needs to handle and schedule the transaction translator,
  *    to assign place in frame where different devices get to go. See chapter
  *    on hubs in USB 2.0 for details.
+ *
  * 3) command failures are not recovered correctly
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.154.4.2 2010/06/12 01:05:44 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.154.4.2.4.1 2011/01/07 02:50:47 matt Exp $");
 #include "ohci.h"
 #include "uhci.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/device.h>
 #include <sys/select.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/mutex.h>
 @@ -386,26 +386,37 @@ ehci_init(ehci_softc_t *sc)
 	usb_delay_ms(&sc->sc_bus, 1);
 	EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
 	for (i = 0; i < 100; i++) {
 		usb_delay_ms(&sc->sc_bus, 1);
 		hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
 		if (!hcr)
 			break;
+	}
 	if (hcr) {
 		aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev));
 		return (USBD_IOERROR);
+	}
 	/*
 	 * If we are doing embedded transaction translation function, force
 	 * the controller to host mode.
 	 */
 	if (sc->sc_flags & EHCIF_ETTF) {
 		uint32_t usbmode = EREAD4(sc, EHCI_USBMODE);
 		usbmode &= ~EHCI_USBMODE_CM;
 		usbmode |= EHCI_USBMODE_CM_HOST;
 		EWRITE4(sc, EHCI_USBMODE, usbmode);
+	}
 	/* XXX need proper intr scheduling */
 	sc->sc_rand = 96;
 	/* frame list size at default, read back what we got and use that */
 	switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
 	case 0: sc->sc_flsize = 1024; break;
 	case 1: sc->sc_flsize = 512; break;
 	case 2: sc->sc_flsize = 256; break;
 	case 3: return (USBD_IOERROR);
+	}
 	err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
 	    EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
 	if (err)
 @@ -1537,27 +1548,37 @@ ehci_open(usbd_pipe_handle pipe)
 	u_int8_t addr = dev->address;
 	u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
 	struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
 	ehci_soft_qh_t *sqh;
 	usbd_status err;
 	int s;
 	int ival, speed, naks;
 	int hshubaddr, hshubport;
 	DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
 		     pipe, addr, ed->bEndpointAddress, sc->sc_addr));
 	if (dev->myhsport) {
-		hshubaddr = dev->myhsport->parent->address;
+		/*
 		 * When directly attached FS/LS device while doing embedded
 		 * transaction translations and we are the hub, set the hub
 		 * adddress to 0 (us).
 		 */
 		if (!(sc->sc_flags & EHCIF_ETTF)
 		    || (dev->myhsport->parent->address != sc->sc_addr)) {
 			hshubaddr = dev->myhsport->parent->address;
 		} else {
 			hshubaddr = 0;
+		}
 		hshubport = dev->myhsport->portno;
 	} else {
 		hshubaddr = 0;
 		hshubport = 0;
+	}
 	if (sc->sc_dying)
 		return (USBD_IOERROR);
 	epipe->nexttoggle = 0;
 	if (addr == sc->sc_addr) {
 		switch (ed->bEndpointAddress) {
 @@ -2245,27 +2266,38 @@ ehci_root_ctrl_start(usbd_xfer_handle xf
 		DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
 			    index));
 		if (index < 1 || index > sc->sc_noport) {
 			err = USBD_IOERROR;
 			goto ret;
+		}
 		if (len != 4) {
 			err = USBD_IOERROR;
 			goto ret;
+		}
 		v = EOREAD4(sc, EHCI_PORTSC(index));
 		DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n",
 			    v));
 		i = UPS_HIGH_SPEED;
 		if (sc->sc_flags & EHCIF_ETTF) {
 			/*
 			 * If we are doing embedded transaction translation,
 			 * then directly attached LS/FS devices are reset by
 			 * the EHCI controller itself.  PSPD is encoded
 			 * the same way as in USBSTATUS.
 			 */
 			i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED;
 		} else {
 			i = UPS_HIGH_SPEED;
+		}
 		if (v & EHCI_PS_CS)	i |= UPS_CURRENT_CONNECT_STATUS;
 		if (v & EHCI_PS_PE)	i |= UPS_PORT_ENABLED;
 		if (v & EHCI_PS_SUSP)	i |= UPS_SUSPEND;
 		if (v & EHCI_PS_OCA)	i |= UPS_OVERCURRENT_INDICATOR;
 		if (v & EHCI_PS_PR)	i |= UPS_RESET;
 		if (v & EHCI_PS_PP)	i |= UPS_PORT_POWER;
 		USETW(ps.wPortStatus, i);
 		i = 0;
 		if (v & EHCI_PS_CSC)	i |= UPS_C_CONNECT_STATUS;
 		if (v & EHCI_PS_PEC)	i |= UPS_C_PORT_ENABLED;
 		if (v & EHCI_PS_OCC)	i |= UPS_C_OVERCURRENT_INDICATOR;
 		if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET;
 		USETW(ps.wPortChange, i);
 @@ -2287,48 +2319,61 @@ ehci_root_ctrl_start(usbd_xfer_handle xf
 		v = EOREAD4(sc, port);
 		DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v));
 		v &= ~EHCI_PS_CLEAR;
 		switch(value) {
 		case UHF_PORT_ENABLE:
 			EOWRITE4(sc, port, v | EHCI_PS_PE);
 			break;
 		case UHF_PORT_SUSPEND:
 			EOWRITE4(sc, port, v | EHCI_PS_SUSP);
 			break;
 		case UHF_PORT_RESET:
 			DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
 				    index));
-			if (EHCI_PS_IS_LOWSPEED(v)) {
+			if (EHCI_PS_IS_LOWSPEED(v)
-				/* Low speed device, give up ownership. */
+			    && !(sc->sc_flags & EHCIF_ETTF)) {
 				/*
 				 * Low speed device on non-ETTF controller,
 				 * give up ownership.
 				 */
 				ehci_disown(sc, index, 1);
 				break;
+			}
 			/* Start reset sequence. */
 			v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
 			EOWRITE4(sc, port, v | EHCI_PS_PR);
 			/* Wait for reset to complete. */
 			usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
 			if (sc->sc_dying) {
 				err = USBD_IOERROR;
 				goto ret;
+			}
-			/* Terminate reset sequence. */
+			/*
-			EOWRITE4(sc, port, v);
+			 * An embedded transaction translater will automatically
-			/* Wait for HC to complete reset. */
+			 * terminate the reset sequence so there's no need to
-			usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
+			 * it.
-			if (sc->sc_dying) {
+			 */
-				err = USBD_IOERROR;
+			if (!(sc->sc_flags & EHCIF_ETTF)) {
-				goto ret;
+				/* Terminate reset sequence. */
 				EOWRITE4(sc, port, v);
 				/* Wait for HC to complete reset. */
 				usb_delay_ms(&sc->sc_bus,
 				    EHCI_PORT_RESET_COMPLETE);
 				if (sc->sc_dying) {
 					err = USBD_IOERROR;
 					goto ret;
+				}
+			}
 			v = EOREAD4(sc, port);
 			DPRINTF(("ehci after reset, status=0x%08x\n", v));
 			if (v & EHCI_PS_PR) {
 				printf("%s: port reset timeout\n",
 				       device_xname(sc->sc_dev));
 				return (USBD_TIMEOUT);
+			}
 			if (!(v & EHCI_PS_PE)) {
 				/* Not a high speed device, give up ownership.*/
 				ehci_disown(sc, index, 0);
 				break;
+			}
 			sc->sc_isreset[index] = 1;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ehcireg.h,v 1.28.4.1 2008/11/29 20:47:05 bouyer Exp $	*/
+/*	$NetBSD: ehcireg.h,v 1.28.4.1.8.1 2011/01/07 02:50:47 matt Exp $	*/
 /*
  * Copyright (c) 2001, 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net).
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -66,26 +66,28 @@
 #define  EHCI_LEG_EXT_SMI_OS_CHANGE	0x20000000
 #define EHCI_CAP_GET_ID(cap) ((cap) & 0xff)
 #define EHCI_CAP_GET_NEXT(cap) (((cap) >> 8) & 0xff)
 #define EHCI_CAP_ID_LEGACY 1
 /*** EHCI capability registers ***/
 #define EHCI_CAPLENGTH		0x00	/*RO Capability register length field */
 /* reserved			0x01 */
 #define EHCI_HCIVERSION		0x02	/* RO Interface version number */
 #define EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
 #define  EHCI_HCS_N_TT(x)	(((x) >> 20) & 0xf) /* # of xacts xlater ETTF */
 #define  EHCI_HCS_N_PTT(x)	(((x) >> 20) & 0xf) /* ports per xlater ETTF */
 #define  EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
 #define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
 #define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf) /* # of companion ctlrs */
 #define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf) /* # of ports per comp. */
 #define  EHCI_HCS_PPC(x)	((x) & 0x10) /* port power control */
 #define  EHCI_HCS_N_PORTS(x)	((x) & 0xf) /* # of ports */
 #define EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
 #define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff) /* extended ports caps */
 #define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf) /* isoc sched threshold */
 #define  EHCI_HCC_ASPC(x)	((x) & 0x4) /* async sched park cap */
 #define  EHCI_HCC_PFLF(x)	((x) & 0x2) /* prog frame list flag */
 #define  EHCI_HCC_64BIT(x)	((x) & 0x1) /* 64 bit address cap */
 @@ -137,48 +139,61 @@
 #define EHCI_INTR_UIE		0x00000001 /* USB intr ena */
 #define EHCI_FRINDEX		0x0c	/* RW Frame Index register */
 #define EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
 #define EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
 #define EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
 #define EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
 #define  EHCI_CONF_CF		0x00000001 /* RW configure flag */
 #define EHCI_PORTSC(n)		(0x40+4*(n)) /* RO, RW, RWC Port Status reg */
 #define  EHCI_PS_PSPD		0x03000000 /* RO port speed (ETTF) */
 #define  EHCI_PS_PSPD_FS	0x00000000 /* Full speed (ETTF) */
 #define  EHCI_PS_PSPD_LS	0x01000000 /* Low speed (ETTF) */
 #define  EHCI_PS_PSPD_HS	0x02000000 /* High speed (ETTF) */
 #define  EHCI_PS_WKOC_E		0x00400000 /* RW wake on over current ena */
 #define  EHCI_PS_WKDSCNNT_E	0x00200000 /* RW wake on disconnect ena */
 #define  EHCI_PS_WKCNNT_E	0x00100000 /* RW wake on connect ena */
 #define  EHCI_PS_PTC		0x000f0000 /* RW port test control */
 #define  EHCI_PS_PIC		0x0000c000 /* RW port indicator control */
 #define  EHCI_PS_PO		0x00002000 /* RW port owner */
 #define  EHCI_PS_PP		0x00001000 /* RW,RO port power */
 #define  EHCI_PS_LS		0x00000c00 /* RO line status */
 #define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
 #define  EHCI_PS_PR		0x00000100 /* RW port reset */
 #define  EHCI_PS_SUSP		0x00000080 /* RW suspend */
 #define  EHCI_PS_FPR		0x00000040 /* RW force port resume */
 #define  EHCI_PS_OCC		0x00000020 /* RWC over current change */
 #define  EHCI_PS_OCA		0x00000010 /* RO over current active */
 #define  EHCI_PS_PEC		0x00000008 /* RWC port enable change */
 #define  EHCI_PS_PE		0x00000004 /* RW port enable */
 #define  EHCI_PS_CSC		0x00000002 /* RWC connect status change */
 #define  EHCI_PS_CS		0x00000001 /* RO connect status */
 #define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
 #define EHCI_PORT_RESET_COMPLETE 2 /* ms */
 #define	EHCI_USBMODE		0xa8		/* USB Device mode */
 #define	  EHCI_USBMODE_SDIS	__BIT(4)	/* Stream disable mode 1=act */
 #define	  EHCI_USBMODE_SLOM	__BIT(3)	/* setup lockouts on */
 #define	  EHCI_USBMODE_ES	__BIT(2)	/* Endian Select ES=1 */
 #define	  EHCI_USBMODE_CM	__BITS(0,1)	/* Controller Mode */
 #define	  EHCI_USBMODE_CM_IDLE	0x00		/* Idle (combo host/device) */
 #define	  EHCI_USBMODE_CM_DEV	0x02		/* Device Controller */
 #define	  EHCI_USBMODE_CM_HOST	0x03		/* Host Controller */
 #define EHCI_FLALIGN_ALIGN	0x1000
 #define EHCI_MAX_PORTS		16 /* only 4 bits available in EHCI_HCS_N_PORTS */
 /* No data structure may cross a page boundary. */
 #define EHCI_PAGE_SIZE 0x1000
 #define EHCI_PAGE(x) ((x) &~ 0xfff)
 #define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
 typedef u_int32_t ehci_link_t;
 #define EHCI_LINK_TERMINATE	0x00000001
 #define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
 #define  EHCI_LINK_ITD		0x0
 #define  EHCI_LINK_QH		0x2

 @@ -1,14 +1,14 @@
-/*	$NetBSD: ehcivar.h,v 1.33 2008/10/14 18:12:38 jmcneill Exp $ */
+/*	$NetBSD: ehcivar.h,v 1.33.16.1 2011/01/07 02:50:47 matt Exp $ */
 /*
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Lennart Augustsson (lennart@augustsson.net).
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -106,26 +106,27 @@ struct ehci_soft_islot {
 #define EHCI_COMPANION_MAX 8
 #define EHCI_FREE_LIST_INTERVAL 100
 typedef struct ehci_softc {
 	device_t sc_dev;
 	struct usbd_bus sc_bus;
 	bus_space_tag_t iot;
 	bus_space_handle_t ioh;
 	bus_size_t sc_size;
 	u_int sc_offs;			/* offset to operational regs */
 	int sc_flags;			/* misc flags */
 #define EHCIF_DROPPED_INTR_WORKAROUND	0x01
 #define EHCIF_ETTF			0x02 /* Emb. Transaction Translater func. */
 	char sc_vendor[32];		/* vendor string for root hub */
 	int sc_id_vendor;		/* vendor ID for root hub */
 	u_int32_t sc_cmd;		/* shadow of cmd reg during suspend */
 	u_int sc_ncomp;
 	u_int sc_npcomp;
 	device_t sc_comps[EHCI_COMPANION_MAX];
 	usb_dma_t sc_fldma;
 	ehci_link_t *sc_flist;
 	u_int sc_flsize;