 @@ -1,16 +1,16 @@
-/*	$NetBSD: cpu.c,v 1.16 2010/12/08 09:48:27 skrll Exp $	*/
+/*	$NetBSD: cpu.c,v 1.17 2011/01/23 21:53:39 skrll Exp $	*/
-/*	$OpenBSD: cpu.c,v 1.28 2004/12/28 05:18:25 mickey Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.29 2009/02/08 18:33:28 miod Exp $	*/
 /*
  * Copyright (c) 1998-2003 Michael Shalayeff
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -19,91 +19,108 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.16 2010/12/08 09:48:27 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.17 2011/01/23 21:53:39 skrll Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/reboot.h>
 #include <uvm/uvm.h>
 #include <machine/cpufunc.h>
 #include <machine/pdc.h>
 #include <machine/iomod.h>
 #include <machine/autoconf.h>
 #include <hp700/hp700/intr.h>
 #include <hp700/hp700/machdep.h>
 #include <hp700/dev/cpudevs.h>
 struct cpu_softc {
 	device_t sc_dev;
 	hppa_hpa_t sc_hpa;
 	void *sc_ih;
 };
 #ifdef MULTIPROCESSOR
 int hppa_ncpus;
 struct cpu_info *cpu_hatch_info;
 static volatile int start_secondary_cpu;
 #endif
 int	cpumatch(device_t, cfdata_t, void *);
 void	cpuattach(device_t, device_t, void *);
 CFATTACH_DECL_NEW(cpu, sizeof(struct cpu_softc),
     cpumatch, cpuattach, NULL, NULL);
 static int cpu_attached;
 int
 cpumatch(device_t parent, cfdata_t cf, void *aux)
+{
 	struct confargs *ca = aux;
 	/* there will be only one for now XXX */
 	/* probe any 1.0, 1.1 or 2.0 */
-	if (cpu_attached ||
+	if (ca->ca_type.iodc_type != HPPA_TYPE_NPROC ||
 	    ca->ca_type.iodc_type != HPPA_TYPE_NPROC ||
 	    ca->ca_type.iodc_sv_model != HPPA_NPROC_HPPA)
 		return 0;
 	if (cf->cf_unit >= MAXCPUS)
 		return 0;
 	return 1;
+}
 void
 cpuattach(device_t parent, device_t self, void *aux)
+{
 	/* machdep.c */
 	extern struct pdc_cache pdc_cache;
 	extern struct pdc_btlb pdc_btlb;
 	extern struct pdc_model pdc_model;
 	extern u_int cpu_ticksnum, cpu_ticksdenom;
 	struct cpu_softc *sc = device_private(self);
 	struct confargs *ca = aux;
-	const char lvls[4][4] = { "0", "1", "1.5", "2" };
+	struct cpu_info *ci;
 	static const char lvls[4][4] = { "0", "1", "1.5", "2" };
 	u_int mhz = 100 * cpu_ticksnum / cpu_ticksdenom;
 	int cpuno = device_unit(self);
 #ifdef MULTIPROCESSOR
 	struct pglist mlist;
 	struct vm_page *m;
 	int error;
 #endif
 	sc->sc_dev = self;
 	cpu_attached = 1;
 	ci = &cpus[cpuno];
 	ci->ci_cpuid = cpuno;
 	ci->ci_hpa = ca->ca_hpa;
 	/* Print the CPU chip name, nickname, and rev. */
 	aprint_normal(": %s", hppa_cpu_info->hci_chip_name);
 	if (hppa_cpu_info->hci_chip_nickname != NULL)
 		aprint_normal(" (%s)", hppa_cpu_info->hci_chip_nickname);
 	aprint_normal(" rev %d", cpu_revision);
 	/* Print the CPU type, spec, level, category, and speed. */
 	aprint_normal("\n%s: %s, PA-RISC %s", self->dv_xname,
 	    hppa_cpu_info->hci_chip_type,
 	    hppa_cpu_info->hci_chip_spec);
 	aprint_normal(", lev %s, cat %c, ",
 	    lvls[pdc_model.pa_lvl], "AB"[pdc_model.mc]);
 @@ -141,30 +158,134 @@ cpuattach(device_t parent, device_t self
 		aprint_normal("\n%s: no floating point support",
 		    self->dv_xname);
 	else
 #endif /* !FPEMUL */
+	{
 		aprint_normal("\n%s: %s floating point, rev %d", self->dv_xname,
 		    hppa_mod_info(HPPA_TYPE_FPU, (fpu_version >> 16) & 0x1f),
 		    (fpu_version >> 11) & 0x1f);
+	}
 	aprint_normal("\n");
 	/* sanity against luser amongst config editors */
-	if (ca->ca_irq == 31) {
+	if (ca->ca_irq != 31) {
 		sc->sc_ih = hp700_intr_establish(IPL_CLOCK, clock_intr,
 		    NULL /*clockframe*/, &int_reg_cpu, ca->ca_irq);
 	} else {
 		aprint_error_dev(self, "bad irq number %d\n", ca->ca_irq);
 		return;
+	}
 	sc->sc_ih = hp700_intr_establish(IPL_CLOCK, clock_intr,
 	    NULL /*clockframe*/, &int_reg_cpu, 31);
 #ifdef MULTIPROCESSOR
 	/* Allocate stack for spin up and FPU emulation. */
 	TAILQ_INIT(&mlist);
 	error = uvm_pglistalloc(PAGE_SIZE, 0, -1L, PAGE_SIZE, 0, &mlist, 1,
 );
 	if (error) {
 		aprint_error(": unable to allocate CPU stack!\n");
 		return;
+	}
 	m = TAILQ_FIRST(&mlist);
 	ci->ci_stack = VM_PAGE_TO_PHYS(m);
 	if (ci->ci_hpa == hppa_mcpuhpa) {
 		ci->ci_flags |= CPUF_PRIMARY|CPUF_RUNNING;
 	} else {
 		int err;
 		err = mi_cpu_attach(ci);
 		if (err) {
 			aprint_error_dev(self,
 			    "mi_cpu_attach failed with %d\n", err);
 			return;
+		}
+	}
 #endif
 	/*
 	 * Set the allocatable bits in the CPU interrupt registers.
 	 * These should only be used by major chipsets, like ASP and
 	 * LASI, and the bits used appear to be important - the
 	 * ASP doesn't seem to like to use interrupt bits above 28
 	 * or below 27.
 	 */
 	int_reg_cpu.int_reg_allocatable_bits =
 		(1 << 28) | (1 << 27) | (1 << 26);
+}
 #ifdef MULTIPROCESSOR
 void
 cpu_boot_secondary_processors(void)
+{
 	struct cpu_info *ci;
 	struct iomod *cpu;
 	int i, j;
 	for (i = 0; i < HPPA_MAXCPUS; i++) {
 		ci = &cpus[i];
 		if (ci->ci_cpuid == 0)
 			continue;
 		if (ci->ci_data.cpu_idlelwp == NULL)
 			continue;
 		if (ci->ci_flags & CPUF_PRIMARY)
 			continue;
 		/* Release the specified CPU by triggering an EIR{0}. */
 		cpu_hatch_info = ci;
 		cpu = (struct iomod *)(ci->ci_hpa);
 		cpu->io_eir = 0;
 		membar_sync();
 		/* Wait for CPU to wake up... */
 		j = 0;
 		while (!(ci->ci_flags & CPUF_RUNNING) && j++ < 10000)
 			delay(1000);
 		if (!(ci->ci_flags & CPUF_RUNNING))
 			printf("failed to hatch cpu %i!\n", ci->ci_cpuid);
+	}
 	/* Release secondary CPUs. */
 	start_secondary_cpu = 1;
 	membar_sync();
+}
 void
 cpu_hw_init(void)
+{
 	struct cpu_info *ci = curcpu();
 	/* Purge TLB and flush caches. */
 	ptlball();
 	fcacheall();
 	/* Enable address translations. */
 	ci->ci_psw = PSW_I | PSW_Q | PSW_P | PSW_C | PSW_D;
 	ci->ci_psw |= (cpus[0].ci_psw & PSW_O);
 	ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
+}
 void
 cpu_hatch(void)
+{
 	struct cpu_info *ci = curcpu();
 	ci->ci_flags |= CPUF_RUNNING;
 	/* Wait for additional CPUs to spinup. */
 	while (!start_secondary_cpu)
+		;
 	/* Spin for now */
 	for (;;)
+		;
+}
 #endif

 @@ -1,14 +1,14 @@
-#	$NetBSD: genassym.cf,v 1.30 2011/01/23 09:44:58 skrll Exp $
+#	$NetBSD: genassym.cf,v 1.31 2011/01/23 21:53:39 skrll Exp $
 #	$OpenBSD: genassym.cf,v 1.18 2001/09/20 18:31:14 mickey Exp $
+#
 # Copyright (c) 1982, 1990, 1993
 #	The Regents of the University of California.  All rights reserved.
+#
 # Redistribution and use in source and binary forms, with or without
 # modification, are permitted provided that the following conditions
 # are met:
 # 1. Redistributions of source code must retain the above copyright
 #    notice, this list of conditions and the following disclaimer.
 # 2. Redistributions in binary form must reproduce the above copyright
 @@ -91,29 +91,29 @@ member	INT_REG_BITS_MAP	int_reg_bits_map
 export	INT_REG_BIT_REG
 # struct cpu_info fields
 define	CI_CPL			offsetof(struct cpu_info, ci_cpl)
 define	CI_IPENDING		offsetof(struct cpu_info, ci_ipending)
 #define	CI_INTR_DEPTH		offsetof(struct cpu_info, ci_intr_depth)
 #define	CI_SOFTLWPS		offsetof(struct cpu_info, ci_softlwps)
 define	CI_MTX_COUNT		offsetof(struct cpu_info, ci_mtx_count)
 define	CI_TRAPSAVE		offsetof(struct cpu_info, ci_trapsave)
 define	CI_PSW			offsetof(struct cpu_info, ci_psw)
 define	CI_FPU_STATE		offsetof(struct cpu_info, ci_fpu_state)
 ifdef MULTIPROCESSOR
 define	CI_CURLWP		offsetof(struct cpu_info, ci_curlwp)
 define	CI_STACK		offsetof(struct cpu_info, ci_stack)
 endif
 define	MTX_IPL			offsetof(struct kmutex, mtx_ipl)
 define	MTX_LOCK		offsetof(struct kmutex, mtx_lock)
 define	MTX_OWNER		offsetof(struct kmutex, mtx_owner)
 define	MTX_WAITERS		offsetof(struct kmutex, mtx_waiters)
 define	RW_OWNER		offsetof(struct krwlock, rw_owner)
 define	RW_WRITE_LOCKED		RW_WRITE_LOCKED
 define	RW_WRITE_WANTED		RW_WRITE_WANTED
 define	RW_READ_INCR		RW_READ_INCR
 define	RW_HAS_WAITERS		RW_HAS_WAITERS
 define	RW_THREAD		RW_THREAD
 define	RW_READER		RW_READER
 define	RW_WRITER		RW_WRITER

 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.S,v 1.52 2011/01/23 09:44:58 skrll Exp $	*/
+/*	$NetBSD: locore.S,v 1.53 2011/01/23 21:53:39 skrll Exp $	*/
 /*	$OpenBSD: locore.S,v 1.158 2008/07/28 19:08:46 miod Exp $	*/
 /*
  * Copyright (c) 1998-2004 Michael Shalayeff
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -248,26 +248,38 @@ L$start_zero_tf:
 	stw	%t3, R%lwp0+L_PCB(%t2)		/* XXXuvm_lwp_getuarea */
 	ldo	NBPG(%t3), %t1
 	stw	%t1, R%lwp0+L_MD_REGS(%t2)
 	ldil	L%TFF_LAST, %t1
 	stw	%t1, TF_FLAGS-TRAPFRAME_SIZEOF(%sp)
 	stw	%t3, TF_CR30-TRAPFRAME_SIZEOF(%sp)
 	/*
 	 * disable all coprocessors
 	 */
 	mtctl	%r0, %ccr
 #ifdef MULTIPROCESSOR
 #define	PZ_MEM_RENDEZ		0x10
 #define	PZ_MEM_RENDEZ_HI	0x28
 	/* Setup SMP rendezvous address. */
 	ldil	L%hw_cpu_spinup_trampoline, %r1
 	ldo	R%hw_cpu_spinup_trampoline(%r1), %r1
 	stw	%r1, PZ_MEM_RENDEZ(%r0)
 	stw	%r0, PZ_MEM_RENDEZ_HI(%r0)
 #endif
 	/*
 	 * We need to set the Q bit so that we can take TLB misses after we
 	 * turn on virtual memory.
 	 */
 	copy	%sp, %arg0
 	ldil	L%qisnowon, %rp
 	ldo	R%qisnowon(%rp), %rp
 	b	kernel_setup
 	ldi	PSW_Q|PSW_I, %arg1
 qisnowon:
 	copy	%r4, %arg0
 @@ -401,26 +413,149 @@ LEAF_ENTRY_NOPROFILE(kernel_setup)
 	 */
 	mtctl	%r0, %pcsq
 	mtctl	%r0, %pcsq
 	mtctl	%rp, %pcoq
 	ldo	4(%rp), %rp
 	mtctl	%rp, %pcoq
 	mtctl	%arg1, %ipsw
 	rfi
 	nop
 	nop
 EXIT(kernel_setup)
 #ifdef MULTIPROCESSOR
 /*
  * Trampoline to spin up secondary processors.
  */
 LEAF_ENTRY_NOPROFILE(hw_cpu_spinup_trampoline)
 	/*
 	 * disable interrupts and turn off all bits in the psw so that
 	 * we start in a known state.
 	 */
 	rsm	RESET_PSW, %r0
 	nop ! nop ! nop ! nop ! nop ! nop
 	/* go to virtual mode...
 	/* get things ready for the kernel to run in virtual mode */
 	ldi	HPPA_PID_KERNEL, %r1
 	mtctl	%r1, %pidr1
 	mtctl	%r1, %pidr2
 #if pbably_not_worth_it
 	mtctl	%r0, %pidr3
 	mtctl	%r0, %pidr4
 #endif
 	mtsp	%r0, %sr0
 	mtsp	%r0, %sr1
 	mtsp	%r0, %sr2
 	mtsp	%r0, %sr3
 	mtsp	%r0, %sr4
 	mtsp	%r0, %sr5
 	mtsp	%r0, %sr6
 	mtsp	%r0, %sr7
 	/*
 	 * disable all coprocessors
 	 */
 	mtctl   %r0, %ccr
 	/*
 	 * to keep the spl() routines consistent we need to put the correct
 	 * spl level into eiem, and reset any pending interrupts
 	 */
 	ldi	-1, %r1
 	mtctl	%r0, %eiem		/* disable interrupts */
 	mtctl	%r1, %eirr
 	/*
 	 * load address of interrupt vector table
 	 */
 	ldil	L%ivaaddr, %t2
 	ldo	R%ivaaddr(%t2), %t2
 	mtctl	%t2, %iva
 	/*
 	 * set up the dp pointer so that we can do quick references off of it
 	 */
 	ldil	L%$global$, %dp
 	ldo	R%$global$(%dp), %dp
 	/*
 	 * Store address of cpu_info in CR_CURCPU.
 	 */
 	ldil	L%cpu_hatch_info, %r3
 	ldw	R%cpu_hatch_info(%r3), %r3
 	mtctl	%r3, CR_CURCPU
 	/*
 	 * Setup the stack frame for us to call C with and mark this as the
 	 * first frame on the stack.
 	 */
 	ldw	CI_STACK(%r3), %sp
 	stw,ma	%r0, HPPA_FRAME_SIZE(%sp)
 	stw	%r0, HPPA_FRAME_CRP(%sp)
 	stw	%r0, HPPA_FRAME_PSP(%sp)
 	/* Provide CPU with page tables. */
 	ldil	L%hppa_vtop, %t1
 	ldw	R%hppa_vtop(%t1), %t1
 	mtctl	%t1, CR_VTOP
 	/* Turn on the Q bit so that we can handle TLB traps. */
 	ldil	L%qenabled, %t1
 	ldo	R%qenabled(%t1), %t1
 	mtctl	%r0, %pcsq
 	mtctl	%r0, %pcsq
 	mtctl	%t1, %pcoq
 	ldo	4(%t1), %t1
 	mtctl	%t1, %pcoq
 	ldi	PSW_Q|PSW_I, %t2
 	mtctl	%t2, %ipsw
 	rfi
 	nop
 qenabled:
 	/* Call C routine to setup CPU. */
 	.import cpu_hw_init, code
 	CALL(cpu_hw_init, %r1)
 	/* Switch CPU mode. */
 	ldil	L%cpu_spinup_vm, %t1
 	ldo	R%cpu_spinup_vm(%t1), %t1
 	mtctl	%r0, %pcsq
 	mtctl	%r0, %pcsq
 	mtctl	%t1, %pcoq
 	ldo	4(%t1), %t1
 	mtctl	%t1, %pcoq
 	mfctl	CR_CURCPU, %t2
 	ldw	CI_PSW(%t2), %t2
 	mtctl	%t2, %ipsw
 	rfi
 	nop
 cpu_spinup_vm:
 	/*
 	 * Okay, time to return to the land of C.
 	 */
 	b	cpu_hatch
 	nop
 EXIT(hw_cpu_spinup_trampoline)
 #endif
 /*
  * int pdc_call(iodcio_t func,int pdc_flag, ...)
  */
 ENTRY(pdc_call,160)
 	mfctl	%eiem, %t1
 	mtctl	%r0, %eiem		/* disable interrupts */
 	stw	%rp, HPPA_FRAME_CRP(%sp)
 	copy	%arg0, %r31
 	copy	%sp, %ret1
 	ldil	L%kernelmapped, %ret0
 	ldw	R%kernelmapped(%ret0), %ret0

 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.97 2011/01/23 09:44:58 skrll Exp $	*/
+/*	$NetBSD: machdep.c,v 1.98 2011/01/23 21:53:40 skrll Exp $	*/
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matthew Fredette.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -48,27 +48,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.97 2011/01/23 09:44:58 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.98 2011/01/23 21:53:40 skrll Exp $");
 #include "opt_cputype.h"
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_modular.h"
 #include "opt_useleds.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/signalvar.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/buf.h>
 @@ -127,26 +127,29 @@ __KERNEL_RCSID(0, "$NetBSD: machdep.c,v
 #ifdef PMAPDEBUG
 #include <hppa/hppa/hpt.h>
 #endif
 #include "ksyms.h"
 #include "lcd.h"
 /*
  * Different kinds of flags used throughout the kernel.
  */
 void *msgbufaddr;
 /* The primary (aka monarch) cpu HPA */
 hppa_hpa_t hppa_mcpuhpa;
 /*
  * cache configuration, for most machines is the same
  * numbers, so it makes sense to do defines w/ numbers depending
  * on configured CPU types in the kernel
  */
 int icache_stride, icache_line_mask;
 int dcache_stride, dcache_line_mask;
 /*
  * things to not kill
  */
 volatile u_int8_t *machine_ledaddr;
 int machine_ledword, machine_leds;
 @@ -444,28 +447,35 @@ hppa_init(paddr_t start, void *bi)
 	ci->ci_psw =
 		PSW_Q |         /* Interrupt State Collection Enable */
 		PSW_P |         /* Protection Identifier Validation Enable */
 		PSW_C |         /* Instruction Address Translation Enable */
 		PSW_D;          /* Data Address Translation Enable */
 	/* Copy bootinfo */
 	if (bi != NULL)
 		memcpy(&bootinfo, bi, sizeof(struct bootinfo));
 	pdc_init();	/* init PDC iface, so we can call em easy */
 	cpu_hzticks = (PAGE0->mem_10msec * 100) / hz;
 	delay_init();	/* calculate CPU clock ratio */
 	/* fetch the monarch/"default" cpu hpa */
 	error =  pdcproc_hpa_processor(&hppa_mcpuhpa);
 	if (error < 0)
 		panic("%s: PDC_HPA failed", __func__);
 	/* cache parameters */
 	error = pdcproc_cache(&pdc_cache);
 	if (error < 0) {
 #ifdef DEBUG
 		printf("WARNING: PDC_CACHE error %d\n", error);
 #endif
+	}
 	dcache_line_mask = pdc_cache.dc_conf.cc_line * 16 - 1;
 	dcache_stride = pdc_cache.dc_stride;
 	icache_line_mask = pdc_cache.ic_conf.cc_line * 16 - 1;
 	icache_stride = pdc_cache.ic_stride;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: mainbus.c,v 1.76 2011/01/13 21:15:15 skrll Exp $	*/
+/*	$NetBSD: mainbus.c,v 1.77 2011/01/23 21:53:40 skrll Exp $	*/
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matthew Fredette.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -48,27 +48,27 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.76 2011/01/13 21:15:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mainbus.c,v 1.77 2011/01/23 21:53:40 skrll Exp $");
 #include "locators.h"
 #include "power.h"
 #include "lcd.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/reboot.h>
 #include <sys/extent.h>
 #include <sys/mbuf.h>
 #include <sys/proc.h>
 @@ -1349,61 +1349,55 @@ mb_cpu_mem_callback(device_t self, struc
 	if ((ca->ca_type.iodc_type != HPPA_TYPE_NPROC &&
 	     ca->ca_type.iodc_type != HPPA_TYPE_MEMORY))
 		return NULL;
 	return config_found_sm_loc(self, "gedoens", NULL, ca, mbprint, mbsubmatch);
+}
 void
 mbattach(device_t parent, device_t self, void *aux)
+{
 	struct mainbus_softc *sc = device_private(self);
 	struct confargs nca;
 	bus_space_handle_t ioh;
 	hppa_hpa_t prochpa;
 	int err;
 	sc->sc_dv = self;
 	mb_attached = 1;
 	/* fetch the "default" cpu hpa */
 	err =  pdcproc_hpa_processor(&prochpa);
 	if (err < 0)
 		panic("mbattach: PDC_HPA failed");
 	/*
 	 * Map all of Fixed Physical, Local Broadcast, and Global Broadcast
 	 * space.  These spaces are adjacent and in that order and run to the
 	 * end of the address space.
 	 */
 	/*
 	 * XXX fredette - this may be a copout, or it may be a great idea.  I'm
 	 * not sure which yet.
 	 */
 	/* map all the way till the end of the memory */
-	if (bus_space_map(&hppa_bustag, prochpa, (~0LU - prochpa + 1),
+	if (bus_space_map(&hppa_bustag, hppa_mcpuhpa, (~0LU - hppa_mcpuhpa + 1),
 , &ioh))
 		panic("%s: cannot map mainbus IO space", __func__);
 	/*
 	 * Local-Broadcast the HPA to all modules on the bus
 	 */
-	((struct iomod *)(prochpa & HPPA_FLEX_MASK))[FPA_IOMOD].io_flex =
+	((struct iomod *)(hppa_mcpuhpa & HPPA_FLEX_MASK))[FPA_IOMOD].io_flex =
-		(void *)((prochpa & HPPA_FLEX_MASK) | DMA_ENABLE);
+		(void *)((hppa_mcpuhpa & HPPA_FLEX_MASK) | DMA_ENABLE);
 	sc->sc_hpa = hppa_mcpuhpa;
-	sc->sc_hpa = prochpa;
+	aprint_normal(" [flex %lx]\n", hppa_mcpuhpa & HPPA_FLEX_MASK);
 	aprint_normal(" [flex %lx]\n", prochpa & HPPA_FLEX_MASK);
 	/* PDC first */
 	memset(&nca, 0, sizeof(nca));
 	nca.ca_name = "pdc";
 	nca.ca_hpa = 0;
 	nca.ca_iot = &hppa_bustag;
 	nca.ca_dmatag = &hppa_dmatag;
 	config_found(self, &nca, mbprint);
 #if NPOWER > 0
 	/* get some power */
 	memset(&nca, 0, sizeof(nca));
 	nca.ca_name = "power";

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.59 2011/01/23 09:44:58 skrll Exp $	*/
+/*	$NetBSD: cpu.h,v 1.60 2011/01/23 21:53:40 skrll Exp $	*/
 /*	$OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $	*/
 /*
  * Copyright (c) 2000-2004 Michael Shalayeff
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -243,41 +243,49 @@ int	clock_intr(void *);
 #include <sys/cpu_data.h>
 /*
  * Note that the alignment of ci_trap_save is important since we want to keep
  * it within a single cache line.  As a result, it must be kept as the first
  * entry within the cpu_info struct.
  */
 struct cpu_info {
 	register_t	ci_trapsave[16];/* the "phys" part of frame */
 	struct cpu_data ci_data;	/* MI per-cpu data */
 #ifndef _KMEMUSER
 #ifdef MULTIPROCESSOR
 	struct	lwp	*ci_curlwp;	/* CPU owner */
 #endif
 	int		ci_cpuid;	/* CPU index (see cpus[] array) */
 	int		ci_mtx_count;
 	int		ci_mtx_oldspl;
 	int		ci_want_resched;
 	volatile int	ci_cpl;
 	volatile int	ci_ipending;	/* The pending interrupts. */
 	u_int		ci_intr_depth;	/* Nonzero iff running an interrupt. */
 	hppa_hpa_t	ci_hpa;
 	register_t	ci_psw;		/* Processor Status Word. */
 	paddr_t		ci_fpu_state;	/* LWP FPU state address, or zero. */
 	u_long		ci_itmr;
 #if defined(MULTIPROCESSOR)
 	struct	lwp	*ci_curlwp;	/* CPU owner */
 	paddr_t		ci_stack;	/* stack for spin up */
 	volatile int	ci_flags;	/* CPU status flags */
 #define	CPUF_PRIMARY	0x0001		/* ... is monarch/primary */
 #define	CPUF_RUNNING	0x0002 		/* ... is running. */
 #endif
 #endif /* !_KMEMUSER */
 } __aligned(64);
 #endif /* _KERNEL || _KMEMUSER */
 #if defined(_KERNEL)
 /*
  * definitions of cpu-dependent requirements
  * referenced in generic code
  */
 #define	cpu_proc_fork(p1, p2)
 @@ -359,26 +367,32 @@ hppa_cpu_hastlbu_p(void)
 void	delay(u_int);
 void	hppa_init(paddr_t, void *);
 void	trap(int, struct trapframe *);
 void	hppa_ras(struct lwp *);
 int	spcopy(pa_space_t, const void *, pa_space_t, void *, size_t);
 int	spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t,
     size_t *);
 int	copy_on_fault(void);
 void	lwp_trampoline(void);
 void	setfunc_trampoline(void);
 int	cpu_dumpsize(void);
 int	cpu_dump(void);
 #ifdef MULTIPROCESSOR
 void	cpu_boot_secondary_processors(void);
 void	cpu_hw_init(void);
 void	cpu_hatch(void);
 #endif
 #endif	/* _KERNEL */
 /*
  * Boot arguments stuff
  */
 #define	BOOTARG_LEN	(PAGE_SIZE)
 #define	BOOTARG_OFF	(0x10000)
 /*
  * CTL_MACHDEP definitions.
  */
 #define	CPU_CONSDEV		1	/* dev_t: console terminal device */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.h,v 1.14 2011/01/23 09:44:59 skrll Exp $	*/
+/*	$NetBSD: machdep.h,v 1.15 2011/01/23 21:53:40 skrll Exp $	*/
 /*
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matthew Fredette.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -34,26 +34,29 @@
  * to the machine-dependent code.  Anything needed by
  * machine-independent code is covered in cpu.h or in
  * other headers.
  */
 /*
  * XXX there is a lot of stuff in various headers under
  * hp700/include and hppa/include, and a lot of one-off
  * `extern's in C files that could probably be moved here.
  */
 #ifdef _KERNEL
 /* The primary (aka monarch) CPU HPA */
 extern hppa_hpa_t hppa_mcpuhpa;
 /*
  * cache configuration, for most machines is the same
  * numbers, so it makes sense to do defines w/ numbers depending
  * on configured CPU types in the kernel.
  */
 extern int icache_stride, icache_line_mask;
 extern int dcache_stride, dcache_line_mask;
 extern vaddr_t vmmap;	/* XXX - See mem.c */
 /* Kernel virtual address space available: */
 extern vaddr_t virtual_start, virtual_end;