 @@ -1,14 +1,14 @@
-/*	$NetBSD: pmap.c,v 1.340 2010/04/26 09:26:25 martin Exp $ */
+/*	$NetBSD: pmap.c,v 1.341 2011/02/15 09:56:32 mrg Exp $ */
 /*
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
 @@ -46,27 +46,27 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)pmap.c	8.4 (Berkeley) 2/5/94
+ *
  */
 /*
  * SPARC physical map management code.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.340 2010/04/26 09:26:25 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.341 2011/02/15 09:56:32 mrg Exp $");
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_sparc_arch.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
 #include <sys/pool.h>
 #include <sys/exec.h>
 #include <sys/core.h>
 @@ -808,40 +808,44 @@ updatepte4m(vaddr_t va, int *pte, int bi
 	swapval = (oldval & ~bic) | bis;
 	swap(vpte, swapval);
 	if (__predict_true(can_lock))
 		mutex_spin_exit(&demap_lock);
 	return (oldval);
+}
 inline void
 setpgt4m(int *ptep, int pte)
+{
 	kpreempt_disable();
 	swap(ptep, pte);
 	kpreempt_enable();
+}
 inline void
 setpgt4m_va(vaddr_t va, int *ptep, int pte, int pageflush, int ctx,
 	    u_int cpuset)
+{
 #if defined(MULTIPROCESSOR)
 	updatepte4m(va, ptep, 0xffffffff, pte, pageflush ? ctx : 0, cpuset);
 #else
 	kpreempt_disable();
 	if (__predict_true(pageflush))
 		tlb_flush_page(va, ctx, 0);
 	setpgt4m(ptep, pte);
 	kpreempt_enable();
 #endif /* MULTIPROCESSOR */
+}
 /* Set the page table entry for va to pte. */
 void
 setpte4m(vaddr_t va, int pte)
+{
 	struct pmap *pm;
 	struct regmap *rp;
 	struct segmap *sp;
 #ifdef DEBUG
 	if (getcontext4m() != 0)
 @@ -6237,43 +6241,43 @@ pmap_enk4m(struct pmap *pm, vaddr_t va,
 	struct regmap *rp;
 	struct segmap *sp;
 	int error = 0;
 #ifdef DEBUG
 	if (va < KERNBASE)
 		panic("pmap_enk4m: can't enter va 0x%lx below KERNBASE", va);
 #endif
 	vr = VA_VREG(va);
 	vs = VA_VSEG(va);
 	rp = &pm->pm_regmap[vr];
 	sp = &rp->rg_segmap[vs];
 	kpreempt_disable();
 	s = splvm();		/* XXX way too conservative */
 	PMAP_LOCK();
 	if (rp->rg_seg_ptps == NULL) /* enter new region */
 		panic("pmap_enk4m: missing kernel region table for va 0x%lx",va);
 	tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
 	if ((tpte & SRMMU_TETYPE) == SRMMU_TEPTE) {
 		/* old mapping exists, and is of the same pa type */
 		if ((tpte & SRMMU_PPNMASK) == (pteproto & SRMMU_PPNMASK)) {
 			/* just changing protection and/or wiring */
 			pmap_changeprot4m(pm, va, prot, flags);
-			PMAP_UNLOCK();
+			error = 0;
-			splx(s);
+			goto out;
 			return (0);
+		}
 		if ((tpte & SRMMU_PGTYPE) == PG_SUN4M_OBMEM) {
 			struct vm_page *opg;
 #ifdef DEBUG
 printf("pmap_enk4m: changing existing va=>pa entry: va 0x%lx, pteproto 0x%x, "
        "oldpte 0x%x\n", va, pteproto, tpte);
 #endif
 			/*
 			 * Switcheroo: changing pa for this va.
 			 * If old pa was managed, remove from pvlist.
 			 * If old page was cached, flush cache.
 			 */
 @@ -6299,26 +6303,27 @@ printf("pmap_enk4m: changing existing va
 	 * If the new mapping is for a managed PA, enter into pvlist.
 	 */
 	if (pg != NULL && (error = pv_link4m(pg, pm, va, &pteproto)) != 0) {
 		if ((flags & PMAP_CANFAIL) != 0)
 			goto out;
 		panic("pmap_enter: cannot allocate PV entry");
+	}
 	setpgt4m(&sp->sg_pte[VA_SUN4M_VPG(va)], pteproto);
 	pm->pm_stats.resident_count++;
 out:
 	PMAP_UNLOCK();
 	splx(s);
 	kpreempt_enable();
 	return (error);
+}
 /* enter new (or change existing) user mapping */
 int
 pmap_enu4m(struct pmap *pm, vaddr_t va, vm_prot_t prot, int flags,
 	   struct vm_page *pg, int pteproto)
+{
 	int vr, vs, *pte, tpte, s;
 	int error = 0;
 	struct regmap *rp;
 	struct segmap *sp;
 	bool owired;
 @@ -6428,29 +6433,28 @@ pmap_enu4m(struct pmap *pm, vaddr_t va,
 		/*
 		 * Might be a change: fetch old pte
 		 */
 		tpte = pte[VA_SUN4M_VPG(va)];
 		if ((tpte & SRMMU_TETYPE) == SRMMU_TEPTE) {
 			/* old mapping exists, and is of the same pa type */
 			if ((tpte & SRMMU_PPNMASK) ==
 			    (pteproto & SRMMU_PPNMASK)) {
 				/* just changing prot and/or wiring */
 				/* caller should call this directly: */
 				pmap_changeprot4m(pm, va, prot, flags);
-				PMAP_UNLOCK();
+				error = 0;
-				splx(s);
+				goto out;
 				return (0);
+			}
 			/*
 			 * Switcheroo: changing pa for this va.
 			 * If old pa was managed, remove from pvlist.
 			 * If old page was cached, flush cache.
 			 */
 #ifdef DEBUG
 			if (pmapdebug & PDB_SWITCHMAP)
 				printf("%s[%d]: pmap_enu: changing existing "
 					"va 0x%x: pte 0x%x=>0x%x\n",
 					curproc->p_comm, curproc->p_pid,
 					(int)va, tpte, pteproto);
 #endif
 @@ -6541,26 +6545,27 @@ void
 pmap_kremove4m(vaddr_t va, vsize_t len)
+{
 	struct pmap *pm = pmap_kernel();
 	struct regmap *rp;
 	struct segmap *sp;
 	vaddr_t endva, nva;
 	int vr, vs;
 	int tpte, perpage, npg, s;
 	/*
 	 * The kernel pmap doesn't need to be locked, but the demap lock
 	 * in updatepte() requires interrupt protection.
 	 */
 	kpreempt_disable();
 	s = splvm();
 	endva = va + len;
 	for (; va < endva; va = nva) {
 		/* do one virtual segment at a time */
 		vr = VA_VREG(va);
 		vs = VA_VSEG(va);
 		nva = VSTOVA(vr, vs + 1);
 		if (nva == 0 || nva > endva) {
 			nva = endva;
+		}
 		rp = &pm->pm_regmap[vr];
 @@ -6586,116 +6591,122 @@ pmap_kremove4m(vaddr_t va, vsize_t len)
 			if ((tpte & SRMMU_TETYPE) != SRMMU_TEPTE)
 				continue;
 			if ((tpte & SRMMU_PGTYPE) == PG_SUN4M_OBMEM) {
 				/* if cacheable, flush page as needed */
 				if (perpage && (tpte & SRMMU_PG_C))
 					cache_flush_page(va, 0);
+			}
 			setpgt4m_va(va, &sp->sg_pte[VA_SUN4M_VPG(va)],
 				 SRMMU_TEINVALID, 1, 0, CPUSET_ALL);
+		}
+	}
 	splx(s);
 	kpreempt_enable();
+}
 /*
  * Change protection on a range of kernel addresses.
  */
 void
 pmap_kprotect4m(vaddr_t va, vsize_t size, vm_prot_t prot)
+{
 	struct pmap *pm = pmap_kernel();
 	int pte, newprot, s;
 	struct regmap *rp;
 	struct segmap *sp;
 	size = roundup(size,NBPG);
 	newprot = pte_kprot4m(prot);
 	/*
 	 * The kernel pmap doesn't need to be locked, but the demap lock
 	 * in updatepte() requires interrupt protection.
 	 */
 	kpreempt_disable();
 	s = splvm();
 	while (size > 0) {
 		rp = &pm->pm_regmap[VA_VREG(va)];
 		sp = &rp->rg_segmap[VA_VSEG(va)];
 		pte = sp->sg_pte[VA_SUN4M_VPG(va)];
 		/*
 		 * Flush cache if page has been referenced to
 		 * avoid stale protection bits in the cache tags.
 		 */
 		if ((pte & (SRMMU_PG_C|SRMMU_PGTYPE)) ==
 		    (SRMMU_PG_C|PG_SUN4M_OBMEM))
 			cache_flush_page(va, 0);
 		setpgt4m_va(va, &sp->sg_pte[VA_SUN4M_VPG(va)],
 			 (pte & ~SRMMU_PROT_MASK) | newprot,
 , pm->pm_ctxnum, PMAP_CPUSET(pm));
 		va += NBPG;
 		size -= NBPG;
+	}
 	splx(s);
 	kpreempt_enable();
+}
 #endif /* SUN4M || SUN4D */
 /*
  * Clear the wiring attribute for a map/virtual-address pair.
  */
 /* ARGSUSED */
 void
 pmap_unwire(struct pmap *pm, vaddr_t va)
+{
 	int vr, vs, *ptep;
 	struct regmap *rp;
 	struct segmap *sp;
 	bool owired;
 	kpreempt_disable();
 	vr = VA_VREG(va);
 	vs = VA_VSEG(va);
 	rp = &pm->pm_regmap[vr];
 	sp = &rp->rg_segmap[vs];
 	owired = false;
 	if (CPU_HAS_SUNMMU) {
 		ptep = &sp->sg_pte[VA_VPG(va)];
 		owired = *ptep & PG_WIRED;
 		*ptep &= ~PG_WIRED;
+	}
 	if (CPU_HAS_SRMMU) {
 		owired = sp->sg_wiremap & (1 << VA_SUN4M_VPG(va));
 		sp->sg_wiremap &= ~(1 << VA_SUN4M_VPG(va));
+	}
 	if (!owired) {
 		pmap_stats.ps_useless_changewire++;
 		return;
 		kpreempt_enable();
+	}
 	pm->pm_stats.wired_count--;
 #if defined(SUN4) || defined(SUN4C)
 	if (CPU_HAS_SUNMMU && --sp->sg_nwired <= 0) {
 #ifdef DIAGNOSTIC
 		if (sp->sg_nwired > sp->sg_npte || sp->sg_nwired < 0)
 			panic("pmap_unwire: pm %p, va %lx: nleft=%d, nwired=%d",
 				pm, va, sp->sg_npte, sp->sg_nwired);
 #endif
 		if (sp->sg_pmeg != seginval)
 			mmu_pmeg_unlock(sp->sg_pmeg);
+	}
 #endif /* SUN4 || SUN4C */
 	kpreempt_enable();
+}
 /*
  * Extract the physical page address associated
  * with the given map/virtual_address pair.
  * GRR, the vm code knows; we should not have to do this!
  */
 #if defined(SUN4) || defined(SUN4C)
 bool
 pmap_extract4_4c(struct pmap *pm, vaddr_t va, paddr_t *pap)
+{
 	int vr, vs;
 @@ -7078,26 +7089,27 @@ pmap_copy_page4_4c(paddr_t src, paddr_t
 /*
  * Fill the given MI physical page with zero bytes.
+ *
  * We avoid stomping on the cache.
  * XXX	might be faster to use destination's context and allow cache to fill?
  */
 void
 pmap_zero_page4m(paddr_t pa)
+{
 	struct vm_page *pg;
 	void *va;
 	int pte;
 	kpreempt_disable();
 	if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
 		/*
 		 * The following VAC flush might not be necessary since the
 		 * page is being cleared because it is about to be allocated,
 		 * i.e., is in use by no one.
 		 * In the case of a physical cache, a flush (or just an
 		 * invalidate, if possible) is usually necessary when using
 		 * uncached access to clear it.
 		 */
 		if (CACHEINFO.c_vactype != VAC_NONE)
 			pv_flushcache4m(pg);
 		else
 			pcache_flush_page(pa, 1);
 @@ -7105,106 +7117,112 @@ pmap_zero_page4m(paddr_t pa)
 	pte = SRMMU_TEPTE | PPROT_N_RWX | (pa >> SRMMU_PPNPASHIFT);
 	if (cpuinfo.flags & CPUFLG_CACHE_MANDATORY)
 		pte |= SRMMU_PG_C;
 	va = cpuinfo.vpage[0];
 	setpgt4m(cpuinfo.vpage_pte[0], pte);
 	qzero(va, NBPG);
 	/*
 	 * Remove temporary mapping (which is kernel-only, so the
 	 * context used for TLB flushing does not matter)
 	 */
 	sp_tlb_flush((int)va, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[0], SRMMU_TEINVALID);
 	kpreempt_enable();
+}
 /*
  * Viking/MXCC specific version of pmap_zero_page
  */
 void
 pmap_zero_page_viking_mxcc(paddr_t pa)
+{
 	u_int offset;
 	u_int stream_data_addr = MXCC_STREAM_DATA;
 	uint64_t v = (uint64_t)pa;
 	kpreempt_disable();
 	/* Load MXCC stream data register with 0 (bottom 32 bytes only) */
 	stda(stream_data_addr+0, ASI_CONTROL, 0);
 	stda(stream_data_addr+8, ASI_CONTROL, 0);
 	stda(stream_data_addr+16, ASI_CONTROL, 0);
 	stda(stream_data_addr+24, ASI_CONTROL, 0);
 	/* Then write the stream data register to each block in the page */
 	v |= MXCC_STREAM_C;
 	for (offset = 0; offset < NBPG; offset += MXCC_STREAM_BLKSZ) {
 		stda(MXCC_STREAM_DST, ASI_CONTROL, v | offset);
+	}
 	kpreempt_enable();
+}
 /*
  * HyperSPARC/RT625 specific version of pmap_zero_page
  */
 void
 pmap_zero_page_hypersparc(paddr_t pa)
+{
 	struct vm_page *pg;
 	void *va;
 	int pte;
 	int offset;
 	kpreempt_disable();
 	/*
 	 * We still have to map the page, since ASI_BLOCKFILL
 	 * takes virtual addresses. This also means we have to
 	 * consider cache aliasing; therefore we still need
 	 * to flush the cache here. All we gain is the speed-up
 	 * in zero-fill loop itself..
 	 */
 	if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
 		/*
 		 * The following might not be necessary since the page
 		 * is being cleared because it is about to be allocated,
 		 * i.e., is in use by no one.
 		 */
 		if (CACHEINFO.c_vactype != VAC_NONE)
 			pv_flushcache4m(pg);
+	}
 	pte = SRMMU_TEPTE | SRMMU_PG_C | PPROT_N_RWX | (pa >> SRMMU_PPNPASHIFT);
 	va = cpuinfo.vpage[0];
 	setpgt4m(cpuinfo.vpage_pte[0], pte);
 	for (offset = 0; offset < NBPG; offset += 32) {
 		sta((char *)va + offset, ASI_BLOCKFILL, 0);
+	}
 	/* Remove temporary mapping */
 	sp_tlb_flush((int)va, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[0], SRMMU_TEINVALID);
 	kpreempt_enable();
+}
 /*
  * Copy the given MI physical source page to its destination.
+ *
  * We avoid stomping on the cache as above (with same `XXX' note).
  * We must first flush any write-back cache for the source page.
  * We go ahead and stomp on the kernel's virtual cache for the
  * source page, since the cache can read memory MUCH faster than
  * the processor.
  */
 void
 pmap_copy_page4m(paddr_t src, paddr_t dst)
+{
 	struct vm_page *pg;
 	void *sva, *dva;
 	int spte, dpte;
 	kpreempt_disable();
 	if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) {
 		if (CACHEINFO.c_vactype == VAC_WRITEBACK)
 			pv_flushcache4m(pg);
+	}
 	spte = SRMMU_TEPTE | SRMMU_PG_C | PPROT_N_RX |
 		(src >> SRMMU_PPNPASHIFT);
 	if ((pg = PHYS_TO_VM_PAGE(dst)) != NULL) {
 		/* similar `might not be necessary' comment applies */
 		if (CACHEINFO.c_vactype != VAC_NONE)
 			pv_flushcache4m(pg);
 		else
 @@ -7215,60 +7233,64 @@ pmap_copy_page4m(paddr_t src, paddr_t ds
 	if (cpuinfo.flags & CPUFLG_CACHE_MANDATORY)
 		dpte |= SRMMU_PG_C;
 	sva = cpuinfo.vpage[0];
 	dva = cpuinfo.vpage[1];
 	setpgt4m(cpuinfo.vpage_pte[0], spte);
 	setpgt4m(cpuinfo.vpage_pte[1], dpte);
 	qcopy(sva, dva, NBPG);	/* loads cache, so we must ... */
 	cpuinfo.sp_vcache_flush_page((vaddr_t)sva, getcontext4m());
 	sp_tlb_flush((int)sva, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[0], SRMMU_TEINVALID);
 	sp_tlb_flush((int)dva, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[1], SRMMU_TEINVALID);
 	kpreempt_enable();
+}
 /*
  * Viking/MXCC specific version of pmap_copy_page
  */
 void
 pmap_copy_page_viking_mxcc(paddr_t src, paddr_t dst)
+{
 	u_int offset;
 	uint64_t v1 = (uint64_t)src;
 	uint64_t v2 = (uint64_t)dst;
 	kpreempt_disable();
 	/* Enable cache-coherency */
 	v1 |= MXCC_STREAM_C;
 	v2 |= MXCC_STREAM_C;
 	/* Copy through stream data register */
 	for (offset = 0; offset < NBPG; offset += MXCC_STREAM_BLKSZ) {
 		stda(MXCC_STREAM_SRC, ASI_CONTROL, v1 | offset);
 		stda(MXCC_STREAM_DST, ASI_CONTROL, v2 | offset);
+	}
 	kpreempt_enable();
+}
 /*
  * HyperSPARC/RT625 specific version of pmap_copy_page
  */
 void
 pmap_copy_page_hypersparc(paddr_t src, paddr_t dst)
+{
 	struct vm_page *pg;
 	void *sva, *dva;
 	int spte, dpte;
 	int offset;
 	kpreempt_disable();
 	/*
 	 * We still have to map the pages, since ASI_BLOCKCOPY
 	 * takes virtual addresses. This also means we have to
 	 * consider cache aliasing; therefore we still need
 	 * to flush the cache here. All we gain is the speed-up
 	 * in copy loop itself..
 	 */
 	if ((pg = PHYS_TO_VM_PAGE(src)) != NULL) {
 		if (CACHEINFO.c_vactype == VAC_WRITEBACK)
 			pv_flushcache4m(pg);
+	}
 @@ -7287,26 +7309,27 @@ pmap_copy_page_hypersparc(paddr_t src, p
 	sva = cpuinfo.vpage[0];
 	dva = cpuinfo.vpage[1];
 	setpgt4m(cpuinfo.vpage_pte[0], spte);
 	setpgt4m(cpuinfo.vpage_pte[1], dpte);
 	for (offset = 0; offset < NBPG; offset += 32) {
 		sta((char *)dva + offset, ASI_BLOCKCOPY, (char *)sva + offset);
+	}
 	sp_tlb_flush((int)sva, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[0], SRMMU_TEINVALID);
 	sp_tlb_flush((int)dva, 0, ASI_SRMMUFP_L3);
 	setpgt4m(cpuinfo.vpage_pte[1], SRMMU_TEINVALID);
 	kpreempt_enable();
+}
 #endif /* SUN4M || SUN4D */
 /*
  * Turn off cache for a given (va, number of pages).
+ *
  * We just assert PG_NC for each PTE; the addresses must reside
  * in locked kernel space.  A cache flush is also done.
  */
 void
 kvm_uncache(char *va, int npages)
+{
 	struct vm_page *pg;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: timer_sun4m.c,v 1.24 2011/02/14 10:21:05 mrg Exp $	*/
+/*	$NetBSD: timer_sun4m.c,v 1.25 2011/02/15 09:56:32 mrg Exp $	*/
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
  * Copyright (c) 1994 Gordon W. Ross
  * Copyright (c) 1993 Adam Glass
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College. All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
 @@ -48,27 +48,27 @@
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)clock.c	8.1 (Berkeley) 6/11/93
  */
 /*
  * Sun4m timer support.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: timer_sun4m.c,v 1.24 2011/02/14 10:21:05 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: timer_sun4m.c,v 1.25 2011/02/15 09:56:32 mrg Exp $");
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/systm.h>
 #include <sys/cpu.h>
 #include <machine/autoconf.h>
 #include <machine/bus.h>
 #include <sparc/sparc/vaddrs.h>
 #include <sparc/sparc/cpuvar.h>
 #include <sparc/sparc/timerreg.h>
 @@ -90,82 +90,88 @@ timer_init_4m(void)
 	int n;
 	timerreg4m->t_limit = tmr_ustolim4m(tick);
 	for (CPU_INFO_FOREACH(n, cpi)) {
 		cpi->counterreg_4m->t_limit = tmr_ustolim4m(statint);
+	}
 	icr_si_bic(SINTR_T);
+}
 void
 schedintr_4m(void *v)
+{
 	kpreempt_disable();
 #ifdef MULTIPROCESSOR
 	/*
 	 * We call hardclock() here so that we make sure it is called on
 	 * all CPUs.  This function ends up being called on sun4m systems
 	 * every tick.
 	 */
 	if (!CPU_IS_PRIMARY(curcpu()))
 		hardclock(v);
 	/*
 	 * The factor 8 is only valid for stathz==100.
 	 * See also clock.c
 	 */
 	if ((++cpuinfo.ci_schedstate.spc_schedticks & 7) == 0 && schedhz != 0)
 #endif
 		schedclock(curlwp);
 	kpreempt_enable();
+}
 /*
  * Level 10 (clock) interrupts from system counter.
  */
 int
 clockintr_4m(void *cap)
+{
 	KASSERT(CPU_IS_PRIMARY(curcpu()));
 	/*
 	 * XXX this needs to be fixed in a more general way
 	 * problem is that the kernel enables interrupts and THEN
 	 * sets up clocks. In between there's an opportunity to catch
 	 * a timer interrupt - if we call hardclock() at that point we'll
 	 * panic
 	 * so for now just bail when cold
+	 *
 	 * For MP, we defer calling hardclock() to the schedintr so
 	 * that we call it on all cpus.
 	 */
 	kpreempt_disable();
 	if (cold)
 		return 0;
 	/* read the limit register to clear the interrupt */
 	*((volatile int *)&timerreg4m->t_limit);
 	tickle_tc();
 	hardclock((struct clockframe *)cap);
 	kpreempt_enable();
 	return (1);
+}
 /*
  * Level 14 (stat clock) interrupts from processor counter.
  */
 int
 statintr_4m(void *cap)
+{
 	struct clockframe *frame = cap;
 	u_long newint;
 	kpreempt_disable();
 	/* read the limit register to clear the interrupt */
 	*((volatile int *)&counterreg4m->t_limit);
 	statclock(frame);
 	/*
 	 * Compute new randomized interval.
 	 */
 	newint = new_interval();
 	/*
 	 * Use the `non-resetting' limit register, so we don't
 	 * loose the counter ticks that happened since this
 @@ -184,26 +190,27 @@ statintr_4m(void *cap)
 			/* No need to schedule a soft interrupt */
 			spllowerschedclock();
 			schedintr_4m(cap);
 		} else {
 			/*
 			 * We're interrupting a thread that may have the
 			 * scheduler lock; run schedintr_4m() on this CPU later.
 			 */
 			raise_ipi(&cpuinfo, IPL_SCHED); /* sched_cookie->pil */
+		}
 #if !defined(MULTIPROCESSOR)
+	}
 #endif
 	kpreempt_enable();
 	return (1);
+}
 void
 timerattach_obio_4m(struct device *parent, struct device *self, void *aux)
+{
 	union obio_attach_args *uoba = aux;
 	struct sbus_attach_args *sa = &uoba->uoba_sbus;
 	struct cpu_info *cpi;
 	bus_space_handle_t bh;
 	int i, n;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: intr.c,v 1.112 2011/02/15 09:05:14 mrg Exp $ */
+/*	$NetBSD: intr.c,v 1.113 2011/02/15 09:56:32 mrg Exp $ */
 /*
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
 @@ -31,27 +31,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)intr.c	8.3 (Berkeley) 11/11/93
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.112 2011/02/15 09:05:14 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.113 2011/02/15 09:56:32 mrg Exp $");
 #include "opt_multiprocessor.h"
 #include "opt_sparc_arch.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/cpu.h>
 #include <sys/intr.h>
 #include <sys/simplelock.h>
 #include <uvm/uvm_extern.h>
 @@ -343,43 +343,47 @@ nmi_soft(struct trapframe *tf)
 #if defined(MULTIPROCESSOR)
 /*
  * Respond to an xcall() request from another CPU.
+ *
  * This is also called directly from xcall() if we notice an
  * incoming message while we're waiting to grab the xpmsg_lock.
  * We pass the address of xcallintr() itself to indicate that
  * this is not a real interrupt.
  */
 void
 xcallintr(void *v)
+{
 	kpreempt_disable();
 	/* Tally */
 	if (v != xcallintr)
 		cpuinfo.ci_sintrcnt[13].ev_count++;
 	/* notyet - cpuinfo.msg.received = 1; */
 	switch (cpuinfo.msg.tag) {
 	case XPMSG_FUNC:
+	    {
 		volatile struct xpmsg_func *p = &cpuinfo.msg.u.xpmsg_func;
 		if (p->func)
 			(*p->func)(p->arg0, p->arg1, p->arg2);
 		break;
+	    }
+	}
 	cpuinfo.msg.tag = 0;
 	cpuinfo.msg.complete = 1;
 	kpreempt_enable();
+}
 #endif /* MULTIPROCESSOR */
 #endif /* SUN4M || SUN4D */
 #ifdef MSIIEP
 /*
  * It's easier to make this separate so that not to further obscure
  * SUN4M case with more ifdefs.  There's no common functionality
  * anyway.
  */
 #include <sparc/sparc/msiiepreg.h>
 @@ -833,16 +837,21 @@ intr_biglock_wrapper(void *vp)
 	KERNEL_LOCK(1, NULL);
 	ret = (*ih->ih_realfun)(ih->ih_realarg);
 	KERNEL_UNLOCK_ONE(NULL);
 	return ret;
+}
 #endif /* MULTIPROCESSOR */
 bool
 cpu_intr_p(void)
+{
 	int idepth;
 	kpreempt_disable();
 	idepth = curcpu()->ci_idepth;
 	kpreempt_enable();
-	return curcpu()->ci_idepth != 0;
+	return idepth != 0;
+}