| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: acpi_cpu_md.c,v 1.39 2011/02/15 17:50:46 jruoho Exp $ */ | | 1 | /* $NetBSD: acpi_cpu_md.c,v 1.40 2011/02/24 13:19:36 jmcneill Exp $ */ |
2 | | | 2 | |
3 | /*- | | 3 | /*- |
4 | * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> | | 4 | * Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi> |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Redistribution and use in source and binary forms, with or without | | 7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions | | 8 | * modification, are permitted provided that the following conditions |
9 | * are met: | | 9 | * are met: |
10 | * | | 10 | * |
11 | * 1. Redistributions of source code must retain the above copyright | | 11 | * 1. Redistributions of source code must retain the above copyright |
12 | * notice, this list of conditions and the following disclaimer. | | 12 | * notice, this list of conditions and the following disclaimer. |
13 | * 2. Redistributions in binary form must reproduce the above copyright | | 13 | * 2. Redistributions in binary form must reproduce the above copyright |
14 | * notice, this list of conditions and the following disclaimer in the | | 14 | * notice, this list of conditions and the following disclaimer in the |
| @@ -17,27 +17,27 @@ | | | @@ -17,27 +17,27 @@ |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | | 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | | 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | | 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | | 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | | 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | | 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | | 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | | 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | | 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
27 | * SUCH DAMAGE. | | 27 | * SUCH DAMAGE. |
28 | */ | | 28 | */ |
29 | #include <sys/cdefs.h> | | 29 | #include <sys/cdefs.h> |
30 | __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.39 2011/02/15 17:50:46 jruoho Exp $"); | | 30 | __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md.c,v 1.40 2011/02/24 13:19:36 jmcneill Exp $"); |
31 | | | 31 | |
32 | #include <sys/param.h> | | 32 | #include <sys/param.h> |
33 | #include <sys/bus.h> | | 33 | #include <sys/bus.h> |
34 | #include <sys/kcore.h> | | 34 | #include <sys/kcore.h> |
35 | #include <sys/sysctl.h> | | 35 | #include <sys/sysctl.h> |
36 | #include <sys/xcall.h> | | 36 | #include <sys/xcall.h> |
37 | | | 37 | |
38 | #include <x86/cpu.h> | | 38 | #include <x86/cpu.h> |
39 | #include <x86/cpufunc.h> | | 39 | #include <x86/cpufunc.h> |
40 | #include <x86/cputypes.h> | | 40 | #include <x86/cputypes.h> |
41 | #include <x86/cpuvar.h> | | 41 | #include <x86/cpuvar.h> |
42 | #include <x86/cpu_msr.h> | | 42 | #include <x86/cpu_msr.h> |
43 | #include <x86/machdep.h> | | 43 | #include <x86/machdep.h> |
| @@ -50,27 +50,27 @@ __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md. | | | @@ -50,27 +50,27 @@ __KERNEL_RCSID(0, "$NetBSD: acpi_cpu_md. |
50 | | | 50 | |
51 | #include <machine/acpi_machdep.h> | | 51 | #include <machine/acpi_machdep.h> |
52 | | | 52 | |
53 | /* | | 53 | /* |
54 | * AMD C1E. | | 54 | * AMD C1E. |
55 | */ | | 55 | */ |
56 | #define MSR_CMPHALT 0xc0010055 | | 56 | #define MSR_CMPHALT 0xc0010055 |
57 | | | 57 | |
58 | #define MSR_CMPHALT_SMI __BIT(27) | | 58 | #define MSR_CMPHALT_SMI __BIT(27) |
59 | #define MSR_CMPHALT_C1E __BIT(28) | | 59 | #define MSR_CMPHALT_C1E __BIT(28) |
60 | #define MSR_CMPHALT_BMSTS __BIT(29) | | 60 | #define MSR_CMPHALT_BMSTS __BIT(29) |
61 | | | 61 | |
62 | /* | | 62 | /* |
63 | * AMD families 10h and 11h. | | 63 | * AMD families 10h, 11h, and 14h |
64 | */ | | 64 | */ |
65 | #define MSR_10H_LIMIT 0xc0010061 | | 65 | #define MSR_10H_LIMIT 0xc0010061 |
66 | #define MSR_10H_CONTROL 0xc0010062 | | 66 | #define MSR_10H_CONTROL 0xc0010062 |
67 | #define MSR_10H_STATUS 0xc0010063 | | 67 | #define MSR_10H_STATUS 0xc0010063 |
68 | #define MSR_10H_CONFIG 0xc0010064 | | 68 | #define MSR_10H_CONFIG 0xc0010064 |
69 | | | 69 | |
70 | /* | | 70 | /* |
71 | * AMD family 0Fh. | | 71 | * AMD family 0Fh. |
72 | */ | | 72 | */ |
73 | #define MSR_0FH_CONTROL 0xc0010041 | | 73 | #define MSR_0FH_CONTROL 0xc0010041 |
74 | #define MSR_0FH_STATUS 0xc0010042 | | 74 | #define MSR_0FH_STATUS 0xc0010042 |
75 | | | 75 | |
76 | #define MSR_0FH_STATUS_CFID __BITS( 0, 5) | | 76 | #define MSR_0FH_STATUS_CFID __BITS( 0, 5) |
| @@ -261,37 +261,40 @@ acpicpu_md_quirks(void) | | | @@ -261,37 +261,40 @@ acpicpu_md_quirks(void) |
261 | case 0x0f: | | 261 | case 0x0f: |
262 | | | 262 | |
263 | if ((regs[3] & CPUID_APM_FID) == 0) | | 263 | if ((regs[3] & CPUID_APM_FID) == 0) |
264 | break; | | 264 | break; |
265 | | | 265 | |
266 | if ((regs[3] & CPUID_APM_VID) == 0) | | 266 | if ((regs[3] & CPUID_APM_VID) == 0) |
267 | break; | | 267 | break; |
268 | | | 268 | |
269 | val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; | | 269 | val |= ACPICPU_FLAG_P_FFH | ACPICPU_FLAG_P_FIDVID; |
270 | break; | | 270 | break; |
271 | | | 271 | |
272 | case 0x10: | | 272 | case 0x10: |
273 | case 0x11: | | 273 | case 0x11: |
| | | 274 | val |= ACPICPU_FLAG_C_C1E; |
| | | 275 | /* FALLTHROUGH */ |
| | | 276 | |
| | | 277 | case 0x14: /* AMD Fusion */ |
274 | | | 278 | |
275 | if ((regs[3] & CPUID_APM_TSC) != 0) | | 279 | if ((regs[3] & CPUID_APM_TSC) != 0) |
276 | val &= ~ACPICPU_FLAG_C_TSC; | | 280 | val &= ~ACPICPU_FLAG_C_TSC; |
277 | | | 281 | |
278 | if ((regs[3] & CPUID_APM_HWP) != 0) | | 282 | if ((regs[3] & CPUID_APM_HWP) != 0) |
279 | val |= ACPICPU_FLAG_P_FFH; | | 283 | val |= ACPICPU_FLAG_P_FFH; |
280 | | | 284 | |
281 | if ((regs[3] & CPUID_APM_CPB) != 0) | | 285 | if ((regs[3] & CPUID_APM_CPB) != 0) |
282 | val |= ACPICPU_FLAG_P_TURBO; | | 286 | val |= ACPICPU_FLAG_P_TURBO; |
283 | | | 287 | |
284 | val |= ACPICPU_FLAG_C_C1E; | | | |
285 | break; | | 288 | break; |
286 | } | | 289 | } |
287 | | | 290 | |
288 | break; | | 291 | break; |
289 | } | | 292 | } |
290 | | | 293 | |
291 | /* | | 294 | /* |
292 | * There are several erratums for PIIX4. | | 295 | * There are several erratums for PIIX4. |
293 | */ | | 296 | */ |
294 | if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) | | 297 | if (pci_find_device(&pa, acpicpu_md_quirks_piix4) != 0) |
295 | val |= ACPICPU_FLAG_PIIX4; | | 298 | val |= ACPICPU_FLAG_PIIX4; |
296 | | | 299 | |
297 | return val; | | 300 | return val; |
| @@ -485,26 +488,27 @@ acpicpu_md_pstate_pss(struct acpicpu_sof | | | @@ -485,26 +488,27 @@ acpicpu_md_pstate_pss(struct acpicpu_sof |
485 | | | 488 | |
486 | if (family == 0xf) | | 489 | if (family == 0xf) |
487 | family += CPUID2EXTFAMILY(ci->ci_signature); | | 490 | family += CPUID2EXTFAMILY(ci->ci_signature); |
488 | | | 491 | |
489 | switch (family) { | | 492 | switch (family) { |
490 | | | 493 | |
491 | case 0x0f: | | 494 | case 0x0f: |
492 | msr.ps_control_addr = MSR_0FH_CONTROL; | | 495 | msr.ps_control_addr = MSR_0FH_CONTROL; |
493 | msr.ps_status_addr = MSR_0FH_STATUS; | | 496 | msr.ps_status_addr = MSR_0FH_STATUS; |
494 | break; | | 497 | break; |
495 | | | 498 | |
496 | case 0x10: | | 499 | case 0x10: |
497 | case 0x11: | | 500 | case 0x11: |
| | | 501 | case 0x14: /* AMD Fusion */ |
498 | msr.ps_control_addr = MSR_10H_CONTROL; | | 502 | msr.ps_control_addr = MSR_10H_CONTROL; |
499 | msr.ps_control_mask = __BITS(0, 2); | | 503 | msr.ps_control_mask = __BITS(0, 2); |
500 | | | 504 | |
501 | msr.ps_status_addr = MSR_10H_STATUS; | | 505 | msr.ps_status_addr = MSR_10H_STATUS; |
502 | msr.ps_status_mask = __BITS(0, 2); | | 506 | msr.ps_status_mask = __BITS(0, 2); |
503 | break; | | 507 | break; |
504 | | | 508 | |
505 | default: | | 509 | default: |
506 | | | 510 | |
507 | if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) | | 511 | if ((sc->sc_flags & ACPICPU_FLAG_P_XPSS) == 0) |
508 | return EOPNOTSUPP; | | 512 | return EOPNOTSUPP; |
509 | } | | 513 | } |
510 | | | 514 | |