| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: locore.S,v 1.177 2011/02/20 16:58:33 matt Exp $ */ | | 1 | /* $NetBSD: locore.S,v 1.178 2011/02/24 15:25:07 tsutsui Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 1992, 1993 | | 4 | * Copyright (c) 1992, 1993 |
5 | * The Regents of the University of California. All rights reserved. | | 5 | * The Regents of the University of California. All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to Berkeley by | | 7 | * This code is derived from software contributed to Berkeley by |
8 | * Digital Equipment Corporation and Ralph Campbell. | | 8 | * Digital Equipment Corporation and Ralph Campbell. |
9 | * | | 9 | * |
10 | * Redistribution and use in source and binary forms, with or without | | 10 | * Redistribution and use in source and binary forms, with or without |
11 | * modification, are permitted provided that the following conditions | | 11 | * modification, are permitted provided that the following conditions |
12 | * are met: | | 12 | * are met: |
13 | * 1. Redistributions of source code must retain the above copyright | | 13 | * 1. Redistributions of source code must retain the above copyright |
14 | * notice, this list of conditions and the following disclaimer. | | 14 | * notice, this list of conditions and the following disclaimer. |
| @@ -611,33 +611,31 @@ XNESTED(mips_fpu_trap) | | | @@ -611,33 +611,31 @@ XNESTED(mips_fpu_trap) |
611 | | | 611 | |
612 | REG_PROLOGUE | | 612 | REG_PROLOGUE |
613 | REG_L a2, TF_REG_CAUSE(a1) | | 613 | REG_L a2, TF_REG_CAUSE(a1) |
614 | REG_EPILOGUE | | 614 | REG_EPILOGUE |
615 | | | 615 | |
616 | cfc1 t0, MIPS_FPU_CSR # stall til FP done | | 616 | cfc1 t0, MIPS_FPU_CSR # stall til FP done |
617 | cfc1 t0, MIPS_FPU_CSR # now get status | | 617 | cfc1 t0, MIPS_FPU_CSR # now get status |
618 | nop | | 618 | nop |
619 | sll t2, t0, (31 - 17) # unimplemented operation? | | 619 | sll t2, t0, (31 - 17) # unimplemented operation? |
620 | bgez t2, 3f # no, normal trap | | 620 | bgez t2, 3f # no, normal trap |
621 | nop | | 621 | nop |
622 | | | 622 | |
623 | /* | | 623 | /* |
624 | * We got an unimplemented operation trap so | | 624 | * We received an unimplemented operation trap so |
625 | * We received an unimplemented operation trap. | | 625 | * fetch the instruction and emulate the instruction. |
626 | * | | 626 | * |
627 | * We check whether it's an unimplemented FP instruction here rather | | 627 | * We check whether it's an unimplemented FP instruction here rather |
628 | * than invoking MachEmulateInst(), since it is faster. | | 628 | * than invoking MachEmulateInst(), since it is faster. |
629 | * | | | |
630 | * fetch the instruction and emulate the instruction. | | | |
631 | */ | | 629 | */ |
632 | bgez a2, 1f # Check the branch delay bit. | | 630 | bgez a2, 1f # Check the branch delay bit. |
633 | nop | | 631 | nop |
634 | /* | | 632 | /* |
635 | * The instruction is in the branch delay slot. | | 633 | * The instruction is in the branch delay slot. |
636 | */ | | 634 | */ |
637 | b 2f | | 635 | b 2f |
638 | INT_L a0, 4(a0) # a0 = coproc instruction | | 636 | INT_L a0, 4(a0) # a0 = coproc instruction |
639 | /* | | 637 | /* |
640 | * This is not in the branch delay slot so calculate the resulting | | 638 | * This is not in the branch delay slot so calculate the resulting |
641 | * PC (epc + 4) into v0 and continue to MachEmulateFP(). | | 639 | * PC (epc + 4) into v0 and continue to MachEmulateFP(). |
642 | */ | | 640 | */ |
643 | 1: | | 641 | 1: |