Sat May 28 14:40:13 2011 UTC ()
Since we mostly use RAS (even if we have LL/SC), need to check for lock ras
addresses even on ll/sc capable CPUs.


(matt)
diff -r1.48 -r1.49 src/sys/arch/mips/mips/mipsX_subr.S
cvs diff -r1.48 -r1.49 src/sys/arch/mips/mips/mipsX_subr.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/mipsX_subr.S 2011/05/07 18:16:54 1.48
+++ src/sys/arch/mips/mips/mipsX_subr.S 2011/05/28 14:40:13 1.49
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: mipsX_subr.S,v 1.48 2011/05/07 18:16:54 tsutsui Exp $ */ 1/* $NetBSD: mipsX_subr.S,v 1.49 2011/05/28 14:40:13 matt Exp $ */
2 2
3/* 3/*
4 * Copyright 2002 Wasabi Systems, Inc. 4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Simon Burge for Wasabi Systems, Inc. 7 * Written by Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -698,39 +698,37 @@ MIPSX(kern_return): @@ -698,39 +698,37 @@ MIPSX(kern_return):
698 INT_L t2, TF_BASE+TF_PPL(sp) # get saved priority level 698 INT_L t2, TF_BASE+TF_PPL(sp) # get saved priority level
699 PTR_L t0, L_CPU(MIPS_CURLWP) 699 PTR_L t0, L_CPU(MIPS_CURLWP)
700 INT_L t1, CPU_INFO_CPL(t0) # get current priority level 700 INT_L t1, CPU_INFO_CPL(t0) # get current priority level
70111: bne t2, t1, 11b # loop forever if unequal 70111: bne t2, t1, 11b # loop forever if unequal
702 nop 702 nop
703 703
704 /* 704 /*
705 * Verify our existing interrupt level. 705 * Verify our existing interrupt level.
706 */ 706 */
707 jal _C_LABEL(splcheck) 707 jal _C_LABEL(splcheck)
708 nop 708 nop
709#endif /* PARANOIA */ 709#endif /* PARANOIA */
710 710
711#ifdef notyet 
712 /* 711 /*
713 * Check for kernel restartable atomic sequences. 712 * Check for kernel restartable atomic sequences.
714 */ 713 */
715 PTR_LA t0, _C_LABEL(_lock_ras_start) 714 PTR_LA t0, _C_LABEL(_lock_ras_start)
716 li t1, -MIPS_LOCK_RAS_SIZE 715 li t1, -MIPS_LOCK_RAS_SIZE
717 and t1, k1 716 and t1, k1
718 bne t1, t0, 1f # exception PC in RAS area? 717 bne t1, t0, 1f # exception PC in RAS area?
719 nop 718 nop
720 jal _C_LABEL(_restart_lock_ras) # fix the pc (k1) 719 jal _C_LABEL(_restart_lock_ras) # fix the pc (k1)
721 nop 720 nop
7221: 7211:
723#endif 
724 722
725 _MTC0 k1, MIPS_COP_0_EXC_PC # set return address 723 _MTC0 k1, MIPS_COP_0_EXC_PC # set return address
726 COP0_SYNC 724 COP0_SYNC
727 725
728 REG_L AT, TF_BASE+TF_REG_AST(sp) 726 REG_L AT, TF_BASE+TF_REG_AST(sp)
729 REG_L v0, TF_BASE+TF_REG_V0(sp) 727 REG_L v0, TF_BASE+TF_REG_V0(sp)
730 REG_L v1, TF_BASE+TF_REG_V1(sp) 728 REG_L v1, TF_BASE+TF_REG_V1(sp)
731 REG_L a0, TF_BASE+TF_REG_A0(sp) 729 REG_L a0, TF_BASE+TF_REG_A0(sp)
732 REG_L a1, TF_BASE+TF_REG_A1(sp) 730 REG_L a1, TF_BASE+TF_REG_A1(sp)
733 REG_L a2, TF_BASE+TF_REG_A2(sp) 731 REG_L a2, TF_BASE+TF_REG_A2(sp)
734 REG_L a3, TF_BASE+TF_REG_A3(sp) 732 REG_L a3, TF_BASE+TF_REG_A3(sp)
735 REG_L t0, TF_BASE+TF_REG_T0(sp) 733 REG_L t0, TF_BASE+TF_REG_T0(sp)
736 REG_L t1, TF_BASE+TF_REG_T1(sp) 734 REG_L t1, TF_BASE+TF_REG_T1(sp)