 @@ -1,105 +1,106 @@
-/*	$NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $	*/
+/*	$NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $	*/
 /*
  * Copyright (c) 2011 Matthew R. Green
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Handle picking the right types of the different cache call.
+ *
  * This module could take on a larger role.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.7 2011/06/06 01:16:48 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.8 2011/06/06 02:49:39 mrg Exp $");
 #include "opt_multiprocessor.h"
 #include <sys/param.h>
 #include <sys/reboot.h>
 #include <machine/cpu.h>
 #include <sparc64/sparc64/cache.h>
 static void
 cache_nop(void)
+{
+}
 static void
 blast_dcache_real(void)
+{
 	sp_blast_dcache(dcache_size, dcache_line_size);
+}
 #if 0
 static void
 sp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t cs)
+{
 	dcache_flush_page(pa);
+}
 void    (*dcache_flush_page)(paddr_t) =	dcache_flush_page_us;
 void	(*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t) =
 					sp_dcache_flush_page_cpuset;
 #endif
 void	(*blast_dcache)(void) =		blast_dcache_real;
 void	(*blast_icache)(void) =		blast_icache_us;
 #ifdef MULTIPROCESSOR
 void    (*sp_dcache_flush_page)(paddr_t) = dcache_flush_page_us;
 #endif
 void
 cache_setup_funcs(void)
+{
 	if (CPU_ISSUN4US || CPU_ISSUN4V) {
 #if 0
 		dcache_flush_page = (void (*)(paddr_t)) cache_nop;
 #ifdef MULTIPROCESSOR
 		/* XXXMRG shouldn't be necessary -- only caller is nop'ed out */
 		sp_dcache_flush_page = (void (*)(paddr_t)) cache_nop;
 #endif
 		blast_dcache = cache_nop;
 		blast_icache = cache_nop;
 	} else {
 		if (CPU_IS_USIII_UP()) {
 #if 0
 			dcache_flush_page = dcache_flush_page_usiii;
 #ifdef MULTIPROCESSOR
 			sp_dcache_flush_page = dcache_flush_page_usiii;
 #endif
 			blast_icache = blast_icache_usiii;
 printf("set usIII dcache/icache funcs\n");
+		}
 #ifdef MULTIPROCESSOR
 		if (sparc_ncpus > 1 && (boothowto & RB_MD1) == 0) {
 printf("set MP dcache funcs\n");
 #if 0
 			dcache_flush_page = smp_dcache_flush_page_allcpu;
 			dcache_flush_page_cpuset = smp_dcache_flush_page_cpuset;
 #endif
 			blast_dcache = smp_blast_dcache;
+		}
 #endif
+	}
+}

 @@ -1,170 +1,159 @@
-/*	$NetBSD: cache.h,v 1.21 2011/06/06 01:16:48 mrg Exp $ */
+/*	$NetBSD: cache.h,v 1.22 2011/06/06 02:49:39 mrg Exp $ */
 /*
  * Copyright (c) 2011 Matthew R. Green
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 /*
  * Copyright (C) 1996-1999 Eduardo Horvath.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  */
 /*
  * The spitfire has a 16K two-way set-associative L1 I$ and a separate
  * 16K L2 D$.  The I$ can be invalidated using the FLUSH instructions,
  * so we don't really need to worry about it much.  The D$ is a 16K
  * write-through, direct mapped virtually-addressed cache with two 16-byte
  * sub-blocks per line.  The E$ is a 512KB to 4MB direct mapped
  * physically-indexed physically-tagged cache.  Since the L1 caches
  * are write-through, they don't need flushing and can be invalidated directly.
+ *
  * The spitfire sees virtual addresses as:
+ *
  *	struct cache_va {
  *		uint64_t	:22,		(unused; VAs are only 40 bits)
  *				cva_tag:28,	(tag ID)
  *				cva_line:9,	(cache line number)
  *				cva_byte:5;	(byte within line)
  *	};
+ *
  * Since there is one bit of overlap between the page offset and the line index,
  * all we need to do is make sure that bit 14 of the va remains constant
  * and we have no aliasing problems.
+ *
  * Let me try again...
  * Page size is 8K, cache size is 16K so if (va1 & 0x3fff != va2 & 0x3fff)
  * then we have a problem.  Bit 14 *must* be the same for all mappings
  * of a page to be cacheable in the D$.  (The I$ is 16K 2-way
  * set-associative -- each bank is 8K.  No conflict there.)
  */
 #include <machine/psl.h>
 /* Various cache size/line sizes */
 extern	int	ecache_min_line_size;
 extern	int	dcache_line_size;
 extern	int	dcache_size;
 extern	int	icache_line_size;
 extern	int	icache_size;
 /* The following are for I$ and D$ flushes and are in locore.s */
 void 	dcache_flush_page_us(paddr_t);	/* flush page from D$ */
 void 	dcache_flush_page_usiii(paddr_t); /* flush page from D$ */
 void 	sp_blast_dcache(int, int);	/* Clear entire D$ */
 void 	blast_icache_us(void);		/* Clear entire I$ */
 void 	blast_icache_usiii(void);	/* Clear entire I$ */
 /* The following flush a range from the D$ and I$ but not E$. */
 void	cache_flush_phys_us(paddr_t, psize_t, int);
 void	cache_flush_phys_usiii(paddr_t, psize_t, int);
 static __inline__ void
 dcache_flush_page(paddr_t pa)
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	if (CPU_IS_USIII_UP())
 		dcache_flush_page_usiii(pa);
 	else
 		dcache_flush_page_us(pa);
 static __inline__ void
 cache_flush_phys(paddr_t pa, psize_t size, int ecache)
+{
 	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
 		cache_flush_phys_usiii(pa, size, ecache);
 	else
 		cache_flush_phys_us(pa, size, ecache);
+}
 /* SPARC64 specific */
 /* Assembly routines to flush TLB mappings */
 void sp_tlb_flush_pte_us(vaddr_t, int);
 void sp_tlb_flush_pte_usiii(vaddr_t, int);
 void sp_tlb_flush_all_us(void);
 void sp_tlb_flush_all_usiii(void);
 static __inline__ void
 sp_tlb_flush_pte(vaddr_t va, int ctx)
+{
 	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
 		sp_tlb_flush_pte_usiii(va, ctx);
 	else
 		sp_tlb_flush_pte_us(va, ctx);
+}
 static __inline__ void
 sp_tlb_flush_all(void)
+{
 	if (CPU_IS_USIII_UP() || CPU_IS_SPARC64_V_UP())
 		sp_tlb_flush_all_usiii();
 	else
 		sp_tlb_flush_all_us();
+}
 #if 0
 extern	void	(*dcache_flush_page)(paddr_t);
 extern	void	(*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t);
 #endif
 extern	void	(*blast_dcache)(void);
 extern	void	(*blast_icache)(void);
 void cache_setup_funcs(void);
 #ifdef MULTIPROCESSOR
 extern	void	(*sp_dcache_flush_page)(paddr_t);
 void smp_tlb_flush_pte(vaddr_t, struct pmap *);
 void smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t);
 void smp_dcache_flush_page_allcpu(paddr_t pa);
 void smp_blast_dcache(void);
-#define	tlb_flush_pte(va,pm	)	smp_tlb_flush_pte(va, pm)
+#define	tlb_flush_pte(va,pm)		smp_tlb_flush_pte(va, pm)
 #define	dcache_flush_page_all(pa)	smp_dcache_flush_page_cpuset(pa, cpus_active)
 #define	dcache_flush_page_cpuset(pa,cs)	smp_dcache_flush_page_cpuset(pa, cs)
 #else
 #define	tlb_flush_pte(va,pm)		sp_tlb_flush_pte(va, (pm)->pm_ctx[0])
 #define	dcache_flush_page_all(pa)	dcache_flush_page(pa)
 #define	dcache_flush_page_cpuset(pa,cs)	dcache_flush_page(pa)
 #endif

 @@ -1,507 +1,499 @@
-/*	$NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $ */
+/*	$NetBSD: ipifuncs.c,v 1.42 2011/06/06 02:49:39 mrg Exp $ */
 /*-
  * Copyright (c) 2004 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.41 2011/06/06 01:16:48 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: ipifuncs.c,v 1.42 2011/06/06 02:49:39 mrg Exp $");
 #include "opt_ddb.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/malloc.h>
 #include <sys/xcall.h>
 #include <machine/db_machdep.h>
 #include <machine/cpu.h>
 #include <machine/cpu_counter.h>
 #include <machine/ctlreg.h>
 #include <machine/pmap.h>
 #include <machine/sparc64.h>
 #include <sparc64/sparc64/cache.h>
 #if defined(DDB) || defined(KGDB)
 #ifdef DDB
 #include <ddb/db_command.h>
 #include <ddb/db_output.h>
 #endif
 #endif
 /* CPU sets containing halted, paused and resumed cpus */
 static volatile sparc64_cpuset_t cpus_halted;
 static volatile sparc64_cpuset_t cpus_spinning;
 static volatile sparc64_cpuset_t cpus_paused;
 static volatile sparc64_cpuset_t cpus_resumed;
 /* IPI handlers. */
 static int	sparc64_ipi_wait(sparc64_cpuset_t volatile *, sparc64_cpuset_t);
 static void	sparc64_ipi_error(const char *, sparc64_cpuset_t, sparc64_cpuset_t);
 /*
  * These are the "function" entry points in locore.s/mp_subr.s to handle IPI's.
  */
 void	sparc64_ipi_halt(void *, void *);
 void	sparc64_ipi_pause(void *, void *);
 void	sparc64_ipi_flush_pte_us(void *, void *);
 void	sparc64_ipi_flush_pte_usiii(void *, void *);
 void	sparc64_ipi_dcache_flush_page_us(void *, void *);
 void	sparc64_ipi_dcache_flush_page_usiii(void *, void *);
 void	sparc64_ipi_blast_dcache(void *, void *);
 void	sparc64_ipi_ccall(void *, void *);
 /*
  * Process cpu stop-self event.
  */
 void
 sparc64_ipi_halt_thiscpu(void *arg, void *arg2)
+{
 	extern void prom_printf(const char *fmt, ...);
 	printf("cpu%d: shutting down\n", cpu_number());
 	if (prom_has_stop_other() || !prom_has_stopself()) {
 		/*
 		 * just loop here, the final cpu will stop us later
 		 */
 		CPUSET_ADD(cpus_spinning, cpu_number());
 		CPUSET_ADD(cpus_halted, cpu_number());
 		spl0();
 		while (1)
 			/* nothing */;
 	} else {
 		CPUSET_ADD(cpus_halted, cpu_number());
 		prom_stopself();
+	}
+}
 void
 sparc64_do_pause(void)
+{
 #if defined(DDB)
 	extern bool ddb_running_on_this_cpu(void);
 	extern void db_resume_others(void);
 #endif
 	CPUSET_ADD(cpus_paused, cpu_number());
 	do {
 		membar_sync();
 	} while(CPUSET_HAS(cpus_paused, cpu_number()));
 	membar_sync();
 	CPUSET_ADD(cpus_resumed, cpu_number());
 #if defined(DDB)
 	if (ddb_running_on_this_cpu()) {
 		db_command_loop();
 		db_resume_others();
+	}
 #endif
+}
 /*
  * Pause cpu.  This is called from locore.s after setting up a trapframe.
  */
 void
 sparc64_ipi_pause_thiscpu(void *arg)
+{
 	int s;
 #if defined(DDB)
 	extern void fill_ddb_regs_from_tf(struct trapframe64 *tf);
 	extern void ddb_restore_state(void);
 	if (arg)
 		fill_ddb_regs_from_tf(arg);
 #endif
 	s = intr_disable();
 	sparc64_do_pause();
 #if defined(DDB)
 	if (arg) {
 		ddb_restore_state();
 		curcpu()->ci_ddb_regs = NULL;
+	}
 #endif
 	intr_restore(s);
+}
 /*
  * Initialize IPI machinery.
  */
 void
 sparc64_ipi_init()
+{
 	/* Clear all cpu sets. */
 	CPUSET_CLEAR(cpus_halted);
 	CPUSET_CLEAR(cpus_spinning);
 	CPUSET_CLEAR(cpus_paused);
 	CPUSET_CLEAR(cpus_resumed);
+}
 /*
  * Send an IPI to all in the list but ourselves.
  */
 void
 sparc64_multicast_ipi(sparc64_cpuset_t cpuset, ipifunc_t func, uint64_t arg1,
 		      uint64_t arg2)
+{
 	struct cpu_info *ci;
 	CPUSET_DEL(cpuset, cpu_number());
 	if (CPUSET_EMPTY(cpuset))
 		return;
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		if (CPUSET_HAS(cpuset, ci->ci_index)) {
 			CPUSET_DEL(cpuset, ci->ci_index);
 			sparc64_send_ipi(ci->ci_cpuid, func, arg1, arg2);
+		}
+	}
+}
 /*
  * Broadcast an IPI to all but ourselves.
  */
 void
 sparc64_broadcast_ipi(ipifunc_t func, uint64_t arg1, uint64_t arg2)
+{
 	sparc64_multicast_ipi(CPUSET_EXCEPT(cpus_active, cpu_number()), func,
 		arg1, arg2);
+}
 /*
  * Send an interprocessor interrupt.
  */
 void
 sparc64_send_ipi(int upaid, ipifunc_t func, uint64_t arg1, uint64_t arg2)
+{
 	int i, ik, shift = 0;
 	uint64_t intr_func;
 	KASSERT(upaid != curcpu()->ci_cpuid);
 	/*
 	 * UltraSPARC-IIIi CPUs select the BUSY/NACK pair based on the
 	 * lower two bits of the ITID.
 	 */
 	if (CPU_IS_USIIIi())
 		shift = (upaid & 0x3) * 2;
 	if (ldxa(0, ASR_IDSR) & (IDSR_BUSY << shift))
 		panic("recursive IPI?");
 	intr_func = (uint64_t)(u_long)func;
 	/* Schedule an interrupt. */
 	for (i = 0; i < 1000; i++) {
 		int s = intr_disable();
 		stxa(IDDR_0H, ASI_INTERRUPT_DISPATCH, intr_func);
 		stxa(IDDR_1H, ASI_INTERRUPT_DISPATCH, arg1);
 		stxa(IDDR_2H, ASI_INTERRUPT_DISPATCH, arg2);
 		stxa(IDCR(upaid), ASI_INTERRUPT_DISPATCH, 0);
 		membar_sync();
 		/* Workaround for SpitFire erratum #54, from FreeBSD */
 		if (CPU_IS_SPITFIRE()) {
 			(void)ldxa(P_DCR_0, ASI_INTERRUPT_RECEIVE_DATA);
 			membar_sync();
+		}
 		for (ik = 0; ik < 1000000; ik++) {
 			if (ldxa(0, ASR_IDSR) & (IDSR_BUSY << shift))
 				continue;
 			else
 				break;
+		}
 		intr_restore(s);
 		if (ik == 1000000)
 			break;
 		if ((ldxa(0, ASR_IDSR) & (IDSR_NACK << shift)) == 0)
 			return;
 		/*
 		 * Wait for a while with enabling interrupts to avoid
 		 * deadlocks.  XXX - random value is better.
 		 */
 		DELAY(1);
+	}
 	if (panicstr == NULL)
 		panic("cpu%d: ipi_send: couldn't send ipi to UPAID %u"
 			" (tried %d times)", cpu_number(), upaid, i);
+}
 /*
  * Wait for IPI operation to complete.
  * Return 0 on success.
  */
 int
 sparc64_ipi_wait(sparc64_cpuset_t volatile *cpus_watchset, sparc64_cpuset_t cpus_mask)
+{
 	uint64_t limit = gettick() + cpu_frequency(curcpu());
 	while (gettick() < limit) {
 		membar_sync();
 		if (CPUSET_EQUAL(*cpus_watchset, cpus_mask))
 			return 0;
+	}
 	return 1;
+}
 /*
  * Halt all cpus but ourselves.
  */
 void
 mp_halt_cpus(void)
+{
 	sparc64_cpuset_t cpumask, cpuset;
 	struct cpu_info *ci;
 	CPUSET_ASSIGN(cpuset, cpus_active);
 	CPUSET_DEL(cpuset, cpu_number());
 	CPUSET_ASSIGN(cpumask, cpuset);
 	CPUSET_SUB(cpuset, cpus_halted);
 	if (CPUSET_EMPTY(cpuset))
 		return;
 	CPUSET_CLEAR(cpus_spinning);
 	sparc64_multicast_ipi(cpuset, sparc64_ipi_halt, 0, 0);
 	if (sparc64_ipi_wait(&cpus_halted, cpumask))
 		sparc64_ipi_error("halt", cpumask, cpus_halted);
 	/*
 	 * Depending on available firmware methods, other cpus will
 	 * either shut down themselfs, or spin and wait for us to
 	 * stop them.
 	 */
 	if (CPUSET_EMPTY(cpus_spinning)) {
 		/* give other cpus a few cycles to actually power down */
 		delay(10000);
 		return;
+	}
 	/* there are cpus spinning - shut them down if we can */
 	if (prom_has_stop_other()) {
 		for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 			if (!CPUSET_HAS(cpus_spinning, ci->ci_index)) continue;
 			prom_stop_other(ci->ci_cpuid);
+		}
+	}
+}
 /*
  * Pause all cpus but ourselves.
  */
 void
 mp_pause_cpus(void)
+{
 	sparc64_cpuset_t cpuset;
 	CPUSET_ASSIGN(cpuset, cpus_active);
 	CPUSET_DEL(cpuset, cpu_number());
 	if (CPUSET_EMPTY(cpuset))
 		return;
 	sparc64_multicast_ipi(cpuset, sparc64_ipi_pause, 0, 0);
 	if (sparc64_ipi_wait(&cpus_paused, cpuset))
 		sparc64_ipi_error("pause", cpus_paused, cpuset);
+}
 /*
  * Resume a single cpu
  */
 void
 mp_resume_cpu(int cno)
+{
 	CPUSET_DEL(cpus_paused, cno);
 	membar_sync();
+}
 /*
  * Resume all paused cpus.
  */
 void
 mp_resume_cpus(void)
+{
 	sparc64_cpuset_t cpuset;
 	CPUSET_CLEAR(cpus_resumed);
 	CPUSET_ASSIGN(cpuset, cpus_paused);
 	membar_sync();
 	CPUSET_CLEAR(cpus_paused);
 	/* CPUs awake on cpus_paused clear */
 	if (sparc64_ipi_wait(&cpus_resumed, cpuset))
 		sparc64_ipi_error("resume", cpus_resumed, cpuset);
+}
 int
 mp_cpu_is_paused(sparc64_cpuset_t cpunum)
+{
 	return CPUSET_HAS(cpus_paused, cpunum);
+}
 /*
  * Flush pte on all active processors.
  */
 void
 smp_tlb_flush_pte(vaddr_t va, struct pmap * pm)
+{
 	sparc64_cpuset_t cpuset;
 	struct cpu_info *ci;
 	int ctx;
 	bool kpm = (pm == pmap_kernel());
 	ipifunc_t func;
 	if (CPU_IS_USIII_UP())
 		func = sparc64_ipi_flush_pte_usiii;
 	else
 		func = sparc64_ipi_flush_pte_us;
 	/* Flush our own TLB */
 	ctx = pm->pm_ctx[cpu_number()];
 	KASSERT(ctx >= 0);
 	if (kpm || ctx > 0)
 		sp_tlb_flush_pte(va, ctx);
 	CPUSET_ASSIGN(cpuset, cpus_active);
 	CPUSET_DEL(cpuset, cpu_number());
 	if (CPUSET_EMPTY(cpuset))
 		return;
 	/* Flush others */
 	for (ci = cpus; ci != NULL; ci = ci->ci_next) {
 		if (CPUSET_HAS(cpuset, ci->ci_index)) {
 			CPUSET_DEL(cpuset, ci->ci_index);
 			ctx = pm->pm_ctx[ci->ci_index];
 			KASSERT(ctx >= 0);
 			if (!kpm && ctx == 0)
 				continue;
 			sparc64_send_ipi(ci->ci_cpuid, func, va, ctx);
+		}
+	}
+}
 /*
  * Make sure this page is flushed from all/some CPUs.
  */
 void
 smp_dcache_flush_page_cpuset(paddr_t pa, sparc64_cpuset_t activecpus)
+{
 	ipifunc_t func;
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	if (CPU_IS_USIII_UP())
 		func = sparc64_ipi_dcache_flush_page_usiii;
 	else
 		func = sparc64_ipi_dcache_flush_page_us;
 	sparc64_multicast_ipi(activecpus, func, pa, dcache_line_size);
-	dcache_flush_page(pa);
+	sp_dcache_flush_page(pa);
+}
 #if 0
 void
 smp_dcache_flush_page_allcpu(paddr_t pa)
+{
 	smp_dcache_flush_page_cpuset(pa, cpus_active);
+}
 #endif
 /*
  * Flush the D$ on all CPUs.
  */
 void
 smp_blast_dcache(void)
+{
 	if (CPU_ISSUN4US || CPU_ISSUN4V)
 		return;
 	sparc64_multicast_ipi(cpus_active, sparc64_ipi_blast_dcache,
 			      dcache_size, dcache_line_size);
 	sp_blast_dcache(dcache_size, dcache_line_size);
+}
 /*
  * Print an error message.
  */
 void
 sparc64_ipi_error(const char *s, sparc64_cpuset_t cpus_succeeded,
 	sparc64_cpuset_t cpus_expected)
+{
 	int cpuid;
 	CPUSET_DEL(cpus_expected, cpus_succeeded);
 	if (!CPUSET_EMPTY(cpus_expected)) {
 		printf("Failed to %s:", s);
 		do {
 			cpuid = CPUSET_NEXT(cpus_expected);
 			CPUSET_DEL(cpus_expected, cpuid);
 			printf(" cpu%d", cpuid);
 		} while(!CPUSET_EMPTY(cpus_expected));
+	}
 	printf("\n");
+}
 /*
  * MD support for xcall(9) interface.
  */
 void
 sparc64_generic_xcall(struct cpu_info *target, ipi_c_call_func_t func,
 	void *arg)
+{
 	/* if target == NULL broadcast to everything but curcpu */
 	if (target)
 		sparc64_send_ipi(target->ci_cpuid, sparc64_ipi_ccall,
 		    (uint64_t)(uintptr_t)func, (uint64_t)(uintptr_t)arg);
 	else {
 		sparc64_multicast_ipi(cpus_active, sparc64_ipi_ccall,
 		    (uint64_t)(uintptr_t)func, (uint64_t)(uintptr_t)arg);
+	}
+}
 void
 xc_send_ipi(struct cpu_info *target)
+{
 	sparc64_generic_xcall(target, (ipi_c_call_func_t)xc_ipi_handler, NULL);
+}