Instead of ioapic(4), make MLINKS { lapic(4), ioapic(4) } to apic(4).


(jruoho)

.\" $NetBSD: apic.4,v 1.1 2011/06/06 16:52:15 jruoho Exp $
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.\" Copyright (c) 2011 Jukka Ruohonen <jruohonen@iki.fi>
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.Dd June 6, 2011
.Dt APIC 4 x86
.Os
.Sh NAME
.Nm apic ,
.Nm ioapic ,
.Nm lapic
.Nd Intel APIC Architecture
.Sh SYNOPSIS
.Cd "ioapic* at mainbus*"
.Sh DESCRIPTION
The
.Nm
subsystem provides basis for a system of advanced programmable
interrupt controllers
.Pq Tn APICs
originally designed by Intel but now widely used on all x86 systems.
.Pp
There are two elements in the architecture, the local
.Tn APIC
.Pq Tn LAPIC
and the
.Tn I/O APIC .
Historically these were connected by a dedicated 3-wire
.Dq APIC bus ,
but the system bus is used for communication today.
The configuration is increasingly dependent on
.Tn ACPI .
.Pp
Typically each
.Tn CPU
in the system contains one
.Tn LAPIC
that performs two primary functions:
.Bl -enum -offset indent
.It
It receives interrupts both from internal sources and from the external
.Tn I/O APIC .
The interrupt sources include
.Tn I/O
devices, the programmable
.Tn APIC
timer, performance monitoring counters,
thermal sensor interrupts, and others.
.It
In multiprocessor
.Pq Tn MP
systems a
.Tn LAPIC
receives and sends interprocessor interrupts
.Pq Tn IPIs
from and to other processors in the system.
.Tn IPIs
are used to provide software interrupts,
interrupt forwarding, or preemptive scheduling.
Against this, the architecture can be generally seen as an attempt
to solve the interrupt routing efficiency issues in
.Tn MP
systems.
.El
.Pp
There is typically one
.Tn I/O APIC
for each peripheral bus in the system.
Each
.Tn I/O APIC
has a series of interrupt inputs to external interrupt sources.
The architecture usually contains a redirection table which can be used
to route the interrupts that an
.Tn I/O APIC
receives to one or more local
.Tn APICs .
When a
.Tn LAPIC
is able to accept an interrupt, it will signal the
.Tn CPU .
Without an
.Tn I/O APIC ,
the local
.Tn APICs
are therefore mostly useless; one of the primary functions
of the architecture is no longer achievable, interrupts can
not be distributed to different
.Tn CPUs .
.Pp
The 8259
.Tn PIC
has coexisted with the architecture since its introduction.
It is still possible to disable the
.Tn APIC
system and revert back to a 8259-compatible
.Tn PIC .
But the widespread use of
.Tn MP
systems has made this mainly a fallback option.
.Sh SEE ALSO
.Xr acpi 4 ,
.Xr ichlpcib 4 ,
.Xr mainbus 4
.Rs
.%A Intel Corporation
.%T Intel 64 and IA-32 Architectures Software Developer's Manual
.%V Volume 3A: System Programming Guide, Part 1
.%P Chapter 10
.%D January, 2011
.%U http://www.intel.com/Assets/PDF/manual/253668.pdf
.Re
.Rs
.%A Intel Corporation
.%T Intel 82093AA I/O Advanced Programmable
.%T Interrupt Controller (I/O APIC) Datasheet
.%D May, 1996
.%U http://www.intel.com/design/chipsets/datashts/29056601.pdf
.Re
.Rs
.%A Intel Corporation
.%T 8259A, Programmable Interrupt Controller
.%D December, 1988
.%U http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf
.Re
.Rs
.%A John Baldwin
.%T PCI Interrupts for x86 Machines under FreeBSD
.%D May 18-19, 2007
.%O Proceedings of BSDCan 2007
.%U http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf
.Re
.Rs
.%A Microsoft Corporation
.%T PCI IRQ Routing on a Multiprocessor ACPI System
.%D December 4, 2001
.%U http://www.microsoft.com/whdc/archive/acpi-mp.mspx
.Re
.Sh AUTHORS
.An -nosplit
Authors of the
.Nx
implementation of the Intel APIC Architecture include
.An Andrew Doran ,
.An Bill Sommerfeld ,
.An Frank van der Linden ,
and
.An Stefan Grefen ,
among others.
The older 8259
.Tn PIC
implementation is based on the work of
.An William Jolitz .