Mon Jun 6 21:53:42 2011 UTC ()
Make sure to free the TLB when exiting from tlb_invalid_exception


(matt)
diff -r1.26.36.1.2.44 -r1.26.36.1.2.45 src/sys/arch/mips/mips/mipsX_subr.S
cvs diff -r1.26.36.1.2.44 -r1.26.36.1.2.45 src/sys/arch/mips/mips/mipsX_subr.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/mipsX_subr.S 2011/05/28 02:20:13 1.26.36.1.2.44
+++ src/sys/arch/mips/mips/mipsX_subr.S 2011/06/06 21:53:42 1.26.36.1.2.45
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.44 2011/05/28 02:20:13 matt Exp $ */ 1/* $NetBSD: mipsX_subr.S,v 1.26.36.1.2.45 2011/06/06 21:53:42 matt Exp $ */
2 2
3/* 3/*
4 * Copyright 2002 Wasabi Systems, Inc. 4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Written by Simon Burge for Wasabi Systems, Inc. 7 * Written by Simon Burge for Wasabi Systems, Inc.
8 * 8 *
9 * Redistribution and use in source and binary forms, with or without 9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions 10 * modification, are permitted provided that the following conditions
11 * are met: 11 * are met:
12 * 1. Redistributions of source code must retain the above copyright 12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer. 13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright 14 * 2. Redistributions in binary form must reproduce the above copyright
@@ -1763,26 +1763,30 @@ MIPSX(kern_tlbi_odd): @@ -1763,26 +1763,30 @@ MIPSX(kern_tlbi_odd):
1763 _SLL k0, k0, WIRED_SHIFT 1763 _SLL k0, k0, WIRED_SHIFT
1764 _SRL k0, k0, WIRED_SHIFT 1764 _SRL k0, k0, WIRED_SHIFT
1765#endif 1765#endif
1766 sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G 1766 sltiu k1, k1, MIPS3_TLB_WIRED_UPAGES # Luckily this is MIPS3_PG_G
1767 or k1, k1, k0 1767 or k1, k1, k0
1768 _MTC0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry 1768 _MTC0 k0, MIPS_COP_0_TLB_LO0 # save PTE entry
1769 COP0_SYNC 1769 COP0_SYNC
1770 tlbwi # update TLB 1770 tlbwi # update TLB
1771 COP0_SYNC 1771 COP0_SYNC
1772#ifdef MIPS3 1772#ifdef MIPS3
1773 nop 1773 nop
1774 nop 1774 nop
1775#endif 1775#endif
 1776#if defined(MULTIPROCESSOR) && (MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
 1777 _MFC0 k1, MIPS_COP_0_OSSCRATCH, 2 # get tlblock addr
 1778 INT_S zero, 0(k1) # clear lock
 1779#endif
1776 eret 1780 eret
1777 1781
1778#if defined(MULTIPROCESSOR) && (MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 1782#if defined(MULTIPROCESSOR) && (MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
1779/* 1783/*
1780 * Before entering kern_gen_exception we need to clear the tlb lock that 1784 * Before entering kern_gen_exception we need to clear the tlb lock that
1781 * we locked. 1785 * we locked.
1782 */ 1786 */
1783MIPSX(tlbunlock_kern_gen_exception): 1787MIPSX(tlbunlock_kern_gen_exception):
1784 _MFC0 k1, MIPS_COP_0_OSSCRATCH, 2 # get tlblock addr 1788 _MFC0 k1, MIPS_COP_0_OSSCRATCH, 2 # get tlblock addr
1785 b _C_LABEL(MIPSX(kern_gen_exception)) 1789 b _C_LABEL(MIPSX(kern_gen_exception))
1786 INT_S zero, 0(k1) # clear lock 1790 INT_S zero, 0(k1) # clear lock
1787#endif 1791#endif
1788 1792