 @@ -1,438 +1,416 @@
-/*	$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $	*/
+/*	$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $	*/
 /*-
  * Copyright (c) 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Platform-specific interrupt support for the Algorithmics P-6032.
+ *
  * The Algorithmics P-6032's interrupts are wired to GPIO pins
  * on the BONITO system controller.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.2 2009/08/07 01:27:14 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdium_intr.c,v 1.3 2011/06/08 17:47:48 bouyer Exp $");
 #define __INTR_PRIVATE
 #include "opt_ddb.h"
 #include <sys/param.h>
 #include <sys/queue.h>
 #include <sys/malloc.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/cpu.h>
 #include <machine/bus.h>
 #include <machine/intr.h>
 #include <mips/locore.h>
 #include <mips/bonito/bonitoreg.h>
 #include <evbmips/gdium/gdiumvar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 /*
  * The GDIUM interrupts are wired up in the following way:
+ *
  *	GPIN0		ISA_NMI		(in)
  *	GPIN1		ISA_INTR	(in)
  *	GPIN2		ETH_INT~	(in)
  *	GPIN3		BONIDE_INT	(in)
+ *
  *	PCI_INTA
  *	GPIN4		ISA IRQ3	(in, also on piix4)
  *	GPIN5		ISA IRQ4	(in, also on piix4)
+ *
  *	GPIO0		PIRQ A~		(in)
  *	GPIO1		PIRQ B~		(in)
  *	GPIO2		PIRQ C~		(in)
  *	GPIO3		PIRQ D~		(in)
  */
 struct gdium_irqmap {
 	const char *name;
 	uint8_t	irqidx;
 	uint8_t	flags;
 };
 #define	IRQ_F_INVERT	0x80	/* invert polarity */
 #define	IRQ_F_EDGE	0x40	/* edge trigger */
 #define	IRQ_F_INT0	0x00	/* INT0 */
 #define	IRQ_F_INT1	0x01	/* INT1 */
 #define	IRQ_F_INT2	0x02	/* INT2 */
 #define	IRQ_F_INT3	0x03	/* INT3 */
 #define	IRQ_F_INTMASK	0x07	/* INT mask */
 const struct gdium_irqmap gdium_irqmap[] = {
 	{ "gpio0",	GDIUM_IRQ_GPIO0,	IRQ_F_INT0 },
 	{ "gpio1",	GDIUM_IRQ_GPIO1,	IRQ_F_INT0 },
 	{ "gpio2",	GDIUM_IRQ_GPIO2,	IRQ_F_INT0 },
 	{ "gpio3",	GDIUM_IRQ_GPIO3,	IRQ_F_INT0 },
 	{ "pci inta",	GDIUM_IRQ_PCI_INTA,	IRQ_F_INT0 },
 	{ "pci intb",	GDIUM_IRQ_PCI_INTB,	IRQ_F_INT0 },
 	{ "pci intc",	GDIUM_IRQ_PCI_INTC,	IRQ_F_INT0 },
 	{ "pci intd",	GDIUM_IRQ_PCI_INTD,	IRQ_F_INT0 },
 	{ "pci perr",	GDIUM_IRQ_PCI_PERR,	IRQ_F_EDGE|IRQ_F_INT1 },
 	{ "pci serr",	GDIUM_IRQ_PCI_SERR,	IRQ_F_EDGE|IRQ_F_INT1 },
 	{ "denali",	GDIUM_IRQ_DENALI,	IRQ_F_INT1 },
 	{ "mips int0",	GDIUM_IRQ_INT0,		IRQ_F_INT0 },
 	{ "mips int1",	GDIUM_IRQ_INT1,		IRQ_F_INT1 },
 	{ "mips int2",	GDIUM_IRQ_INT2,		IRQ_F_INT2 },
 	{ "mips int3",	GDIUM_IRQ_INT3,		IRQ_F_INT3 },
 };
 struct gdium_intrhead {
 	struct evcnt intr_count;
 	int intr_refcnt;
 };
 struct gdium_intrhead gdium_intrtab[__arraycount(gdium_irqmap)];
 #define	NINTRS			2	/* MIPS INT0 - INT1 */
 struct gdium_cpuintr {
 	LIST_HEAD(, evbmips_intrhand) cintr_list;
 	struct evcnt cintr_count;
 	int cintr_refcnt;
 };
 struct gdium_cpuintr gdium_cpuintrs[NINTRS];
-const char *gdium_cpuintrnames[NINTRS] = {
+const char * const gdium_cpuintrnames[NINTRS] = {
 	"int 0 (pci)",
 	"int 1 (errors)",
 };
 /*
  * This is a mask of bits to clear in the SR when we go to a
  * given hardware interrupt priority level.
  */
-const uint32_t ipl_sr_bits[_IPL_N] = {
+static const struct ipl_sr_map gdium_ipl_sr_map = {
-	[IPL_NONE] = 0,
+    .sr_bits = {
-	[IPL_SOFTCLOCK] =
+	[IPL_NONE] =		0,
-	    MIPS_SOFT_INT_MASK_0,
+	[IPL_SOFTCLOCK] =	MIPS_SOFT_INT_MASK_0,
-#if IPL_SOFTCLOCK != IPL_SOFTBIO
+	[IPL_SOFTNET] =		MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 	[IPL_SOFTBIO] =
 	    MIPS_SOFT_INT_MASK_0,
 #endif
 	[IPL_SOFTNET] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 #if IPL_SOFTNET != IPL_SOFTSERIAL
 	[IPL_SOFTSERIAL] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1,
 #endif
 	[IPL_VM] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_1 |
 	    MIPS_INT_MASK_2 |
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4,
 	[IPL_SCHED] =
 	    MIPS_SOFT_INT_MASK_0 | MIPS_SOFT_INT_MASK_1 |
 	    MIPS_INT_MASK_0 |
 	    MIPS_INT_MASK_1 |
 	    MIPS_INT_MASK_2 |
 	    MIPS_INT_MASK_3 |
 	    MIPS_INT_MASK_4 |
 	    MIPS_INT_MASK_5,
 	[IPL_DDB] =		MIPS_INT_MASK,
 	[IPL_HIGH] =            MIPS_INT_MASK,
     },
 };
-/*
+int	gdium_pci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
  * This is a mask of bits to clear in the SR when we go to a
  * given software interrupt priority level.
  * Hardware ipls are port/board specific.
  */
 const uint32_t mips_ipl_si_to_sr[] = {
 	[IPL_SOFTCLOCK-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
 #if IPL_SOFTCLOCK != IPL_SOFTBIO
 	[IPL_SOFTBIO-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
 #endif
 	[IPL_SOFTNET-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
 #if IPL_SOFTNET != IPL_SOFTSERIAL
 	[IPL_SOFTSERIAL-IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_1,
 #endif
 };
 int	gdium_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
 const char *gdium_pci_intr_string(void *, pci_intr_handle_t);
 const struct evcnt *gdium_pci_intr_evcnt(void *, pci_intr_handle_t);
 void	*gdium_pci_intr_establish(void *, pci_intr_handle_t, int,
 	    int (*)(void *), void *);
 void	gdium_pci_intr_disestablish(void *, void *);
 void	gdium_pci_conf_interrupt(void *, int, int, int, int, int *);
 void
 evbmips_intr_init(void)
+{
-	struct gdium_config *gc = &gdium_configuration;
+	struct gdium_config * const gc = &gdium_configuration;
 	struct bonito_config *bc = &gc->gc_bonito;
 	const struct gdium_irqmap *irqmap;
 	uint32_t intbit;
-	int i;
+	size_t i;
 	ipl_sr_map = gdium_ipl_sr_map;
 	for (i = 0; i < NINTRS; i++) {
 		LIST_INIT(&gdium_cpuintrs[i].cintr_list);
 		evcnt_attach_dynamic(&gdium_cpuintrs[i].cintr_count,
 		    EVCNT_TYPE_INTR, NULL, "mips", gdium_cpuintrnames[i]);
+	}
 	//evcnt_attach_static(&mips_int5_evcnt);
 	for (i = 0; i < __arraycount(gdium_irqmap); i++) {
 		irqmap = &gdium_irqmap[i];
 		intbit = 1 << irqmap->irqidx;
 		evcnt_attach_dynamic(&gdium_intrtab[i].intr_count,
 		    EVCNT_TYPE_INTR, NULL, "bonito", irqmap->name);
 		if (irqmap->irqidx < 4)
 			bc->bc_gpioIE |= intbit;
 		if (irqmap->flags & IRQ_F_INVERT)
 			bc->bc_intPol |= intbit;
 		if (irqmap->flags & IRQ_F_EDGE)
 			bc->bc_intEdge |= intbit;
 		if ((irqmap->flags & IRQ_F_INTMASK) == IRQ_F_INT1)
 			bc->bc_intSteer |= intbit;
 		REGVAL(BONITO_INTENCLR) = intbit;
+	}
 	REGVAL(BONITO_GPIOIE) = bc->bc_gpioIE;
 	REGVAL(BONITO_INTEDGE) = bc->bc_intEdge;
 	REGVAL(BONITO_INTSTEER) = bc->bc_intSteer;
 	REGVAL(BONITO_INTPOL) = bc->bc_intPol;
 	gc->gc_pc.pc_intr_v = NULL;
 	gc->gc_pc.pc_intr_map = gdium_pci_intr_map;
 	gc->gc_pc.pc_intr_string = gdium_pci_intr_string;
 	gc->gc_pc.pc_intr_evcnt = gdium_pci_intr_evcnt;
 	gc->gc_pc.pc_intr_establish = gdium_pci_intr_establish;
 	gc->gc_pc.pc_intr_disestablish = gdium_pci_intr_disestablish;
 	gc->gc_pc.pc_conf_interrupt = gdium_pci_conf_interrupt;
 	/* We let the PCI-ISA bridge code handle this. */
 	gc->gc_pc.pc_pciide_compat_intr_establish = NULL;
+}
 void *
 evbmips_intr_establish(int irq, int (*func)(void *), void *arg)
+{
 	const struct gdium_irqmap *irqmap;
 	struct evbmips_intrhand *ih;
 	int level;
 	int s;
 	irqmap = &gdium_irqmap[irq];
 	KASSERT(irq < __arraycount(gdium_irqmap));
 	KASSERT(irq == irqmap->irqidx);
 	ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT|M_ZERO);
 	if (ih == NULL)
 		return NULL;
 	ih->ih_func = func;
 	ih->ih_arg = arg;
 	ih->ih_irq = irq;
 	s = splhigh();
 	/*
 	 * First, link it into the tables.
 	 */
 	level = (irqmap->flags & IRQ_F_INT1) != 0;
 	LIST_INSERT_HEAD(&gdium_cpuintrs[level].cintr_list, ih, ih_q);
 	gdium_cpuintrs[level].cintr_refcnt++;
 	/*
 	 * Now enable it.
 	 */
 	if (gdium_intrtab[ih->ih_irq].intr_refcnt++ == 0)
 		REGVAL(BONITO_INTENSET) = (1 << ih->ih_irq);
 	splx(s);
 	return (ih);
+}
 void
 evbmips_intr_disestablish(void *cookie)
+{
 	const struct gdium_irqmap *irqmap;
 	struct evbmips_intrhand *ih = cookie;
 	int s;
 	irqmap = &gdium_irqmap[ih->ih_irq];
 	s = splhigh();
 	/*
 	 * First, remove it from the table.
 	 */
 	LIST_REMOVE(ih, ih_q);
 	gdium_cpuintrs[(irqmap->flags & IRQ_F_INT1) != 0].cintr_refcnt--;
 	/*
 	 * Now, disable it, if there is nothing remaining on the
 	 * list.
 	 */
 	if (gdium_intrtab[ih->ih_irq].intr_refcnt-- == 1)
 		REGVAL(BONITO_INTENCLR) = (1 << ih->ih_irq);
 	splx(s);
 	free(ih, M_DEVBUF);
+}
 void
-evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc,
+evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
 	uint32_t ipending)
+{
 	const struct gdium_irqmap *irqmap;
 	struct evbmips_intrhand *ih;
 	int level;
 	uint32_t isr;
 	/*
 	 * Read the interrupt pending registers, mask them with the
 	 * ones we have enabled, and service them in order of decreasing
 	 * priority.
 	 */
 	isr = REGVAL(BONITO_INTISR) & REGVAL(BONITO_INTEN);
 	for (level = 1; level >= 0; level--) {
 		if ((ipending & (MIPS_INT_MASK_4 << level)) == 0)
 			continue;
 		gdium_cpuintrs[level].cintr_count.ev_count++;
 		LIST_FOREACH (ih, &gdium_cpuintrs[level].cintr_list, ih_q) {
 			irqmap = &gdium_irqmap[ih->ih_irq];
 			if (isr & (1 << ih->ih_irq)) {
 				gdium_intrtab[ih->ih_irq].intr_count.ev_count++;
 				(*ih->ih_func)(ih->ih_arg);
+			}
+		}
 		cause &= ~(MIPS_INT_MASK_0 << level);
+	}
 	/* Re-enable anything that we have processed. */
 	_splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK));
+}
 /*****************************************************************************
  * PCI interrupt support
  *****************************************************************************/
 int
-gdium_pci_intr_map(struct pci_attach_args *pa,
+gdium_pci_intr_map(const struct pci_attach_args *pa,
     pci_intr_handle_t *ihp)
+{
 	static const int8_t pciirqmap[5/*device*/] = {
 	    GDIUM_IRQ_PCI_INTC, /* 13: PCI 802.11 */
 	    GDIUM_IRQ_PCI_INTA, /* 14: SM501 */
 	    GDIUM_IRQ_PCI_INTB, /* 15: NEC USB (2 func) */
 	    GDIUM_IRQ_PCI_INTD, /* 16: Ethernet */
 	    GDIUM_IRQ_PCI_INTC, /* 17: NEC USB (2 func) */
 	};
 	pcitag_t bustag = pa->pa_intrtag;
 	int buspin = pa->pa_intrpin;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	int device;
 	if (buspin == 0) {
 		/* No IRQ used. */
 		return (1);
+	}
 	if (buspin > 4) {
 		printf("gdium_pci_intr_map: bad interrupt pin %d\n",
 		    buspin);
 		return (1);
+	}
 	pci_decompose_tag(pc, bustag, NULL, &device, NULL);
 	if (device < 13 || device > 17) {
 		printf("gdium_pci_intr_map: bad device %d\n",
 		    device);
 		return (1);
+	}
 	*ihp = pciirqmap[device - 13];
 	return (0);
+}
 const char *
 gdium_pci_intr_string(void *v, pci_intr_handle_t ih)
+{
 	if (ih >= __arraycount(gdium_irqmap))
 		panic("gdium_intr_string: bogus IRQ %ld", ih);
 	return gdium_irqmap[ih].name;
+}
 const struct evcnt *
 gdium_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
+{
 	return &gdium_intrtab[ih].intr_count;
+}
 void *
 gdium_pci_intr_establish(void *v, pci_intr_handle_t ih, int level,
     int (*func)(void *), void *arg)
+{
 	if (ih >= __arraycount(gdium_irqmap))
 		panic("gdium_pci_intr_establish: bogus IRQ %ld", ih);
 	return evbmips_intr_establish(ih, func, arg);
+}
 void
 gdium_pci_intr_disestablish(void *v, void *cookie)
+{
 	return (evbmips_intr_disestablish(cookie));
+}
 void
 gdium_pci_conf_interrupt(void *v, int bus, int dev, int pin, int swiz,
     int *iline)
+{
 	/*
 	 * We actually don't need to do anything; everything is handled
 	 * in pci_intr_map().
 	 */
 	*iline = 0;
+}

 @@ -1,484 +1,451 @@
-/*	$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $	*/
+/*	$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed for the NetBSD Project by
  *      Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright (c) 1988 University of Utah.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * the Systems Programming Group of the University of Utah Computer
  * Science Department, The Mach Operating System project at
  * Carnegie-Mellon University and Ralph Campbell.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of the University nor the names of its contributors
  *    may be used to endorse or promote products derived from this software
  *    without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c   8.3 (Berkeley) 1/12/94
  *	from: Utah Hdr: machdep.c 1.63 91/04/24
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.13 2011/02/20 07:48:34 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.14 2011/06/08 17:47:48 bouyer Exp $");
 #include "opt_ddb.h"
 #include "opt_execfmt.h"
 #include "opt_modular.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/buf.h>
 #include <sys/reboot.h>
 #include <sys/mount.h>
 #include <sys/kcore.h>
 #include <sys/boot_flag.h>
 #include <sys/termios.h>
 #include <sys/ksyms.h>
 #include <sys/device.h>
 #include <uvm/uvm_extern.h>
 #include <dev/cons.h>
 #include "ksyms.h"
 #if NKSYMS || defined(DDB) || defined(MODULAR)
 #include <machine/db_machdep.h>
 #include <ddb/db_extern.h>
 #endif
 #include <machine/cpu.h>
 #include <machine/psl.h>
 #include <mips/locore.h>
 #include <mips/bonito/bonitoreg.h>
 #include <evbmips/gdium/gdiumvar.h>
 #include "com.h"
 #if NCOM > 0
 #include <dev/ic/comreg.h>
 #include <dev/ic/comvar.h>
 int	comcnrate = 38400;	/* XXX should be config option */
 #endif /* NCOM > 0 */
 struct gdium_config gdium_configuration = {
 	.gc_bonito = {
 		.bc_adbase = 11,	/* magic */
 	},
 };
 /* For sysctl_hw. */
 extern char cpu_model[];
 /* Our exported CPU info; we can have only one. */
 struct cpu_info cpu_info_store;
 /* Maps for VM objects. */
 struct vm_map *phys_map = NULL;
 int	netboot;		/* Are we netbooting? */
 phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
 int mem_cluster_cnt;
 void	configure(void);
 void	mach_init(int, char **, char **, void *);
 /*
  * For some reason, PMON doesn't assign a real address to the Ralink's BAR.
  * So we have to do it.
  */
 static void
 gdium_pci_attach_hook(device_t parent, device_t self,
     struct pcibus_attach_args *pba)
+{
 	const pcitag_t high_dev = pci_make_tag(pba->pba_pc, 0, 17, 1);
 	const pcitag_t ralink_dev = pci_make_tag(pba->pba_pc, 0, 13, 0);
 	bus_size_t high_size, ralink_size;
 	pcireg_t v;
 	/*
 	 * Get the highest PCI addr used from the last PCI dev.
 	 */
 	v = pci_conf_read(pba->pba_pc, high_dev, PCI_MAPREG_START);
 	v &= PCI_MAPREG_MEM_ADDR_MASK;
 	/*
 	 * Get the sizes of the map registers.
 	 */
 	pci_mapreg_info(pba->pba_pc, high_dev, PCI_MAPREG_START,
 	    PCI_MAPREG_MEM_TYPE_32BIT, NULL, &high_size, NULL);
 	pci_mapreg_info(pba->pba_pc, ralink_dev, PCI_MAPREG_START,
 	    PCI_MAPREG_MEM_TYPE_32BIT, NULL, &ralink_size, NULL);
 	/*
 	 * Position the ralink register space after the last device.
 	 */
 	v = (v + high_size + ralink_size - 1) & ~(ralink_size - 1);
 	/*
 	 * Set the mapreg.
 	 */
 	pci_conf_write(pba->pba_pc, ralink_dev, PCI_MAPREG_START, v);
 #if 0
 	/*
 	 * Why does linux do this?
 	 */
 	for (int dev = 15; dev <= 17; dev +=2) {
 		for (int func = 0; func <= 1; func++) {
 			pcitag_t usb_dev = pci_make_tag(pba->pba_pc, 0, dev, func);
 			v = pci_conf_read(pba->pba_pc, usb_dev, 0xe0);
 			v |= 3;
 			pci_conf_write(pba->pba_pc, usb_dev, 0xe0, v);
+		}
+	}
 #endif
+}
 /*
  * Do all the stuff that locore normally does before calling main().
  */
 void
 mach_init(int argc, char **argv, char **envp, void *callvec)
+{
 	struct gdium_config *gc = &gdium_configuration;
 	void *kernend;
 	u_long first, last;
 	struct pcb *pcb0;
 	vaddr_t v;
 #ifdef NOTYET
 	char *cp;
 	int howto;
 #endif
 	int i;
 	psize_t memsize;
 	extern char edata[], end[];
 	/*
 	 * Clear the BSS segment.
 	 */
 	kernend = (void *)mips_round_page(end);
 	memset(edata, 0, (char *)kernend - edata);
 	/*
 	 * Set up the exception vectors and CPU-specific function
 	 * vectors early on.  We need the wbflush() vector set up
 	 * before comcnattach() is called (or at least before the
 	 * first printf() after that is called).
 	 * Also clears the I+D caches.
 	 */
-	mips_vector_init(NULL, bool);
+	mips_vector_init(NULL, false);
 	/* set the VM page size */
 	uvm_setpagesize();
 	memsize = 256*1024*1024;
 	physmem = btoc(memsize);
 	bonito_pci_init(&gc->gc_pc, &gc->gc_bonito);
 	/*
 	 * Override the null bonito_pci_attach_hook with our own to we can
 	 * fix the ralink (device 13).
 	 */
 	gc->gc_pc.pc_attach_hook = gdium_pci_attach_hook;
 	gdium_bus_io_init(&gc->gc_iot, gc);
 	gdium_bus_mem_init(&gc->gc_memt, gc);
 	gdium_dma_init(gc);
 	gdium_cnattach(gc);
 	/*
 	 * Disable the 2nd PCI window since we don't need it.
 	 */
 	mips3_sd((uint64_t *)MIPS_PHYS_TO_KSEG1(BONITO_REGBASE + 0x158), 0xe);
 	pci_conf_write(&gc->gc_pc, pci_make_tag(&gc->gc_pc, 0, 0, 0), 18, 0);
 	/*
 	 * Get the timer from PMON.
 	 */
 	for (i = 0; envp[i] != NULL; i++) {
 		if (!strncmp(envp[i], "cpuclock=", 9)) {
 			curcpu()->ci_cpu_freq =
 			    strtoul(&envp[i][9], NULL, 10);
 			break;
+		}
+	}
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq /= 2;
 	/* Compute the number of ticks for hz. */
 	curcpu()->ci_cycles_per_hz = (curcpu()->ci_cpu_freq + hz / 2) / hz;
 	/* Compute the delay divisor. */
 	curcpu()->ci_divisor_delay =
 	    ((curcpu()->ci_cpu_freq + 500000) / 1000000);
 	/*
 	 * Get correct cpu frequency if the CPU runs at twice the
 	 * external/cp0-count frequency.
 	 */
-	if (mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
+	if (mips_options.mips_cpu_flags & CPU_MIPS_DOUBLE_COUNT)
 		curcpu()->ci_cpu_freq *= 2;
 #ifdef DEBUG
 	printf("Timer calibration: %lu cycles/sec\n",
 	    curcpu()->ci_cpu_freq);
 #endif
 #if NCOM > 0
 	/*
 	 * Delay to allow firmware putchars to complete.
 	 * FIFO depth * character time.
 	 * character time = (1000000 / (defaultrate / 10))
 	 */
 	delay(160000000 / comcnrate);
 	if (comcnattach(&gc->gc_iot, MALTA_UART0ADR, comcnrate,
 	    COM_FREQ, COM_TYPE_NORMAL,
 	    (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8) != 0)
 		panic("malta: unable to initialize serial console");
 #endif /* NCOM > 0 */
 	mem_clusters[0].start = 0;
 	mem_clusters[0].size = ctob(physmem);
 	mem_cluster_cnt = 1;
 	strcpy(cpu_model, "Gdium Liberty 1000");
 	/*
 	 * XXX: check argv[0] - do something if "gdb"???
 	 */
 	/*
 	 * Look at arguments passed to us and compute boothowto.
 	 */
 	boothowto = RB_AUTOBOOT;
 #ifdef NOTYET
 	for (i = 1; i < argc; i++) {
 		for (cp = argv[i]; *cp; cp++) {
 			/* Ignore superfluous '-', if there is one */
 			if (*cp == '-')
 				continue;
 			howto = 0;
 			BOOT_FLAG(*cp, howto);
 			if (! howto)
 				printf("bootflag '%c' not recognised\n", *cp);
 			else
 				boothowto |= howto;
+		}
+	}
 #endif
 	/*
 	 * Load the rest of the available pages into the VM system.
 	 */
-	first = round_page(MIPS_KSEG0_TO_PHYS(kernend));
+	mips_page_physload(MIPS_KSEG0_START, (vaddr_t)kernend,
-	last = mem_clusters[0].start + mem_clusters[0].size;
+	    mem_clusters, mem_cluster_cnt, NULL, 0);
 	uvm_page_physload(atop(first), atop(last), atop(first), atop(last),
 		VM_FREELIST_DEFAULT);
 	/*
 	 * Initialize error message buffer (at end of core).
 	 */
 	mips_init_msgbuf();
 	pmap_bootstrap();
 	/*
 	 * Allocate uarea page for lwp0 and set it.
 	 */
-	v = uvm_pageboot_alloc(USPACE);
+	mips_init_lwp0_uarea();
 	uvm_lwp_setuarea(&lwp0, v);
 	pcb0 = lwp_getpcb(&lwp0);
 	pcb0->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; /* SR */
 	lwp0.l_md.md_regs = (struct frame *)(v + USPACE) - 1;
 	/*
 	 * Initialize debuggers, and break into them, if appropriate.
 	 */
 #if defined(DDB)
 	if (boothowto & RB_KDB)
 		Debugger();
 #endif
+}
 void
 consinit(void)
+{
 	/*
 	 * Everything related to console initialization is done
 	 * in mach_init().
 	 */
+}
 /*
  * Allocate memory for variable-sized tables,
  */
 void
 cpu_startup(void)
+{
 	vaddr_t minaddr, maxaddr;
 	char pbuf[9];
 	/*
-	 * Good {morning,afternoon,evening,night}.
+	 *  Do the common startup items.
 	 */
-	printf("%s%s", copyright, version);
+	cpu_startup_common();
 	format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
 	printf("total memory = %s\n", pbuf);
 	/*
 	 * Virtual memory is bootstrapped -- notify the bus spaces
 	 * that memory allocation is now safe.
 	 */
 	gdium_configuration.gc_mallocsafe = 1;
 	minaddr = 0;
 	/*
 	 * Allocate a submap for physio.
 	 */
 	phys_map = uvm_km_suballoc(kernel_map, &minaddr, &maxaddr,
 				    VM_PHYS_SIZE, 0, FALSE, NULL);
 	/*
 	 * (No need to allocate an mbuf cluster submap.  Mbuf clusters
 	 * are allocated via the pool allocator, and we use KSEG to
 	 * map those pages.)
 	 */
 	format_bytes(pbuf, sizeof(pbuf), ptoa(uvmexp.free));
 	printf("avail memory = %s\n", pbuf);
+}
 int	waittime = -1;
 void
 cpu_reboot(int howto, char *bootstr)
+{
 	/* Take a snapshot before clobbering any registers. */
-	if (curproc)
+	savectx(curpcb);
 		savectx(curpcb);
 	if (cold) {
 		howto |= RB_HALT;
 		goto haltsys;
+	}
 	/* If "always halt" was specified as a boot flag, obey. */
 	if (boothowto & RB_HALT)
 		howto |= RB_HALT;
 	boothowto = howto;
 	if ((howto & RB_NOSYNC) == 0 && (waittime < 0)) {
 		waittime = 0;
 		vfs_shutdown();
 		/*
 		 * If we've been adjusting the clock, the todr
 		 * will be out of synch; adjust it now.
 		 */
 		resettodr();
+	}
 	splhigh();
 	if (howto & RB_DUMP)
 		dumpsys();
 haltsys:
 	doshutdownhooks();
 	pmf_system_shutdown(boothowto);
 	if ((howto & RB_POWERDOWN) == RB_POWERDOWN) {
 		/*
 		 * Turning on GPIO1 as output will cause a powerdown.
 		 */
 		REGVAL(BONITO_GPIODATA) |= 2;
 		REGVAL(BONITO_GPIOIE) &= ~2;
+	}
 	if (howto & RB_HALT) {
 		printf("\n");
 		printf("The operating system has halted.\n");
 		printf("Please press any key to reboot.\n\n");
 		cnpollc(1);	/* For proper keyboard command handling */
 		cngetc();
 		cnpollc(0);
+	}
 	printf("%s\n\n", ((howto & RB_HALT) != 0) ? "halted." : "rebooting...");
 	/*
 	 * Turning off GPIO2 as output will cause a reset.
 	 */
 	REGVAL(BONITO_GPIODATA) &= ~4;
 	REGVAL(BONITO_GPIOIE) &= ~4;
 	__asm__ __volatile__ (
 		"\t.long 0x3c02bfc0\n"
 		"\t.long 0x00400008\n"
 	    ::: "v0");
+}

 @@ -1,1225 +1,1225 @@
-/*	$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $	*/
 /*
  * Copyright 2001, 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Copyright 2000, 2001
  * Broadcom Corporation. All rights reserved.
+ *
  * This software is furnished under license and may be used and copied only
  * in accordance with the following terms and conditions.  Subject to these
  * conditions, you may download, copy, install, use, modify and distribute
  * modified or unmodified copies of this software in source and/or binary
  * form. No title or ownership is transferred hereby.
+ *
  * 1) Any source code used, modified or distributed must reproduce and
  *    retain this copyright notice and list of conditions as they appear in
  *    the source file.
+ *
  * 2) No right is granted to use any trade name, trademark, or logo of
  *    Broadcom Corporation.  The "Broadcom Corporation" name may not be
  *    used to endorse or promote products derived from this software
  *    without the prior written permission of Broadcom Corporation.
+ *
  * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
  *    WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
  *    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
  *    NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
  *    FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
  *    LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  *    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  *    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  *    WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  *    OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.46 2011/03/15 07:39:22 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.47 2011/06/08 17:47:48 bouyer Exp $");
 #include "opt_cputype.h"
 #include "opt_mips_cache.h"
 #include <sys/param.h>
 #include <uvm/uvm_extern.h>
 #include <mips/cache.h>
 #include <mips/locore.h>
 #ifdef MIPS1
 #include <mips/cache_r3k.h>
 #endif
 #ifdef MIPS3_PLUS
 #include <mips/cache_r4k.h>
 #include <mips/cache_r5k.h>
 #ifdef ENABLE_MIPS4_CACHE_R10K
 #include <mips/cache_r10k.h>
 #endif
 #ifdef MIPS3_LOONGSON2
 #include <mips/cache_ls2.h>
 #endif
 #endif
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 #include <mips/mipsNN.h>		/* MIPS32/MIPS64 registers */
 #include <mips/cache_mipsNN.h>
 #endif
 struct mips_cache_info mips_cache_info;
 struct mips_cache_ops mips_cache_ops;
 #ifdef MIPS1
 #ifdef ENABLE_MIPS_TX3900
 #include <mips/cache_tx39.h>
 void	tx3900_get_cache_config(void);
 void	tx3920_get_cache_config(void);
 void	tx39_cache_config_write_through(void);
 #endif /* ENABLE_MIPS_TX3900 */
 #endif /* MIPS1 */
 #if defined(MIPS3) || defined(MIPS4)
 void	mips3_get_cache_config(int);
 #ifdef ENABLE_MIPS4_CACHE_R10K
 void	mips4_get_cache_config(int);
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #endif /* MIPS3 || MIPS4 */
 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
 static void mips_config_cache_prehistoric(void);
 static void mips_config_cache_emips(void);
 #endif
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 static void mips_config_cache_modern(void);
 #endif
 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
 /* no-cache definition */
 static void no_cache_op(void);
 static void no_cache_op_range(vaddr_t va, vsize_t size);
 /* no-cache implementation */
 static void no_cache_op(void) {}
 static void no_cache_op_range(vaddr_t va, vsize_t size) {}
 #endif
 /*
  * mips_dcache_compute_align:
+ *
  *	Compute the D-cache alignment values.
  */
 void
 mips_dcache_compute_align(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	u_int align;
 	align = mci->mci_pdcache_line_size;
 	if (mci->mci_sdcache_line_size > align)
 		align = mci->mci_sdcache_line_size;
 	if (mci->mci_tcache_line_size > align)
 		align = mci->mci_tcache_line_size;
 	mci->mci_dcache_align = align;
 	mci->mci_dcache_align_mask = align - 1;
+}
 /*
  * mips_config_cache:
+ *
  *	Configure the cache for the system.
+ *
  *	XXX DOES NOT HANDLE SPLIT SECONDARY CACHES.
  */
 void
 mips_config_cache(void)
+{
 #ifdef DIAGNOSTIC
 	struct mips_cache_info * const mci = &mips_cache_info;
 	struct mips_cache_ops * const mco = &mips_cache_ops;
 #endif
 	const mips_prid_t cpu_id = mips_options.mips_cpu_id;
 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
 	if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC)
 		mips_config_cache_prehistoric();
 	else if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_MICROSOFT)
 		mips_config_cache_emips();
 #endif
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 	if (MIPS_PRID_CID(cpu_id) != MIPS_PRID_CID_PREHISTORIC)
 		mips_config_cache_modern();
 #endif
 #ifdef DIAGNOSTIC
 	/* Check that all cache ops are set up. */
 	if (mci->mci_picache_size || 1) {	/* XXX- must have primary Icache */
 		if (!mco->mco_icache_sync_all)
 			panic("no icache_sync_all cache op");
 		if (!mco->mco_icache_sync_range)
 			panic("no icache_sync_range cache op");
 		if (!mco->mco_icache_sync_range_index)
 			panic("no icache_sync_range_index cache op");
+	}
 	if (mci->mci_pdcache_size || 1) {	/* XXX- must have primary Dcache */
 		if (!mco->mco_pdcache_wbinv_all)
 			panic("no pdcache_wbinv_all");
 		if (!mco->mco_pdcache_wbinv_range)
 			panic("no pdcache_wbinv_range");
 		if (!mco->mco_pdcache_wbinv_range_index)
 			panic("no pdcache_wbinv_range_index");
 		if (!mco->mco_pdcache_inv_range)
 			panic("no pdcache_inv_range");
 		if (!mco->mco_pdcache_wb_range)
 			panic("no pdcache_wb_range");
+	}
 	if (mci->mci_sdcache_size) {
 		if (!mco->mco_sdcache_wbinv_all)
 			panic("no sdcache_wbinv_all");
 		if (!mco->mco_sdcache_wbinv_range)
 			panic("no sdcache_wbinv_range");
 		if (!mco->mco_sdcache_wbinv_range_index)
 			panic("no sdcache_wbinv_range_index");
 		if (!mco->mco_sdcache_inv_range)
 			panic("no sdcache_inv_range");
 		if (!mco->mco_sdcache_wb_range)
 			panic("no sdcache_wb_range");
+	}
 #endif /* DIAGNOSTIC */
+}
 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
 /*
  *	XXX DOES NOT HANDLE SPLIT SECONDARY CACHES.
  */
 void
 mips_config_cache_prehistoric(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	struct mips_cache_ops * const mco = &mips_cache_ops;
 	const mips_prid_t cpu_id = mips_options.mips_cpu_id;
 #if defined(MIPS3) || defined(MIPS4)
 	int csizebase = MIPS3_CONFIG_C_DEFBASE;
 #endif
 	KASSERT(PAGE_SIZE != 0);
 	/*
 	 * Configure primary caches.
 	 */
 	switch (MIPS_PRID_IMPL(cpu_id)) {
 #ifdef MIPS1
 	case MIPS_R2000:
 	case MIPS_R3000:
 		mci->mci_picache_size = r3k_picache_size();
 		mci->mci_pdcache_size = r3k_pdcache_size();
 		mci->mci_picache_line_size = 4;
 		mci->mci_pdcache_line_size = 4;
 		mci->mci_picache_ways = 1;
 		mci->mci_pdcache_ways = 1;
 		mci->mci_pdcache_write_through = true;
 		mco->mco_icache_sync_all =
 		    r3k_icache_sync_all;
 		mco->mco_icache_sync_range =
 		    r3k_icache_sync_range;
 		mco->mco_icache_sync_range_index =
 		    mco->mco_icache_sync_range;
 		mco->mco_pdcache_wbinv_all =
 		    r3k_pdcache_wbinv_all;
 		mco->mco_pdcache_wbinv_range =
 		    r3k_pdcache_inv_range;
 		mco->mco_pdcache_wbinv_range_index =
 		    mco->mco_pdcache_wbinv_range;
 		mco->mco_pdcache_inv_range =
 		    r3k_pdcache_inv_range;
 		mco->mco_pdcache_wb_range =
 		    r3k_pdcache_wb_range;
 		uvmexp.ncolors = atop(mci->mci_pdcache_size);
 		break;
 #ifdef ENABLE_MIPS_TX3900
 	case MIPS_TX3900:
 		switch (MIPS_PRID_REV_MAJ(cpu_id)) {
 		case 1:		/* TX3912 */
 			mci->mci_picache_ways = 1;
 			mci->mci_picache_line_size = 16;
 			mci->mci_pdcache_line_size = 4;
 			tx3900_get_cache_config();
 			mci->mci_pdcache_write_through = true;
 			mco->mco_icache_sync_all =
 			    tx3900_icache_sync_all_16;
 			mco->mco_icache_sync_range =
 			    tx3900_icache_sync_range_16;
 			mco->mco_icache_sync_range_index =
 			    tx3900_icache_sync_range_16;
 			mco->mco_pdcache_wbinv_all =
 			    tx3900_pdcache_wbinv_all_4;
 			mco->mco_pdcache_wbinv_range =
 			    tx3900_pdcache_inv_range_4;
 			mco->mco_pdcache_wbinv_range_index =
 			    tx3900_pdcache_inv_range_4;
 			mco->mco_pdcache_inv_range =
 			    tx3900_pdcache_inv_range_4;
 			mco->mco_pdcache_wb_range =
 			    tx3900_pdcache_wb_range_4;
 			break;
 		case 3:		/* TX3922 */
 			mci->mci_picache_ways = 2;
 			mci->mci_picache_line_size = 16;
 			mci->mci_pdcache_line_size = 16;
 			tx3920_get_cache_config();
 			mco->mco_icache_sync_all =
 			    mci->mci_pdcache_write_through ?
 			    tx3900_icache_sync_all_16 :
 			    tx3920_icache_sync_all_16wb;
 			mco->mco_icache_sync_range =
 			    mci->mci_pdcache_write_through ?
 			    tx3920_icache_sync_range_16wt :
 			    tx3920_icache_sync_range_16wb;
 			mco->mco_icache_sync_range_index =
 			    mco->mco_icache_sync_range;
 			mco->mco_pdcache_wbinv_all =
 			    mci->mci_pdcache_write_through ?
 			    tx3920_pdcache_wbinv_all_16wt :
 			    tx3920_pdcache_wbinv_all_16wb;
 			mco->mco_pdcache_wbinv_range =
 			    mci->mci_pdcache_write_through ?
 			    tx3920_pdcache_inv_range_16 :
 			    tx3920_pdcache_wbinv_range_16wb;
 			mco->mco_pdcache_wbinv_range_index =
 			    mco->mco_pdcache_wbinv_range;
 			mco->mco_pdcache_inv_range =
 			    tx3920_pdcache_inv_range_16;
 			mco->mco_pdcache_wb_range =
 			    mci->mci_pdcache_write_through ?
 			    tx3920_pdcache_wb_range_16wt :
 			    tx3920_pdcache_wb_range_16wb;
 			break;
 		default:
 			panic("mips_config_cache: unsupported TX3900");
+		}
 		mci->mci_pdcache_ways = 2;
 		tx3900_get_cache_config();
 		/* change to write-through mode */
 		tx39_cache_config_write_through();
 		uvmexp.ncolors = atop(mci->mci_pdcache_size) / mci->mci_pdcache_ways;
 		break;
 #endif /* ENABLE_MIPS_TX3900 */
 #endif /* MIPS1 */
 #if defined(MIPS3) || defined(MIPS4)
 	case MIPS_R4100:
 		if ((mips3_cp0_config_read() & MIPS3_CONFIG_CS) != 0)
 			csizebase = MIPS3_CONFIG_C_4100BASE;
 		/*
 		 * R4100 (NEC VR series) revision number means:
+		 *
 		 *		MIPS_PRID_REV_MAJ	MIPS_PRID_REV_MIN
 		 * VR4102	4			?
 		 * VR4111	5			?
 		 * VR4181	5			?
 		 * VR4121	6			?
 		 * VR4122	7			0 or 1
 		 * VR4181A	7			3 <
 		 * VR4131	8			?
 		 */
 		/* Vr4131 has R4600 style 2-way set-associative cache */
 		if (MIPS_PRID_REV_MAJ(cpu_id) == 8)
 			goto primary_cache_is_2way;
 		/* FALLTHROUGH */
 	case MIPS_R4000:
 	case MIPS_R4300:
 		mci->mci_picache_ways = 1;
 		mci->mci_pdcache_ways = 1;
 		mci->mci_sdcache_ways = 1;
 		mips3_get_cache_config(csizebase);
 		if (mci->mci_picache_size > PAGE_SIZE ||
 		    mci->mci_pdcache_size > PAGE_SIZE)
 			/* no VCE support if there is no L2 cache */
 			mci->mci_cache_virtual_alias = true;
 		switch (mci->mci_picache_line_size) {
 		case 16:
 			mco->mco_icache_sync_all =
 			    r4k_icache_sync_all_16;
 			mco->mco_icache_sync_range =
 			    r4k_icache_sync_range_16;
 			mco->mco_icache_sync_range_index =
 			    r4k_icache_sync_range_index_16;
 			break;
 		case 32:
 			mco->mco_icache_sync_all =
 			    r4k_icache_sync_all_32;
 			mco->mco_icache_sync_range =
 			    r4k_icache_sync_range_32;
 			mco->mco_icache_sync_range_index =
 			    r4k_icache_sync_range_index_32;
 			break;
 		default:
 			panic("r4k picache line size %d",
 			    mci->mci_picache_line_size);
+		}
 		switch (mci->mci_pdcache_line_size) {
 		case 16:
 			mco->mco_pdcache_wbinv_all =
 			    r4k_pdcache_wbinv_all_16;
 			mco->mco_pdcache_wbinv_range =
 			    r4k_pdcache_wbinv_range_16;
 			mco->mco_pdcache_wbinv_range_index =
 			    r4k_pdcache_wbinv_range_index_16;
 			mco->mco_pdcache_inv_range =
 			    r4k_pdcache_inv_range_16;
 			mco->mco_pdcache_wb_range =
 			    r4k_pdcache_wb_range_16;
 			break;
 		case 32:
 			mco->mco_pdcache_wbinv_all =
 			    r4k_pdcache_wbinv_all_32;
 			mco->mco_pdcache_wbinv_range =
 			    r4k_pdcache_wbinv_range_32;
 			mco->mco_pdcache_wbinv_range_index =
 			    r4k_pdcache_wbinv_range_index_32;
 			mco->mco_pdcache_inv_range =
 			    r4k_pdcache_inv_range_32;
 			mco->mco_pdcache_wb_range =
 			    r4k_pdcache_wb_range_32;
 			break;
 		default:
 			panic("r4k pdcache line size %d",
 			    mci->mci_pdcache_line_size);
+		}
 		/* Virtually-indexed cache; no use for colors. */
 		break;
 	case MIPS_R4600:
 #ifdef ENABLE_MIPS_R4700
 	case MIPS_R4700:
 #endif
 #ifndef ENABLE_MIPS_R3NKK
 	case MIPS_R5000:
 #endif
 	case MIPS_RM5200:
 primary_cache_is_2way:
 		mci->mci_picache_ways = 2;
 		mci->mci_pdcache_ways = 2;
 		mips3_get_cache_config(csizebase);
 		if ((mci->mci_picache_size / mci->mci_picache_ways) > PAGE_SIZE ||
 		    (mci->mci_pdcache_size / mci->mci_pdcache_ways) > PAGE_SIZE)
 			mci->mci_cache_virtual_alias = true;
 		switch (mci->mci_picache_line_size) {
 		case 32:
 			mco->mco_icache_sync_all =
 			    r5k_icache_sync_all_32;
 			mco->mco_icache_sync_range =
 			    r5k_icache_sync_range_32;
 			mco->mco_icache_sync_range_index =
 			    r5k_icache_sync_range_index_32;
 			break;
 		default:
 			panic("r5k picache line size %d",
 			    mci->mci_picache_line_size);
+		}
 		switch (mci->mci_pdcache_line_size) {
 		case 16:
 			mco->mco_pdcache_wbinv_all =
 			    r5k_pdcache_wbinv_all_16;
 			mco->mco_pdcache_wbinv_range =
 			    r5k_pdcache_wbinv_range_16;
 			mco->mco_pdcache_wbinv_range_index =
 			    r5k_pdcache_wbinv_range_index_16;
 			mco->mco_pdcache_inv_range =
 			    r5k_pdcache_inv_range_16;
 			mco->mco_pdcache_wb_range =
 			    r5k_pdcache_wb_range_16;
 			break;
 		case 32:
 			mco->mco_pdcache_wbinv_all =
 			    r5k_pdcache_wbinv_all_32;
 			mco->mco_pdcache_wbinv_range =
 			    r5k_pdcache_wbinv_range_32;
 			mco->mco_pdcache_wbinv_range_index =
 			    r5k_pdcache_wbinv_range_index_32;
 			mco->mco_pdcache_inv_range =
 			    r5k_pdcache_inv_range_32;
 			mco->mco_pdcache_wb_range =
 			    r5k_pdcache_wb_range_32;
 			break;
 		default:
 			panic("r5k pdcache line size %d",
 			    mci->mci_pdcache_line_size);
+		}
 		/*
 		 * Deal with R4600 chip bugs.
 		 */
 		if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 &&
 		    MIPS_PRID_REV_MAJ(cpu_id) == 1) {
 			KASSERT(mci->mci_pdcache_line_size == 32);
 			mco->mco_pdcache_wbinv_range =
 			    r4600v1_pdcache_wbinv_range_32;
 			mco->mco_pdcache_inv_range =
 			    r4600v1_pdcache_inv_range_32;
 			mco->mco_pdcache_wb_range =
 			    r4600v1_pdcache_wb_range_32;
 		} else if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 &&
 			   MIPS_PRID_REV_MAJ(cpu_id) == 2) {
 			KASSERT(mci->mci_pdcache_line_size == 32);
 			mco->mco_pdcache_wbinv_range =
 			    r4600v2_pdcache_wbinv_range_32;
 			mco->mco_pdcache_inv_range =
 			    r4600v2_pdcache_inv_range_32;
 			mco->mco_pdcache_wb_range =
 			    r4600v2_pdcache_wb_range_32;
+		}
 		/*
 		 * Deal with VR4131 chip bugs.
 		 */
 		if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
 		    MIPS_PRID_REV_MAJ(cpu_id) == 8) {
 			KASSERT(mci->mci_pdcache_line_size == 16);
 			mco->mco_pdcache_wbinv_range =
 			    vr4131v1_pdcache_wbinv_range_16;
+		}
 		/* Virtually-indexed cache; no use for colors. */
 		break;
 #ifdef ENABLE_MIPS4_CACHE_R10K
 	case MIPS_R10000:
 	case MIPS_R12000:
 	case MIPS_R14000:
 		mci->mci_picache_ways = 2;
 		mci->mci_pdcache_ways = 2;
 		mci->mci_sdcache_ways = 2;
 		mips4_get_cache_config(csizebase);
 		/* VCE is handled by hardware */
 		mco->mco_icache_sync_all =
 		    r10k_icache_sync_all;
 		mco->mco_icache_sync_range =
 		    r10k_icache_sync_range;
 		mco->mco_icache_sync_range_index =
 		    r10k_icache_sync_range_index;
 		mco->mco_pdcache_wbinv_all =
 		    r10k_pdcache_wbinv_all;
 		mco->mco_pdcache_wbinv_range =
 		    r10k_pdcache_wbinv_range;
 		mco->mco_pdcache_wbinv_range_index =
 		    r10k_pdcache_wbinv_range_index;
 		mco->mco_pdcache_inv_range =
 		    r10k_pdcache_inv_range;
 		mco->mco_pdcache_wb_range =
 		    r10k_pdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_picache_ways = 4;
+		mci->mci_picache_ways = 4;
-		mips_pdcache_ways = 4;
+		mci->mci_pdcache_ways = 4;
 		mips3_get_cache_config(csizebase);
-		mips_sdcache_line_size = 32;	/* don't trust config reg */
+		mci->mci_sdcache_line_size = 32;	/* don't trust config reg */
-		if (mips_picache_size / mips_picache_ways > PAGE_SIZE ||
+		if (mci->mci_picache_size / mci->mci_picache_ways > PAGE_SIZE ||
-		    mips_pdcache_size / mips_pdcache_ways > PAGE_SIZE)
+		    mci->mci_pdcache_size / mci->mci_pdcache_ways > PAGE_SIZE)
-			mips_cache_virtual_alias = 1;
+			mci->mci_cache_virtual_alias = 1;
-		mips_cache_ops.mco_icache_sync_all =
+		mco->mco_icache_sync_all =
 		    ls2_icache_sync_all;
-		mips_cache_ops.mco_icache_sync_range =
+		mco->mco_icache_sync_range =
 		    ls2_icache_sync_range;
-		mips_cache_ops.mco_icache_sync_range_index =
+		mco->mco_icache_sync_range_index =
 		    ls2_icache_sync_range_index;
-		mips_cache_ops.mco_pdcache_wbinv_all =
+		mco->mco_pdcache_wbinv_all =
 		    ls2_pdcache_wbinv_all;
-		mips_cache_ops.mco_pdcache_wbinv_range =
+		mco->mco_pdcache_wbinv_range =
 		    ls2_pdcache_wbinv_range;
-		mips_cache_ops.mco_pdcache_wbinv_range_index =
+		mco->mco_pdcache_wbinv_range_index =
 		    ls2_pdcache_wbinv_range_index;
-		mips_cache_ops.mco_pdcache_inv_range =
+		mco->mco_pdcache_inv_range =
 		    ls2_pdcache_inv_range;
-		mips_cache_ops.mco_pdcache_wb_range =
+		mco->mco_pdcache_wb_range =
 		    ls2_pdcache_wb_range;
 		/*
 		 * For current version chips, [the] operating system is
 		 * obliged to eliminate the potential for virtual aliasing.
 		 */
-		uvmexp.ncolors = mips_pdcache_ways;
+		uvmexp.ncolors = mci->mci_pdcache_ways;
 		break;
 #endif
 #endif /* MIPS3 || MIPS4 */
 	default:
 		panic("can't handle primary cache on impl 0x%x",
 		    MIPS_PRID_IMPL(cpu_id));
+	}
 	/*
 	 * Compute the "way mask" for each cache.
 	 */
 	if (mci->mci_picache_size) {
 		KASSERT(mci->mci_picache_ways != 0);
 		mci->mci_picache_way_size = (mci->mci_picache_size / mci->mci_picache_ways);
 		mci->mci_picache_way_mask = mci->mci_picache_way_size - 1;
+	}
 	if (mci->mci_pdcache_size) {
 		KASSERT(mci->mci_pdcache_ways != 0);
 		mci->mci_pdcache_way_size = (mci->mci_pdcache_size / mci->mci_pdcache_ways);
 		mci->mci_pdcache_way_mask = mci->mci_pdcache_way_size - 1;
+	}
 	mips_dcache_compute_align();
 	if (mci->mci_sdcache_line_size == 0)
 		return;
 	/*
 	 * Configure the secondary cache.
 	 */
 	switch (MIPS_PRID_IMPL(cpu_id)) {
 #if defined(MIPS3) || defined(MIPS4)
 	case MIPS_R4000:
 		/*
 		 * R4000/R4400 detects virtual alias by VCE as if
 		 * its primary cache size were 32KB, because it always
 		 * compares 3 bits of vaddr[14:12] which causes
 		 * primary cache miss and PIdx[2:0] in the secondary
 		 * cache tag regardless of its primary cache size.
 		 * i.e. VCE could happen even if there is no actual
 		 * virtual alias on its 8KB or 16KB primary cache
 		 * which has only 1 or 2 bit valid PIdx in 4KB page.
 		 * Actual primary cache size is ignored wrt VCE
 		 * and virtual aliases are resolved by the VCE hander,
 		 * but it's still worth to avoid unnecessary VCE by
 		 * setting alias mask and prefer mask to 32K, though
 		 * some other possible aliases (maybe caused by KSEG0
 		 * accesses which can't be managed by PMAP_PREFER(9))
 		 * will still be resolved by the VCED/VCEI handler.
 		 */
 		mci->mci_cache_alias_mask =
 		    (MIPS3_MAX_PCACHE_SIZE - 1) & ~PAGE_MASK;	/* va[14:12] */
 		mci->mci_cache_prefer_mask = MIPS3_MAX_PCACHE_SIZE - 1;
 		mci->mci_cache_virtual_alias = 0;
 		/* FALLTHROUGH */
 	case MIPS_R4600:
 #ifdef ENABLE_MIPS_R4700
 	case MIPS_R4700:
 #endif
 		switch (mci->mci_sdcache_ways) {
 		case 1:
 			switch (mci->mci_sdcache_line_size) {
 			case 32:
 				mco->mco_sdcache_wbinv_all =
 				    r4k_sdcache_wbinv_all_32;
 				mco->mco_sdcache_wbinv_range =
 				    r4k_sdcache_wbinv_range_32;
 				mco->mco_sdcache_wbinv_range_index =
 				    r4k_sdcache_wbinv_range_index_32;
 				mco->mco_sdcache_inv_range =
 				    r4k_sdcache_inv_range_32;
 				mco->mco_sdcache_wb_range =
 				    r4k_sdcache_wb_range_32;
 				break;
 			case 16:
 			case 64:
 				mco->mco_sdcache_wbinv_all =
 				    r4k_sdcache_wbinv_all_generic;
 				mco->mco_sdcache_wbinv_range =
 				    r4k_sdcache_wbinv_range_generic;
 				mco->mco_sdcache_wbinv_range_index =
 				    r4k_sdcache_wbinv_range_index_generic;
 				mco->mco_sdcache_inv_range =
 				    r4k_sdcache_inv_range_generic;
 				mco->mco_sdcache_wb_range =
 				    r4k_sdcache_wb_range_generic;
 				break;
 			case 128:
 				mco->mco_sdcache_wbinv_all =
 				    r4k_sdcache_wbinv_all_128;
 				mco->mco_sdcache_wbinv_range =
 				    r4k_sdcache_wbinv_range_128;
 				mco->mco_sdcache_wbinv_range_index =
 				    r4k_sdcache_wbinv_range_index_128;
 				mco->mco_sdcache_inv_range =
 				    r4k_sdcache_inv_range_128;
 				mco->mco_sdcache_wb_range =
 				    r4k_sdcache_wb_range_128;
 				break;
 			default:
 				panic("r4k sdcache %d way line size %d",
 				    mci->mci_sdcache_ways, mci->mci_sdcache_line_size);
+			}
 			break;
 		default:
 			panic("r4k sdcache %d way line size %d",
 			    mci->mci_sdcache_ways, mci->mci_sdcache_line_size);
+		}
 		break;
 #ifndef ENABLE_MIPS_R3NKK
 	case MIPS_R5000:
 #endif
 	case MIPS_RM5200:
 		mci->mci_sdcache_write_through = true;
 		mco->mco_sdcache_wbinv_all =
 		    r5k_sdcache_wbinv_all;
 		mco->mco_sdcache_wbinv_range =
 		    r5k_sdcache_wbinv_range;
 		mco->mco_sdcache_wbinv_range_index =
 		    r5k_sdcache_wbinv_range_index;
 		mco->mco_sdcache_inv_range =
 		    r5k_sdcache_wbinv_range;
 		mco->mco_sdcache_wb_range =
 		    r5k_sdcache_wb_range;
 		break;
 #ifdef ENABLE_MIPS4_CACHE_R10K
 	case MIPS_R10000:
 	case MIPS_R12000:
 	case MIPS_R14000:
 		mco->mco_sdcache_wbinv_all =
 		    r10k_sdcache_wbinv_all;
 		mco->mco_sdcache_wbinv_range =
 		    r10k_sdcache_wbinv_range;
 		mco->mco_sdcache_wbinv_range_index =
 		    r10k_sdcache_wbinv_range_index;
 		mco->mco_sdcache_inv_range =
 		    r10k_sdcache_inv_range;
 		mco->mco_sdcache_wb_range =
 		    r10k_sdcache_wb_range;
 		break;
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #ifdef MIPS3_LOONGSON2
 	case MIPS_LOONGSON2:
-		mips_sdcache_ways = 4;
+		mci->mci_sdcache_ways = 4;
-		mips_sdcache_size = 512*1024;
+		mci->mci_sdcache_size = 512*1024;
-		mips_scache_unified = 1;
+		mci->mci_scache_unified = 1;
-		mips_cache_ops.mco_sdcache_wbinv_all =
+		mco->mco_sdcache_wbinv_all =
 		    ls2_sdcache_wbinv_all;
-		mips_cache_ops.mco_sdcache_wbinv_range =
+		mco->mco_sdcache_wbinv_range =
 		    ls2_sdcache_wbinv_range;
-		mips_cache_ops.mco_sdcache_wbinv_range_index =
+		mco->mco_sdcache_wbinv_range_index =
 		    ls2_sdcache_wbinv_range_index;
-		mips_cache_ops.mco_sdcache_inv_range =
+		mco->mco_sdcache_inv_range =
 		    ls2_sdcache_inv_range;
-		mips_cache_ops.mco_sdcache_wb_range =
+		mco->mco_sdcache_wb_range =
 		    ls2_sdcache_wb_range;
 		/*
 		 * The secondary cache is physically indexed and tagged
 		 */
 		break;
 #endif
 #endif /* MIPS3 || MIPS4 */
 	default:
 		panic("can't handle secondary cache on impl 0x%x",
 		    MIPS_PRID_IMPL(cpu_id));
+	}
 	/*
 	 * Compute the "way mask" for each secondary cache.
 	 */
 	if (mci->mci_sdcache_size) {
 		KASSERT(mci->mci_sdcache_ways != 0);
 		mci->mci_sdcache_way_size = (mci->mci_sdcache_size / mci->mci_sdcache_ways);
 		mci->mci_sdcache_way_mask = mci->mci_sdcache_way_size - 1;
+	}
 	mips_dcache_compute_align();
+}
 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
 void
 mips_config_cache_emips(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	struct mips_cache_ops * const mco = &mips_cache_ops;
 	const mips_prid_t cpu_id = mips_options.mips_cpu_id;
 	KASSERT(PAGE_SIZE != 0);
 	/*
 	 * Configure primary caches.
 	 */
 	switch (MIPS_PRID_IMPL(cpu_id)) {
 	case MIPS_eMIPS:
 		mci->mci_picache_size = 0;
 		mci->mci_pdcache_size = 0;
 		mci->mci_picache_line_size = 4;
 		mci->mci_pdcache_line_size = 4;
 		mci->mci_picache_ways = 1;
 		mci->mci_pdcache_ways = 1;
 		mci->mci_pdcache_write_through = 1;
 		mco->mco_icache_sync_all = no_cache_op;
 		mco->mco_icache_sync_range = no_cache_op_range;
 		mco->mco_icache_sync_range_index = mco->mco_icache_sync_range;
 		mco->mco_pdcache_wbinv_all = no_cache_op;
 		mco->mco_pdcache_wbinv_range = no_cache_op_range;
 		mco->mco_pdcache_wbinv_range_index =
 		    mco->mco_pdcache_wbinv_range;
 		mco->mco_pdcache_inv_range = no_cache_op_range;
 		mco->mco_pdcache_wb_range = no_cache_op_range;
 		uvmexp.ncolors = 1;
 		break;
 	default:
 		panic("%s: unsupported eMIPS", __func__);
+	}
+}
 #endif
 #ifdef MIPS1
 #ifdef ENABLE_MIPS_TX3900
 /*
  * tx3900_get_cache_config:
+ *
  *	Fetch cache size information for the TX3900.
  */
 void
 tx3900_get_cache_config(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	uint32_t config;
 	config = tx3900_cp0_config_read();
 	mci->mci_picache_size = R3900_C_SIZE_MIN <<
 	    ((config & R3900_CONFIG_ICS_MASK) >> R3900_CONFIG_ICS_SHIFT);
 	mci->mci_pdcache_size = R3900_C_SIZE_MIN <<
 	    ((config & R3900_CONFIG_DCS_MASK) >> R3900_CONFIG_DCS_SHIFT);
+}
 /*
  * tx3920_get_cache_config:
+ *
  *	Fetch cache size information for the TX3920.
  */
 void
 tx3920_get_cache_config(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	/* Size is the same as TX3900. */
 	tx3900_get_cache_config();
 	/* Now determine write-through/write-back mode. */
 	if ((tx3900_cp0_config_read() & R3900_CONFIG_WBON) == 0)
 		mci->mci_pdcache_write_through = true;
+}
 /*
  * tx39_cache_config_write_through:
+ *
  *	TX3922 write-through D-cache mode.
  *	for TX3912, no meaning. (no write-back mode)
  */
 void
 tx39_cache_config_write_through(void)
+{
 	u_int32_t r;
 	mips_dcache_wbinv_all();
 	__asm volatile("mfc0 %0, $3" : "=r"(r));
 	r &= 0xffffdfff;
 	__asm volatile("mtc0 %0, $3" : : "r"(r));
+}
 #endif /* ENABLE_MIPS_TX3900 */
 #endif /* MIPS1 */
 #if defined(MIPS3) || defined(MIPS4)
 /*
  * mips3_get_cache_config:
+ *
  *	Fetch the cache config information for a MIPS-3 or MIPS-4
  *	processor (virtually-indexed cache).
+ *
  *	NOTE: Fetching the size of the secondary cache is something
  *	that platform specific code has to do.  We'd appreciate it
  *	if they initialized the size before now.
+ *
  *	ALSO NOTE: The number of ways in the cache must already be
  *	initialized.
  */
 void
 mips3_get_cache_config(int csizebase)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	const mips_prid_t cpu_id = mips_options.mips_cpu_id;
 	bool has_sdcache_enable = false;
 	uint32_t config = mips3_cp0_config_read();
 	mci->mci_picache_size = MIPS3_CONFIG_CACHE_SIZE(config,
 	    MIPS3_CONFIG_IC_MASK, csizebase, MIPS3_CONFIG_IC_SHIFT);
 	mci->mci_picache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
 	    MIPS3_CONFIG_IB);
 	mci->mci_pdcache_size = MIPS3_CONFIG_CACHE_SIZE(config,
 	    MIPS3_CONFIG_DC_MASK, csizebase, MIPS3_CONFIG_DC_SHIFT);
 	mci->mci_pdcache_line_size = MIPS3_CONFIG_CACHE_L1_LSIZE(config,
 	    MIPS3_CONFIG_DB);
 	mci->mci_cache_alias_mask =
 	    ((mci->mci_pdcache_size / mci->mci_pdcache_ways) - 1) & ~PAGE_MASK;
 	mci->mci_cache_prefer_mask =
 	    max(mci->mci_pdcache_size, mci->mci_picache_size) - 1;
 	uvmexp.ncolors = (mci->mci_cache_alias_mask >> PAGE_SHIFT) + 1;
 	switch(MIPS_PRID_IMPL(cpu_id)) {
 #ifndef ENABLE_MIPS_R3NKK
 	case MIPS_R5000:
 #endif
 	case MIPS_RM5200:
 		has_sdcache_enable = true;
 		break;
+	}
 	/*
  	 * If CPU has a software-enabled L2 cache, check both if it's
 	 * present and if it's enabled before making assumptions the
 	 * L2 is usable.  If the L2 is disabled, we treat it the same
 	 * as if there were no L2 cache.
 	 */
 	if ((config & MIPS3_CONFIG_SC) == 0) {
 		if (has_sdcache_enable == 0 ||
 		    (has_sdcache_enable && (config & MIPS3_CONFIG_SE))) {
 			mci->mci_sdcache_line_size =
 				MIPS3_CONFIG_CACHE_L2_LSIZE(config);
 			if ((config & MIPS3_CONFIG_SS) == 0)
 				mci->mci_scache_unified = true;
 		} else {
 #ifdef CACHE_DEBUG
 			printf("External cache detected, but is disabled -- WILL NOT ENABLE!\n");
 #endif	/* CACHE_DEBUG */
+		}
+	}
+}
 #ifdef ENABLE_MIPS4_CACHE_R10K
 void
 mips4_get_cache_config(int csizebase)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	uint32_t config = mips3_cp0_config_read();
 	mci->mci_picache_size = MIPS4_CONFIG_CACHE_SIZE(config,
 	    MIPS4_CONFIG_IC_MASK, csizebase, MIPS4_CONFIG_IC_SHIFT);
 	mci->mci_picache_line_size = 64;	/* 64 Byte */
 	mci->mci_pdcache_size = MIPS4_CONFIG_CACHE_SIZE(config,
 	    MIPS4_CONFIG_DC_MASK, csizebase, MIPS4_CONFIG_DC_SHIFT);
 	mci->mci_pdcache_line_size = 32;	/* 32 Byte */
 	mci->mci_cache_alias_mask =
 	    ((mci->mci_pdcache_size / mci->mci_pdcache_ways) - 1) & ~PAGE_MASK;
 	mci->mci_cache_prefer_mask =
 	    max(mci->mci_pdcache_size, mci->mci_picache_size) - 1;
+}
 #endif /* ENABLE_MIPS4_CACHE_R10K */
 #endif /* MIPS3 || MIPS4 */
 #endif /* MIPS1 || MIPS3 || MIPS4 */
 #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
 static void cache_noop(void) __unused;
 static void cache_noop(void) {}
 static void
 mips_config_cache_modern(void)
+{
 	struct mips_cache_info * const mci = &mips_cache_info;
 	struct mips_cache_ops * const mco = &mips_cache_ops;
 	/* MIPS32/MIPS64, use coprocessor 0 config registers */
 	uint32_t cfg, cfg1;
 	cfg = mips3_cp0_config_read();
 	cfg1 = mipsNN_cp0_config1_read();
 #ifdef MIPS_DISABLE_L1_CACHE
 	cfg1 &= ~MIPSNN_CFG1_IL_MASK;
 	cfg1 &= ~MIPSNN_CFG1_DL_MASK;
 	mipsNN_cp0_config1_write(cfg1);
 #endif
 	/* figure out Dcache params. */
 	switch (MIPSNN_GET(CFG1_DL, cfg1)) {
 	case MIPSNN_CFG1_DL_NONE:
 		mci->mci_pdcache_line_size = mci->mci_pdcache_way_size =
 		    mci->mci_pdcache_ways = 0;
 		break;
 	case MIPSNN_CFG1_DL_RSVD:
 		panic("reserved MIPS32/64 Dcache line size");
 		break;
 	default:
 		if (MIPSNN_GET(CFG1_DS, cfg1) == MIPSNN_CFG1_DS_RSVD)
 			panic("reserved MIPS32/64 Dcache sets per way");
 		mci->mci_pdcache_line_size = MIPSNN_CFG1_DL(cfg1);
 		mci->mci_pdcache_way_size =
 		    mci->mci_pdcache_line_size * MIPSNN_CFG1_DS(cfg1);
 		mci->mci_pdcache_ways = MIPSNN_CFG1_DA(cfg1) + 1;
 		/*
 		 * Compute the total size and "way mask" for the
 		 * primary Dcache.
 		 */
 		mci->mci_pdcache_size =
 		    mci->mci_pdcache_way_size * mci->mci_pdcache_ways;
 		mci->mci_pdcache_way_mask = mci->mci_pdcache_way_size - 1;
 		uvmexp.ncolors = atop(mci->mci_pdcache_size) / mci->mci_pdcache_ways;
 		break;
+	}
 	/* figure out Icache params. */
 	switch (MIPSNN_GET(CFG1_IL, cfg1)) {
 	case MIPSNN_CFG1_IL_NONE:
 		mci->mci_picache_line_size = mci->mci_picache_way_size =
 		    mci->mci_picache_ways = 0;
 		break;
 	case MIPSNN_CFG1_IL_RSVD:
 		panic("reserved MIPS32/64 Icache line size");
 		break;
 	default:
 		if (MIPSNN_GET(CFG1_IS, cfg1) == MIPSNN_CFG1_IS_RSVD)
 			panic("reserved MIPS32/64 Icache sets per way");
 		mci->mci_picache_line_size = MIPSNN_CFG1_IL(cfg1);
 		mci->mci_picache_way_size =
 		    mci->mci_picache_line_size * MIPSNN_CFG1_IS(cfg1);
 		mci->mci_picache_ways = MIPSNN_CFG1_IA(cfg1) + 1;
 		/*
 		 * Compute the total size and "way mask" for the
 		 * primary Dcache.
 		 */
 		mci->mci_picache_size =
 		    mci->mci_picache_way_size * mci->mci_picache_ways;
 		mci->mci_picache_way_mask = mci->mci_picache_way_size - 1;
 		break;
+	}
 #define CACHE_DEBUG
 #ifdef CACHE_DEBUG
 	printf("MIPS32/64 params: cpu arch: %d\n", mips_options.mips_cpu_arch);
 	printf("MIPS32/64 params: TLB entries: %d\n", mips_options.mips_num_tlb_entries);
 	if (mci->mci_picache_line_size == 0)
 		printf("MIPS32/64 params: no Icache\n");
 	else {
 		printf("MIPS32/64 params: Icache: line = %d, total = %d, "
 		    "ways = %d\n", mci->mci_picache_line_size,
 		    mci->mci_picache_way_size * mci->mci_picache_ways,
 		    mci->mci_picache_ways);
 		printf("\t\t sets = %d\n", (mci->mci_picache_way_size *
 		    mci->mci_picache_ways / mci->mci_picache_line_size) /
 		    mci->mci_picache_ways);
+	}
 	if (mci->mci_pdcache_line_size == 0)
 		printf("MIPS32/64 params: no Dcache\n");
 	else {
 		printf("MIPS32/64 params: Dcache: line = %d, total = %d, "
 		    "ways = %d\n", mci->mci_pdcache_line_size,
 		    mci->mci_pdcache_way_size * mci->mci_pdcache_ways,
 		    mci->mci_pdcache_ways);
 		printf("\t\t sets = %d\n", (mci->mci_pdcache_way_size *
 		    mci->mci_pdcache_ways / mci->mci_pdcache_line_size) /
 		    mci->mci_pdcache_ways);
+	}
 #endif /* CACHE_DEBUG */
 	switch (mci->mci_picache_line_size) {
 	case 16:
 		mco->mco_icache_sync_all = mipsNN_icache_sync_all_16;
 		mco->mco_icache_sync_range =
 		    mipsNN_icache_sync_range_16;
 		mco->mco_icache_sync_range_index =
 		    mipsNN_icache_sync_range_index_16;
 		break;
 	case 32:
 		mco->mco_icache_sync_all = mipsNN_icache_sync_all_32;
 		mco->mco_icache_sync_range =
 		    mipsNN_icache_sync_range_32;
 		mco->mco_icache_sync_range_index =
 		    mipsNN_icache_sync_range_index_32;
 		break;
 #ifdef MIPS_DISABLE_L1_CACHE
 	case 0:
 		mco->mco_icache_sync_all = cache_noop;
 		mco->mco_icache_sync_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_icache_sync_range_index =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		break;
 #endif
 	default:
 		panic("no Icache ops for %d byte lines",
 		    mci->mci_picache_line_size);
+	}
 	switch (mci->mci_pdcache_line_size) {
 	case 16:
 		mco->mco_pdcache_wbinv_all =
 		    mco->mco_intern_pdcache_wbinv_all =
 		    mipsNN_pdcache_wbinv_all_16;
 		mco->mco_pdcache_wbinv_range =
 		    mipsNN_pdcache_wbinv_range_16;
 		mco->mco_pdcache_wbinv_range_index =
 		    mco->mco_intern_pdcache_wbinv_range_index =
 		    mipsNN_pdcache_wbinv_range_index_16;
 		mco->mco_pdcache_inv_range =
 		    mipsNN_pdcache_inv_range_16;
 		mco->mco_pdcache_wb_range =
 		    mco->mco_intern_pdcache_wb_range =
 		    mipsNN_pdcache_wb_range_16;
 		break;
 	case 32:
 		mco->mco_pdcache_wbinv_all =
 		    mco->mco_intern_pdcache_wbinv_all =
 		    mipsNN_pdcache_wbinv_all_32;
 		mco->mco_pdcache_wbinv_range =
 		    mipsNN_pdcache_wbinv_range_32;
 		mco->mco_pdcache_wbinv_range_index =
 		    mco->mco_intern_pdcache_wbinv_range_index =
 		    mipsNN_pdcache_wbinv_range_index_32;
 		mco->mco_pdcache_inv_range =
 		    mipsNN_pdcache_inv_range_32;
 		mco->mco_pdcache_wb_range =
 		    mco->mco_intern_pdcache_wb_range =
 		    mipsNN_pdcache_wb_range_32;
 		break;
 #ifdef MIPS_DISABLE_L1_CACHE
 	case 0:
 		mco->mco_pdcache_wbinv_all = cache_noop;
 		mco->mco_intern_pdcache_wbinv_all = cache_noop;
 		mco->mco_pdcache_wbinv_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_wbinv_range_index =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_intern_pdcache_wbinv_range_index =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_inv_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_wb_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_intern_pdcache_wb_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		break;
 #endif
 	default:
 		panic("no Dcache ops for %d byte lines",
 		    mci->mci_pdcache_line_size);
+	}
 	mipsNN_cache_init(cfg, cfg1);
 	if (mips_options.mips_cpu_flags &
 	    (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
 #ifdef CACHE_DEBUG
 		printf("  Dcache is coherent\n");
 #endif
 		mco->mco_pdcache_wbinv_all = cache_noop;
 		mco->mco_pdcache_wbinv_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_wbinv_range_index =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_inv_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_pdcache_wb_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
+	}
 	if (mips_options.mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
 #ifdef CACHE_DEBUG
 		printf("  Icache is coherent against Dcache\n");
 #endif
 		mco->mco_intern_pdcache_wbinv_all =
 		    cache_noop;
 		mco->mco_intern_pdcache_wbinv_range_index =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
 		mco->mco_intern_pdcache_wb_range =
 		    (void (*)(vaddr_t, vsize_t))cache_noop;
+	}
+}
 #endif /* MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 > 0 */

	@@ -1,299 +1,306 @@		@@ -1,299 +1,306 @@
1	/* $NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $ */	1	/* $NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $ */
2		2
3	/*-	3	/*-
4	* Copyright (c) 2009 The NetBSD Foundation, Inc.	4	* Copyright (c) 2009 The NetBSD Foundation, Inc.
5	* All rights reserved.	5	* All rights reserved.
6	*	6	*
7	* This code is derived from software contributed to The NetBSD Foundation	7	* This code is derived from software contributed to The NetBSD Foundation
8	* by Matt Thomas <matt@3am-software.com>.	8	* by Matt Thomas <matt@3am-software.com>.
9	*	9	*
10	* Redistribution and use in source and binary forms, with or without	10	* Redistribution and use in source and binary forms, with or without
11	* modification, are permitted provided that the following conditions	11	* modification, are permitted provided that the following conditions
12	* are met:	12	* are met:
13	* 1. Redistributions of source code must retain the above copyright	13	* 1. Redistributions of source code must retain the above copyright
14	* notice, this list of conditions and the following disclaimer.	14	* notice, this list of conditions and the following disclaimer.
15	* 2. Redistributions in binary form must reproduce the above copyright	15	* 2. Redistributions in binary form must reproduce the above copyright
16	* notice, this list of conditions and the following disclaimer in the	16	* notice, this list of conditions and the following disclaimer in the
17	* documentation and/or other materials provided with the distribution.	17	* documentation and/or other materials provided with the distribution.
18	*	18	*
19	* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS	19	* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED	20	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21	* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR	21	* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS	22	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR	23	* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF	24	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS	25	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN	26	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)	27	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE	28	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29	* POSSIBILITY OF SUCH DAMAGE.	29	* POSSIBILITY OF SUCH DAMAGE.
30	*/	30	*/
31		31
32	#include <sys/cdefs.h>	32	#include <sys/cdefs.h>
33	__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.3 2009/08/11 00:34:29 matt Exp $");	33	__KERNEL_RCSID(0, "$NetBSD: cache_ls2.c,v 1.4 2011/06/08 17:47:48 bouyer Exp $");
34		34
35	#include <sys/param.h>	35	#include <sys/param.h>
36		36
37	#include <mips/cache.h>	37	#include <mips/cache.h>
38	#include <mips/cache_ls2.h>	38	#include <mips/cache_ls2.h>
39	#include <mips/locore.h>	39	#include <mips/locore.h>
40		40
41	/*	41	/*
42	* Cache operations for Loongson2-style caches:	42	* Cache operations for Loongson2-style caches:
43	*	43	*
44	* - 4-way set-associative 32b/l	44	* - 4-way set-associative 32b/l
45	* - Write-back	45	* - Write-back
46	* - Primary is virtually indexed, physically tagged	46	* - Primary is virtually indexed, physically tagged
47	* - Seconadry is physically indexed, physically tagged	47	* - Seconadry is physically indexed, physically tagged
48	*/	48	*/
49		49
50	#define round_line(x) (((x) + 31) & ~31)	50	#define round_line(x) (((x) + 31) & ~31)
51	#define trunc_line(x) ((x) & ~31)	51	#define trunc_line(x) ((x) & ~31)
52		52
53	__asm(".set mips3");	53	__asm(".set mips3");
54		54
55	void	55	void
56	ls2_icache_sync_range(vaddr_t va, vsize_t size)	56	ls2_icache_sync_range(vaddr_t va, vsize_t size)
57	{	57	{
		58	struct mips_cache_info * const mci = &mips_cache_info;
58	const vaddr_t eva = round_line(va + size);	59	const vaddr_t eva = round_line(va + size);
59		60
60	va = trunc_line(va);	61	va = trunc_line(va);
61		62
62	if (va + mips_picache_size <= eva) {	63	if (va + mci->mci_picache_size <= eva) {
63	ls2_icache_sync_all();	64	ls2_icache_sync_all();
64	return;	65	return;
65	}	66	}
66		67
67	for (; va + 8 * 32 <= eva; va += 8 * 32) {	68	for (; va + 8 * 32 <= eva; va += 8 * 32) {
68	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);	69	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);
69	cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);	70	cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);
70	}	71	}
71		72
72	for (; va < eva; va += 32) {	73	for (; va < eva; va += 32) {
73	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);	74	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);
74	cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);	75	cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);
75	}	76	}
76		77
77	__asm volatile("sync");	78	__asm volatile("sync");
78	}	79	}
79		80
80	void	81	void
81	ls2_icache_sync_range_index(vaddr_t va, vsize_t size)	82	ls2_icache_sync_range_index(vaddr_t va, vsize_t size)
82	{	83	{
83	vaddr_t eva;	84	vaddr_t eva;
		85	struct mips_cache_info * const mci = &mips_cache_info;
84		86
85	/*	87	/*
86	* Since we're doing Index ops, we expect to not be able	88	* Since we're doing Index ops, we expect to not be able
87	* to access the address we've been given. So, get the	89	* to access the address we've been given. So, get the
88	* bits that determine the cache index, and make a KSEG0	90	* bits that determine the cache index, and make a KSEG0
89	* address out of them.	91	* address out of them.
90	*/	92	*/
91		93
92	va = MIPS_PHYS_TO_KSEG0(va & mips_picache_way_mask);	94	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
93	eva = round_line(va + size);	95	eva = round_line(va + size);
94	va = trunc_line(va);	96	va = trunc_line(va);
95		97
96	if (va + mips_picache_way_size < eva) {	98	if (va + mci->mci_picache_way_size < eva) {
97	va = MIPS_PHYS_TO_KSEG0(0);	99	va = MIPS_PHYS_TO_KSEG0(0);
98	eva = mips_picache_way_size;	100	eva = mci->mci_picache_way_size;
99	}	101	}
100		102
101	for (; va + 8 * 32 <= eva; va += 8 * 32) {	103	for (; va + 8 * 32 <= eva; va += 8 * 32) {
102	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	104	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
103	cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);	105	cache_op_ls2_8line(va, CACHEOP_LS2_I_INDEX_INV);
104	}	106	}
105		107
106	for (; va < eva; va += 32) {	108	for (; va < eva; va += 32) {
107	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	109	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
108	cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);	110	cache_op_ls2_line(va, CACHEOP_LS2_I_INDEX_INV);
109	}	111	}
110		112
111	__asm volatile("sync");	113	__asm volatile("sync");
112	}	114	}
113		115
114	void	116	void
115	ls2_icache_sync_all(void)	117	ls2_icache_sync_all(void)
116	{	118	{
117	ls2_icache_sync_range_index(0, mips_picache_way_size);	119	struct mips_cache_info * const mci = &mips_cache_info;
		120	ls2_icache_sync_range_index(0, mci->mci_picache_way_size);
118	}	121	}
119		122
120	void	123	void
121	ls2_pdcache_inv_range(vaddr_t va, vsize_t size)	124	ls2_pdcache_inv_range(vaddr_t va, vsize_t size)
122	{	125	{
123	const vaddr_t eva = round_line(va + size);	126	const vaddr_t eva = round_line(va + size);
124		127
125	va = trunc_line(va);	128	va = trunc_line(va);
126		129
127	for (; va + 8 * 32 <= eva; va += 8 * 32) {	130	for (; va + 8 * 32 <= eva; va += 8 * 32) {
128	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);	131	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);
129	}	132	}
130		133
131	for (; va < eva; va += 32) {	134	for (; va < eva; va += 32) {
132	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV);	135	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV);
133	}	136	}
134		137
135	__asm volatile("sync");	138	__asm volatile("sync");
136	}	139	}
137		140
138	void	141	void
139	ls2_pdcache_wbinv_range(vaddr_t va, vsize_t size)	142	ls2_pdcache_wbinv_range(vaddr_t va, vsize_t size)
140	{	143	{
141	const vaddr_t eva = round_line(va + size);	144	const vaddr_t eva = round_line(va + size);
142		145
143	va = trunc_line(va);	146	va = trunc_line(va);
144		147
145	for (; va + 8 * 32 <= eva; va += 8 * 32) {	148	for (; va + 8 * 32 <= eva; va += 8 * 32) {
146	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);	149	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);
147	}	150	}
148		151
149	for (; va < eva; va += 32) {	152	for (; va < eva; va += 32) {
150	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);	153	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);
151	}	154	}
152		155
153	__asm volatile("sync");	156	__asm volatile("sync");
154	}	157	}
155		158
156	void	159	void
157	ls2_pdcache_wb_range(vaddr_t va, vsize_t size)	160	ls2_pdcache_wb_range(vaddr_t va, vsize_t size)
158	{	161	{
159	/*	162	/*
160	* Alas, can't writeback without invalidating...	163	* Alas, can't writeback without invalidating...
161	*/	164	*/
162	ls2_pdcache_wbinv_range(va, size);	165	ls2_pdcache_wbinv_range(va, size);
163	}	166	}
164		167
165	void	168	void
166	ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)	169	ls2_pdcache_wbinv_range_index(vaddr_t va, vsize_t size)
167	{	170	{
168	vaddr_t eva;	171	vaddr_t eva;
		172	struct mips_cache_info * const mci = &mips_cache_info;
169		173
170	/*	174	/*
171	* Since we're doing Index ops, we expect to not be able	175	* Since we're doing Index ops, we expect to not be able
172	* to access the address we've been given. So, get the	176	* to access the address we've been given. So, get the
173	* bits that determine the cache index, and make a KSEG0	177	* bits that determine the cache index, and make a KSEG0
174	* address out of them.	178	* address out of them.
175	*/	179	*/
176	va = MIPS_PHYS_TO_KSEG0(va & mips_pdcache_way_mask);	180	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_pdcache_way_mask);
177		181
178	eva = round_line(va + size);	182	eva = round_line(va + size);
179	va = trunc_line(va);	183	va = trunc_line(va);
180		184
181	if (va + mips_pdcache_way_size > eva) {	185	if (va + mci->mci_pdcache_way_size > eva) {
182	va = MIPS_PHYS_TO_KSEG0(0);	186	va = MIPS_PHYS_TO_KSEG0(0);
183	eva = mips_pdcache_way_size;	187	eva = mci->mci_pdcache_way_size;
184	}	188	}
185		189
186	for (; va + 8 * 32 <= eva; va += 8 * 32) {	190	for (; va + 8 * 32 <= eva; va += 8 * 32) {
187	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	191	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
188	}	192	}
189		193
190	for (; va < eva; va += 32) {	194	for (; va < eva; va += 32) {
191	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	195	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
192	}	196	}
193		197
194	__asm volatile("sync");	198	__asm volatile("sync");
195	}	199	}
196		200
197	void	201	void
198	ls2_pdcache_wbinv_all(void)	202	ls2_pdcache_wbinv_all(void)
199	{	203	{
200	ls2_pdcache_wbinv_range_index(0, mips_pdcache_way_size);	204	struct mips_cache_info * const mci = &mips_cache_info;
		205	ls2_pdcache_wbinv_range_index(0, mci->mci_pdcache_way_size);
201	}	206	}
202		207
203	/*	208	/*
204	* Cache operations for secondary caches:	209	* Cache operations for secondary caches:
205	*	210	*
206	* - Direct-mapped	211	* - Direct-mapped
207	* - Write-back	212	* - Write-back
208	* - Physically indexed, physically tagged	213	* - Physically indexed, physically tagged
209	*	214	*
210	*/	215	*/
211		216
212	void	217	void
213	ls2_sdcache_inv_range(vaddr_t va, vsize_t size)	218	ls2_sdcache_inv_range(vaddr_t va, vsize_t size)
214	{	219	{
215	const vaddr_t eva = round_line(va + size);	220	const vaddr_t eva = round_line(va + size);
216		221
217	va = trunc_line(va);	222	va = trunc_line(va);
218		223
219	for (; va + 8 * 32 <= eva; va += 8 * 32) {	224	for (; va + 8 * 32 <= eva; va += 8 * 32) {
220	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);	225	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_INV);
221	cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_INV);	226	cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_INV);
222	}	227	}
223		228
224	for (; va < eva; va += 32) {	229	for (; va < eva; va += 32) {
225	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV);	230	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_INV);
226	cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_INV);	231	cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_INV);
227	}	232	}
228		233
229	__asm volatile("sync");	234	__asm volatile("sync");
230	}	235	}
231		236
232	void	237	void
233	ls2_sdcache_wbinv_range(vaddr_t va, vsize_t size)	238	ls2_sdcache_wbinv_range(vaddr_t va, vsize_t size)
234	{	239	{
235	const vaddr_t eva = round_line(va + size);	240	const vaddr_t eva = round_line(va + size);
236		241
237	va = trunc_line(va);	242	va = trunc_line(va);
238		243
239	for (; va + 8 * 32 <= eva; va += 8 * 32) {	244	for (; va + 8 * 32 <= eva; va += 8 * 32) {
240	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);	245	cache_op_ls2_8line(va, CACHEOP_LS2_D_HIT_WB_INV);
241	cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_WB_INV);	246	cache_op_ls2_8line(va, CACHEOP_LS2_S_HIT_WB_INV);
242	}	247	}
243		248
244	for (; va < eva; va += 32) {	249	for (; va < eva; va += 32) {
245	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);	250	cache_op_ls2_line(va, CACHEOP_LS2_D_HIT_WB_INV);
246	cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_WB_INV);	251	cache_op_ls2_line(va, CACHEOP_LS2_S_HIT_WB_INV);
247	}	252	}
248		253
249	__asm volatile("sync");	254	__asm volatile("sync");
250	}	255	}
251		256
252	void	257	void
253	ls2_sdcache_wb_range(vaddr_t va, vsize_t size)	258	ls2_sdcache_wb_range(vaddr_t va, vsize_t size)
254	{	259	{
255	/*	260	/*
256	* Alas, can't writeback without invalidating...	261	* Alas, can't writeback without invalidating...
257	*/	262	*/
258	ls2_sdcache_wbinv_range(va, size);	263	ls2_sdcache_wbinv_range(va, size);
259	}	264	}
260		265
261	void	266	void
262	ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)	267	ls2_sdcache_wbinv_range_index(vaddr_t va, vsize_t size)
263	{	268	{
264	vaddr_t eva;	269	vaddr_t eva;
		270	struct mips_cache_info * const mci = &mips_cache_info;
265		271
266	/*	272	/*
267	* Since we're doing Index ops, we expect to not be able	273	* Since we're doing Index ops, we expect to not be able
268	* to access the address we've been given. So, get the	274	* to access the address we've been given. So, get the
269	* bits that determine the cache index, and make a KSEG0	275	* bits that determine the cache index, and make a KSEG0
270	* address out of them.	276	* address out of them.
271	*/	277	*/
272	va = MIPS_PHYS_TO_KSEG0(va & mips_sdcache_way_mask);	278	va = MIPS_PHYS_TO_KSEG0(va & mci->mci_sdcache_way_mask);
273		279
274	eva = round_line(va + size);	280	eva = round_line(va + size);
275	va = trunc_line(va);	281	va = trunc_line(va);
276		282
277	if (va + mips_sdcache_way_size > eva) {	283	if (va + mci->mci_sdcache_way_size > eva) {
278	va = MIPS_PHYS_TO_KSEG0(0);	284	va = MIPS_PHYS_TO_KSEG0(0);
279	eva = va + mips_sdcache_way_size;	285	eva = va + mci->mci_sdcache_way_size;
280	}	286	}
281		287
282	for (; va + 8 * 32 <= eva; va += 8 * 32) {	288	for (; va + 8 * 32 <= eva; va += 8 * 32) {
283	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	289	cache_op_ls2_8line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
284	cache_op_ls2_8line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);	290	cache_op_ls2_8line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
285	}	291	}
286		292
287	for (; va < eva; va += 32) {	293	for (; va < eva; va += 32) {
288	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);	294	cache_op_ls2_line_4way(va, CACHEOP_LS2_D_INDEX_WB_INV);
289	cache_op_ls2_line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);	295	cache_op_ls2_line_4way(va, CACHEOP_LS2_S_INDEX_WB_INV);
290	}	296	}
291		297
292	__asm volatile("sync");	298	__asm volatile("sync");
293	}	299	}
294		300
295	void	301	void
296	ls2_sdcache_wbinv_all(void)	302	ls2_sdcache_wbinv_all(void)
297	{	303	{
298	ls2_sdcache_wbinv_range_index(0, mips_sdcache_way_size);	304	struct mips_cache_info * const mci = &mips_cache_info;
		305	ls2_sdcache_wbinv_range_index(0, mci->mci_sdcache_way_size);
299	}	306	}

 @@ -1,48 +1,47 @@
-#	$NetBSD: files.gdium,v 1.1 2009/08/06 00:50:25 matt Exp $
+#	$NetBSD: files.gdium,v 1.2 2011/06/08 17:47:48 bouyer Exp $
 file	arch/evbmips/gdium/gdium_bus_io.c
 file	arch/evbmips/gdium/gdium_bus_mem.c
 file	arch/evbmips/gdium/gdium_dma.c
 file	arch/evbmips/gdium/gdium_genfb.c	wsdisplay
 file	arch/evbmips/gdium/gdium_intr.c
 file	arch/evbmips/gdium/autoconf.c
 file	arch/evbmips/gdium/machdep.c
 file	arch/mips/mips/bus_dma.c
 file	arch/evbmips/evbmips/disksubr.c
 file	arch/evbmips/evbmips/interrupt.c
 file	arch/mips/mips/mips3_clock.c
 file	arch/mips/mips/mips3_clockintr.c
 file	arch/mips/mips/softintr.c
 # The autoconfiguration root.
 device	mainbus { [addr = -1] }
 attach	mainbus at root
 file	arch/evbmips/gdium/mainbus.c		mainbus
 device	cpu
 attach	cpu at mainbus
 file	arch/evbmips/evbmips/cpu.c		cpu
 # Machine-independent I2O drivers.
 include "dev/i2o/files.i2o"
 # Machine-independent SCSI drivers
 include "dev/scsipi/files.scsipi"
 # Machine-independent USB device support
 include "dev/usb/files.usb"
 include "dev/ata/files.ata"			# to make umass happy
 # Memory Disk
 file	dev/md_root.c				memory_disk_hooks
+#
 # PCI bus support.
+#
 include "dev/pci/files.pci"
 include "arch/mips/conf/files.bonito"
 file	arch/evbmips/gdium/bonito_mainbus.c	bonito_mainbus