Thu Jun 9 19:10:38 2011 UTC ()
Correct definitions of USB_SNOOP registers.  Add USB_CONTROL register.


(matt)
diff -r1.7 -r1.8 src/sys/arch/powerpc/include/booke/e500reg.h

cvs diff -r1.7 -r1.8 src/sys/arch/powerpc/include/booke/e500reg.h (expand / switch to unified diff)

--- src/sys/arch/powerpc/include/booke/e500reg.h 2011/05/28 05:23:08 1.7
+++ src/sys/arch/powerpc/include/booke/e500reg.h 2011/06/09 19:10:37 1.8
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: e500reg.h,v 1.7 2011/05/28 05:23:08 matt Exp $ */ 1/* $NetBSD: e500reg.h,v 1.8 2011/06/09 19:10:37 matt Exp $ */
2/*- 2/*-
3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc. 3 * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
4 * All rights reserved. 4 * All rights reserved.
5 * 5 *
6 * This code is derived from software contributed to The NetBSD Foundation 6 * This code is derived from software contributed to The NetBSD Foundation
7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects 7 * by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
8 * Agency and which was developed by Matt Thomas of 3am Software Foundry. 8 * Agency and which was developed by Matt Thomas of 3am Software Foundry.
9 * 9 *
10 * This material is based upon work supported by the Defense Advanced Research 10 * This material is based upon work supported by the Defense Advanced Research
11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under 11 * Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
12 * Contract No. N66001-09-C-2073. 12 * Contract No. N66001-09-C-2073.
13 * Approved for Public Release, Distribution Unlimited 13 * Approved for Public Release, Distribution Unlimited
14 * 14 *
@@ -267,31 +267,33 @@ @@ -267,31 +267,33 @@
267#define DUART2_BASE 0x4600 267#define DUART2_BASE 0x4600
268#define DUART_SIZE 0x0100 268#define DUART_SIZE 0x0100
269 269
270#define SPI_BASE 0x7000 /* MPC8536 */ 270#define SPI_BASE 0x7000 /* MPC8536 */
271#define SPI_SIZE 0x1000 271#define SPI_SIZE 0x1000
272 272
273#define SATA1_BASE 0x18000 /* MPC8536 */ 273#define SATA1_BASE 0x18000 /* MPC8536 */
274#define SATA2_BASE 0x19000 /* MPC8536 */ 274#define SATA2_BASE 0x19000 /* MPC8536 */
275#define SATA_SIZE 0x01000 275#define SATA_SIZE 0x01000
276 276
277#define USB1_BASE 0x22100 /* MPC8536 */ 277#define USB1_BASE 0x22100 /* MPC8536 */
278#define USB2_BASE 0x23100 /* MPC8536 */ 278#define USB2_BASE 0x23100 /* MPC8536 */
279#define USB3_BASE 0x2b100 /* MPC8536 */ 279#define USB3_BASE 0x2b100 /* MPC8536 */
 280#define USB_SNOOP1 0x0300 /* DMA Snooping Register 1 */
 281#define USB_SNOOP2 0x0304 /* DMA Snooping Register 2 */
 282#define USB_CONTROL 0x0400 /* USB General Purpose Register */
 283#define USB_EN __PPCBIT(29)
 284#define USB_ULPI_INT_EN __PPCBIT(31)
280#define USB_SIZE 0x00f00 285#define USB_SIZE 0x00f00
281 286
282#define USB_SNOOP1 0x400 
283#define USB_SNOOP2 0x404 
284 
285#define SNOOP_2GB 0x1e 287#define SNOOP_2GB 0x1e
286 288
287#define ETSEC1_BASE 0x24000 289#define ETSEC1_BASE 0x24000
288#define ETSEC2_BASE 0x25000 290#define ETSEC2_BASE 0x25000
289#define ETSEC3_BASE 0x26000 291#define ETSEC3_BASE 0x26000
290#define ETSEC4_BASE 0x27000 292#define ETSEC4_BASE 0x27000
291#define ETSEC_SIZE 0x01000 293#define ETSEC_SIZE 0x01000
292 294
293#define ESDHC_BASE 0x2e000 295#define ESDHC_BASE 0x2e000
294#define ESDHC_SIZE 0x01000 296#define ESDHC_SIZE 0x01000
295 297
296#define GLOBAL_BASE 0xe0000 298#define GLOBAL_BASE 0xe0000
297#define GLOBAL_SIZE 0x01000 299#define GLOBAL_SIZE 0x01000