 @@ -1,1410 +1,1408 @@
-/*	$NetBSD: i82365.c,v 1.113 2010/04/19 18:24:26 dyoung Exp $	*/
+/*	$NetBSD: i82365.c,v 1.114 2011/07/26 22:21:02 dyoung Exp $	*/
 /*
  * Copyright (c) 2004 Charles M. Hannum.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *      This product includes software developed by Charles M. Hannum.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
  */
 /*
  * Copyright (c) 2000 Christian E. Hopps.  All rights reserved.
  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Marc Horowitz.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.113 2010/04/19 18:24:26 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.114 2011/07/26 22:21:02 dyoung Exp $");
 #define	PCICDEBUG
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/extent.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/kthread.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/pcmcia/pcmciareg.h>
 #include <dev/pcmcia/pcmciavar.h>
 #include <dev/ic/i82365reg.h>
 #include <dev/ic/i82365var.h>
 #include "locators.h"
 #ifdef PCICDEBUG
 int	pcic_debug = 0;
 #define	DPRINTF(arg) if (pcic_debug) printf arg;
 #else
 #define	DPRINTF(arg)
 #endif
 /*
  * Individual drivers will allocate their own memory and io regions. Memory
  * regions must be a multiple of 4k, aligned on a 4k boundary.
  */
 #define	PCIC_MEM_ALIGN	PCIC_MEM_PAGESIZE
 void	pcic_attach_socket(struct pcic_handle *);
 void	pcic_attach_socket_finish(struct pcic_handle *);
 int	pcic_print (void *arg, const char *pnp);
 int	pcic_intr_socket(struct pcic_handle *);
 void	pcic_poll_intr(void *);
 void	pcic_attach_card(struct pcic_handle *);
 void	pcic_detach_card(struct pcic_handle *, int);
 void	pcic_deactivate_card(struct pcic_handle *);
 void	pcic_chip_do_mem_map(struct pcic_handle *, int);
 void	pcic_chip_do_io_map(struct pcic_handle *, int);
 void	pcic_event_thread(void *);
 void	pcic_queue_event(struct pcic_handle *, int);
 void	pcic_power(int, void *);
 static int	pcic_wait_ready(struct pcic_handle *);
 static void	pcic_delay(struct pcic_handle *, int, const char *);
 static uint8_t st_pcic_read(struct pcic_handle *, int);
 static void st_pcic_write(struct pcic_handle *, int, uint8_t);
 int
 pcic_ident_ok(int ident)
+{
 	/* this is very empirical and heuristic */
 	if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO))
 		return 0;
 	if ((ident & PCIC_IDENT_REV_MASK) == 0)
 		return 0;
 	if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) {
 #ifdef DIAGNOSTIC
 		printf("pcic: does not support memory and I/O cards, "
 		    "ignored (ident=%0x)\n", ident);
 #endif
 		return 0;
+	}
 	return 1;
+}
 int
 pcic_vendor(struct pcic_handle *h)
+{
 	int reg;
 	int vendor;
 	reg = pcic_read(h, PCIC_IDENT);
 	if ((reg & PCIC_IDENT_REV_MASK) == 0)
 		return PCIC_VENDOR_NONE;
 	switch (reg) {
 	case 0x00:
 	case 0xff:
 		return PCIC_VENDOR_NONE;
 	case PCIC_IDENT_ID_INTEL0:
 		vendor = PCIC_VENDOR_I82365SLR0;
 		break;
 	case PCIC_IDENT_ID_INTEL1:
 		vendor = PCIC_VENDOR_I82365SLR1;
 		break;
 	case PCIC_IDENT_ID_INTEL2:
 		vendor = PCIC_VENDOR_I82365SL_DF;
 		break;
 	case PCIC_IDENT_ID_IBM1:
 	case PCIC_IDENT_ID_IBM2:
 		vendor = PCIC_VENDOR_IBM;
 		break;
 	case PCIC_IDENT_ID_IBM3:
 		vendor = PCIC_VENDOR_IBM_KING;
 		break;
 	default:
 		vendor = PCIC_VENDOR_UNKNOWN;
 		break;
+	}
 	if (vendor == PCIC_VENDOR_I82365SLR0 ||
 	    vendor == PCIC_VENDOR_I82365SLR1) {
 		/*
 		 * Check for Cirrus PD67xx.
 		 * the chip_id of the cirrus toggles between 11 and 00 after a
 		 * write.  weird.
 		 */
 		pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0);
 		reg = pcic_read(h, -1);
 		if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) ==
 		    PCIC_CIRRUS_CHIP_INFO_CHIP_ID) {
 			reg = pcic_read(h, -1);
 			if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0)
 				return PCIC_VENDOR_CIRRUS_PD67XX;
+		}
 		/*
 		 * check for Ricoh RF5C[23]96
 		 */
 		reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID);
 		switch (reg) {
 		case PCIC_RICOH_CHIP_ID_5C296:
 			return PCIC_VENDOR_RICOH_5C296;
 		case PCIC_RICOH_CHIP_ID_5C396:
 			return PCIC_VENDOR_RICOH_5C396;
+		}
+	}
 	return vendor;
+}
 const char *
 pcic_vendor_to_string(int vendor)
+{
 	switch (vendor) {
 	case PCIC_VENDOR_I82365SLR0:
 		return "Intel 82365SL Revision 0";
 	case PCIC_VENDOR_I82365SLR1:
 		return "Intel 82365SL Revision 1";
 	case PCIC_VENDOR_CIRRUS_PD67XX:
 		return "Cirrus PD6710/2X";
 	case PCIC_VENDOR_I82365SL_DF:
 		return "Intel 82365SL-DF";
 	case PCIC_VENDOR_RICOH_5C296:
 		return "Ricoh RF5C296";
 	case PCIC_VENDOR_RICOH_5C396:
 		return "Ricoh RF5C396";
 	case PCIC_VENDOR_IBM:
 		return "IBM PCIC";
 	case PCIC_VENDOR_IBM_KING:
 		return "IBM KING";
+	}
 	return "Unknown controller";
+}
 void
 pcic_attach(struct pcic_softc *sc)
+{
 	int i, reg, chip, socket;
 	struct pcic_handle *h;
 	device_t self;
 	DPRINTF(("pcic ident regs:"));
 	self = &sc->dev;
 	mutex_init(&sc->sc_pcic_lock, MUTEX_DEFAULT, IPL_NONE);
 	/* find and configure for the available sockets */
 	for (i = 0; i < __arraycount(sc->handle); i++) {
 		h = &sc->handle[i];
 		chip = i / 2;
 		socket = i % 2;
 		h->ph_parent = self;
 		h->chip = chip;
 		h->socket = socket;
 		h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET;
 		h->laststate = PCIC_LASTSTATE_EMPTY;
 		/* initialize pcic_read and pcic_write functions */
 		h->ph_read = st_pcic_read;
 		h->ph_write = st_pcic_write;
 		h->ph_bus_t = sc->iot;
 		h->ph_bus_h = sc->ioh;
 		h->flags = 0;
 		/* need to read vendor -- for cirrus to report no xtra chip */
 		if (socket == 0) {
 			h->vendor = pcic_vendor(h);
 			if (i < __arraycount(sc->handle) - 1)
 				(h + 1)->vendor = h->vendor;
+		}
 		switch (h->vendor) {
 		case PCIC_VENDOR_NONE:
 			/* no chip */
 			continue;
 		case PCIC_VENDOR_CIRRUS_PD67XX:
 			reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO);
 			if (socket == 0 ||
 			    (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS))
 				h->flags = PCIC_FLAG_SOCKETP;
 			break;
 		default:
 			/*
 			 * During the socket probe, read the ident register
 			 * twice.  I don't understand why, but sometimes the
 			 * clone chips in hpcmips boxes read all-0s the first
 			 * time. -- mycroft
 			 */
 			reg = pcic_read(h, PCIC_IDENT);
 			DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));
 			reg = pcic_read(h, PCIC_IDENT);
 			DPRINTF(("socket %d ident reg 0x%02x\n", i, reg));
 			if (pcic_ident_ok(reg))
 				h->flags = PCIC_FLAG_SOCKETP;
 			break;
+		}
+	}
 	for (i = 0; i < __arraycount(sc->handle); i++) {
 		h = &sc->handle[i];
 		if (h->flags & PCIC_FLAG_SOCKETP) {
 			SIMPLEQ_INIT(&h->events);
 			/* disable interrupts and leave socket in reset */
 			pcic_write(h, PCIC_INTR, 0);
 			/* zero out the address windows */
 			pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
 			/* power down the socket */
 			pcic_write(h, PCIC_PWRCTL, 0);
 			pcic_write(h, PCIC_CSC_INTR, 0);
 			(void) pcic_read(h, PCIC_CSC);
+		}
+	}
 	/* print detected info */
 	for (i = 0; i < __arraycount(sc->handle) - 1; i += 2) {
 		h = &sc->handle[i];
 		chip = i / 2;
 		if (h->vendor == PCIC_VENDOR_NONE)
 			continue;
 		aprint_normal_dev(self, "controller %d (%s) has ",
 		    chip, pcic_vendor_to_string(sc->handle[i].vendor));
 		if ((h->flags & PCIC_FLAG_SOCKETP) &&
 		    ((h + 1)->flags & PCIC_FLAG_SOCKETP))
 			aprint_normal("sockets A and B\n");
 		else if (h->flags & PCIC_FLAG_SOCKETP)
 			aprint_normal("socket A only\n");
 		else if ((h + 1)->flags & PCIC_FLAG_SOCKETP)
 			aprint_normal("socket B only\n");
 		else
 			aprint_normal("no sockets\n");
+	}
+}
 /*
  * attach the sockets before we know what interrupts we have
  */
 void
 pcic_attach_sockets(struct pcic_softc *sc)
+{
 	int i;
 	for (i = 0; i < __arraycount(sc->handle); i++)
 		if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 			pcic_attach_socket(&sc->handle[i]);
+}
 void
 pcic_power(int why, void *arg)
+{
 	struct pcic_handle *h = arg;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	int reg;
 	DPRINTF(("%s: power: why %d\n", device_xname(h->ph_parent), why));
 	if (h->flags & PCIC_FLAG_SOCKETP) {
 		if ((why == PWR_RESUME) &&
 		    (pcic_read(h, PCIC_CSC_INTR) == 0)) {
 #ifdef PCICDEBUG
 			char bitbuf[64];
 #endif
 			reg = PCIC_CSC_INTR_CD_ENABLE;
 			if (sc->irq != -1)
 			    reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;
 			pcic_write(h, PCIC_CSC_INTR, reg);
 #ifdef PCICDEBUG
 			snprintb(bitbuf, sizeof(bitbuf), PCIC_CSC_INTR_FORMAT,
 			    pcic_read(h, PCIC_CSC_INTR));
 #endif
 			DPRINTF(("%s: CSC_INTR was zero; reset to %s\n",
 			    device_xname(&sc->dev), bitbuf));
+		}
 		/*
 		 * check for card insertion or removal during suspend period.
 		 * XXX: the code can't cope with card swap (remove then insert).
 		 * how can we detect such situation?
 		 */
 		if (why == PWR_RESUME)
 			(void)pcic_intr_socket(h);
+	}
+}
 /*
  * attach a socket -- we don't know about irqs yet
  */
 void
 pcic_attach_socket(struct pcic_handle *h)
+{
 	struct pcmciabus_attach_args paa;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	int locs[PCMCIABUSCF_NLOCS];
 	/* initialize the rest of the handle */
 	h->shutdown = 0;
 	h->memalloc = 0;
 	h->ioalloc = 0;
 	h->ih_irq = 0;
 	/* now, config one pcmcia device per socket */
 	paa.paa_busname = "pcmcia";
 	paa.pct = (pcmcia_chipset_tag_t) sc->pct;
 	paa.pch = (pcmcia_chipset_handle_t) h;
 	paa.iobase = sc->iobase;
 	paa.iosize = sc->iosize;
 	locs[PCMCIABUSCF_CONTROLLER] = h->chip;
 	locs[PCMCIABUSCF_SOCKET] = h->socket;
 	h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", locs, &paa,
 					pcic_print, config_stdsubmatch);
 	if (h->pcmcia == NULL) {
 		h->flags &= ~PCIC_FLAG_SOCKETP;
 		return;
+	}
+}
 /*
  * now finish attaching the sockets, we are ready to allocate
  * interrupts
  */
 void
 pcic_attach_sockets_finish(struct pcic_softc *sc)
+{
 	int i;
 	for (i = 0; i < __arraycount(sc->handle); i++)
 		if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 			pcic_attach_socket_finish(&sc->handle[i]);
+}
 /*
  * finishing attaching the socket.  Interrupts may now be on
  * if so expects the pcic interrupt to be blocked
  */
 void
 pcic_attach_socket_finish(struct pcic_handle *h)
+{
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	int reg;
 	char cs[4];
 	DPRINTF(("%s: attach finish socket %ld\n", device_xname(h->ph_parent),
 	    (long) (h - &sc->handle[0])));
 	/*
 	 * Set up a powerhook to ensure it continues to interrupt on
 	 * card detect even after suspend.
 	 * (this works around a bug seen in suspend-to-disk on the
 	 * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved).
 	 */
 	powerhook_establish(device_xname(h->ph_parent), pcic_power, h);
 	/* enable interrupts on card detect, poll for them if no irq avail */
 	reg = PCIC_CSC_INTR_CD_ENABLE;
 	if (sc->irq == -1) {
 		if (sc->poll_established == 0) {
 			callout_init(&sc->poll_ch, 0);
 			callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc);
 			sc->poll_established = 1;
+		}
 	} else
 		reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT;
 	pcic_write(h, PCIC_CSC_INTR, reg);
 	/* steer above mgmt interrupt to configured place */
 	if (sc->irq == 0)
 		pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE);
 	/* clear possible card detect interrupt */
 	(void) pcic_read(h, PCIC_CSC);
 	DPRINTF(("%s: attach finish vendor 0x%02x\n",
 	    device_xname(h->ph_parent), h->vendor));
 	/* unsleep the cirrus controller */
 	if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) {
 		reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2);
 		if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) {
 			DPRINTF(("%s: socket %02x was suspended\n",
 			    device_xname(h->ph_parent), h->sock));
 			reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND;
 			pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg);
+		}
+	}
 	/* if there's a card there, then attach it. */
 	reg = pcic_read(h, PCIC_IF_STATUS);
 	if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
 	    PCIC_IF_STATUS_CARDDETECT_PRESENT) {
 		pcic_queue_event(h, PCIC_EVENT_INSERTION);
 		h->laststate = PCIC_LASTSTATE_PRESENT;
 	} else {
 		h->laststate = PCIC_LASTSTATE_EMPTY;
+	}
 	/*
 	 * queue creation of a kernel thread to handle insert/removal events.
 	 */
 #ifdef DIAGNOSTIC
 	if (h->event_thread != NULL)
 		panic("pcic_attach_socket: event thread");
 #endif
 	config_pending_incr();
 	snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket);
 	if (kthread_create(PRI_NONE, 0, NULL, pcic_event_thread, h,
 	    &h->event_thread, "%s,%s", device_xname(h->ph_parent), cs)) {
 		aprint_error_dev(h->ph_parent,
 		    "unable to create event thread for sock 0x%02x\n", h->sock);
 		panic("pcic_attach_socket");
+	}
+}
 void
 pcic_event_thread(void *arg)
+{
 	struct pcic_handle *h = arg;
 	struct pcic_event *pe;
 	int s, first = 1;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	while (h->shutdown == 0) {
 		/*
 		 * Serialize event processing on the PCIC.  We may
 		 * sleep while we hold this lock.
 		 */
 		mutex_enter(&sc->sc_pcic_lock);
 		s = splhigh();
 		if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
 			splx(s);
 			if (first) {
 				first = 0;
 				config_pending_decr();
+			}
 			/*
 			 * No events to process; release the PCIC lock.
 			 */
 			(void) mutex_exit(&sc->sc_pcic_lock);
 			(void) tsleep(&h->events, PWAIT, "pcicev", 0);
 			continue;
 		} else {
 			splx(s);
 			/* sleep .25s to be enqueued chatterling interrupts */
 			(void) tsleep((void *)pcic_event_thread, PWAIT,
 			    "pcicss", hz / 4);
+		}
 		s = splhigh();
 		SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 		splx(s);
 		switch (pe->pe_type) {
 		case PCIC_EVENT_INSERTION:
 			s = splhigh();
 			for (;;) {
 				struct pcic_event *pe1, *pe2;
 				if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
 					break;
 				if (pe1->pe_type != PCIC_EVENT_REMOVAL)
 					break;
 				if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
 					break;
 				if (pe2->pe_type == PCIC_EVENT_INSERTION) {
 					SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 					free(pe1, M_TEMP);
 					SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 					free(pe2, M_TEMP);
+				}
+			}
 			splx(s);
 			DPRINTF(("%s: insertion event\n",
 			    device_xname(h->ph_parent)));
 			pcic_attach_card(h);
 			break;
 		case PCIC_EVENT_REMOVAL:
 			s = splhigh();
 			for (;;) {
 				struct pcic_event *pe1, *pe2;
 				if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL)
 					break;
 				if (pe1->pe_type != PCIC_EVENT_INSERTION)
 					break;
 				if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL)
 					break;
 				if (pe2->pe_type == PCIC_EVENT_REMOVAL) {
 					SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 					free(pe1, M_TEMP);
 					SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 					free(pe2, M_TEMP);
+				}
+			}
 			splx(s);
 			DPRINTF(("%s: removal event\n",
 			    device_xname(h->ph_parent)));
 			pcic_detach_card(h, DETACH_FORCE);
 			break;
 		default:
 			panic("pcic_event_thread: unknown event %d",
 			    pe->pe_type);
+		}
 		free(pe, M_TEMP);
 		mutex_exit(&sc->sc_pcic_lock);
+	}
 	h->event_thread = NULL;
 	/* In case parent is waiting for us to exit. */
 	wakeup(sc);
 	kthread_exit(0);
+}
 int
 pcic_print(void *arg, const char *pnp)
+{
 	struct pcmciabus_attach_args *paa = arg;
 	struct pcic_handle *h = (struct pcic_handle *) paa->pch;
 	/* Only "pcmcia"s can attach to "pcic"s... easy. */
 	if (pnp)
 		aprint_normal("pcmcia at %s", pnp);
 	aprint_normal(" controller %d socket %d", h->chip, h->socket);
 	return UNCONF;
+}
 void
 pcic_poll_intr(void *arg)
+{
 	struct pcic_softc *sc;
 	int i, s;
 	s = spltty();
 	sc = arg;
 	for (i = 0; i < __arraycount(sc->handle); i++)
 		if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 			(void)pcic_intr_socket(&sc->handle[i]);
 	callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc);
 	splx(s);
+}
 int
 pcic_intr(void *arg)
+{
 	struct pcic_softc *sc = arg;
 	int i, ret = 0;
 	DPRINTF(("%s: intr\n", device_xname(&sc->dev)));
 	for (i = 0; i < __arraycount(sc->handle); i++)
 		if (sc->handle[i].flags & PCIC_FLAG_SOCKETP)
 			ret += pcic_intr_socket(&sc->handle[i]);
 	return ret ? 1 : 0;
+}
 int
 pcic_intr_socket(struct pcic_handle *h)
+{
 	int cscreg;
 	cscreg = pcic_read(h, PCIC_CSC);
 	cscreg &= (PCIC_CSC_GPI |
 		   PCIC_CSC_CD |
 		   PCIC_CSC_READY |
 		   PCIC_CSC_BATTWARN |
 		   PCIC_CSC_BATTDEAD);
 	if (cscreg & PCIC_CSC_GPI) {
 		DPRINTF(("%s: %02x GPI\n",
 		    device_xname(h->ph_parent), h->sock));
+	}
 	if (cscreg & PCIC_CSC_CD) {
 		int statreg;
 		statreg = pcic_read(h, PCIC_IF_STATUS);
 		DPRINTF(("%s: %02x CD %x\n", device_xname(h->ph_parent),
 		    h->sock, statreg));
 		if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) ==
 		    PCIC_IF_STATUS_CARDDETECT_PRESENT) {
 			if (h->laststate != PCIC_LASTSTATE_PRESENT) {
 				DPRINTF(("%s: enqueing INSERTION event\n",
 				    device_xname(h->ph_parent)));
 				pcic_queue_event(h, PCIC_EVENT_INSERTION);
+			}
 			h->laststate = PCIC_LASTSTATE_PRESENT;
 		} else {
 			if (h->laststate == PCIC_LASTSTATE_PRESENT) {
 				/* Deactivate the card now. */
 				DPRINTF(("%s: deactivating card\n",
 				    device_xname(h->ph_parent)));
 				pcic_deactivate_card(h);
 				DPRINTF(("%s: enqueing REMOVAL event\n",
 				    device_xname(h->ph_parent)));
 				pcic_queue_event(h, PCIC_EVENT_REMOVAL);
+			}
 			h->laststate = PCIC_LASTSTATE_EMPTY;
+		}
+	}
 	if (cscreg & PCIC_CSC_READY) {
 		DPRINTF(("%s: %02x READY\n", device_xname(h->ph_parent),
 		     h->sock));
 		/* shouldn't happen */
+	}
 	if (cscreg & PCIC_CSC_BATTWARN) {
 		DPRINTF(("%s: %02x BATTWARN\n", device_xname(h->ph_parent),
 		    h->sock));
+	}
 	if (cscreg & PCIC_CSC_BATTDEAD) {
 		DPRINTF(("%s: %02x BATTDEAD\n", device_xname(h->ph_parent),
 		    h->sock));
+	}
 	return cscreg ? 1 : 0;
+}
 void
 pcic_queue_event(struct pcic_handle *h, int event)
+{
 	struct pcic_event *pe;
 	int s;
 	pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
 	if (pe == NULL)
 		panic("pcic_queue_event: can't allocate event");
 	pe->pe_type = event;
 	s = splhigh();
 	SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
 	splx(s);
 	wakeup(&h->events);
+}
 void
 pcic_attach_card(struct pcic_handle *h)
+{
 	if ((h->flags & PCIC_FLAG_CARDP) == 0) {
 		/* call the MI attach function */
 		pcmcia_card_attach(h->pcmcia);
 		h->flags |= PCIC_FLAG_CARDP;
 	} else {
 		DPRINTF(("pcic_attach_card: already attached"));
+	}
+}
 void
 pcic_detach_card(struct pcic_handle *h, int flags)
 	/* flags:		 DETACH_* */
+{
 	if (h->flags & PCIC_FLAG_CARDP) {
 		h->flags &= ~PCIC_FLAG_CARDP;
 		/* call the MI detach function */
 		pcmcia_card_detach(h->pcmcia, flags);
 	} else {
 		DPRINTF(("pcic_detach_card: already detached"));
+	}
+}
 void
 pcic_deactivate_card(struct pcic_handle *h)
+{
 	int intr;
 	/* call the MI deactivate function */
 	pcmcia_card_deactivate(h->pcmcia);
 	/* reset the socket */
 	intr = pcic_read(h, PCIC_INTR);
 	intr &= PCIC_INTR_ENABLE;
 	pcic_write(h, PCIC_INTR, intr);
 	/* power down the socket */
 	pcic_write(h, PCIC_PWRCTL, 0);
+}
 int
 pcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
     struct pcmcia_mem_handle *pcmhp)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	bus_space_handle_t memh;
 	bus_addr_t addr;
 	bus_size_t sizepg;
 	int i, mask, mhandle;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	/* out of sc->memh, allocate as many pages as necessary */
 	/* convert size to PCIC pages */
 	sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN;
 	if (sizepg > PCIC_MAX_MEM_PAGES)
 		return 1;
 	mask = (1 << sizepg) - 1;
 	addr = 0;		/* XXX gcc -Wuninitialized */
 	mhandle = 0;		/* XXX gcc -Wuninitialized */
 	for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) {
 		if ((sc->subregionmask & (mask << i)) == (mask << i)) {
 			if (bus_space_subregion(sc->memt, sc->memh,
 			    i * PCIC_MEM_PAGESIZE,
 			    sizepg * PCIC_MEM_PAGESIZE, &memh))
 				return 1;
 			mhandle = mask << i;
 			addr = sc->membase + (i * PCIC_MEM_PAGESIZE);
 			sc->subregionmask &= ~(mhandle);
 			pcmhp->memt = sc->memt;
 			pcmhp->memh = memh;
 			pcmhp->addr = addr;
 			pcmhp->size = size;
 			pcmhp->mhandle = mhandle;
 			pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
 			return 0;
+		}
+	}
 	return 1;
+}
 void
 pcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	sc->subregionmask |= pcmhp->mhandle;
+}
 static const struct mem_map_index_st {
 	int	sysmem_start_lsb;
 	int	sysmem_start_msb;
 	int	sysmem_stop_lsb;
 	int	sysmem_stop_msb;
 	int	cardmem_lsb;
 	int	cardmem_msb;
 	int	memenable;
 } mem_map_index[] = {
+	{
 		PCIC_SYSMEM_ADDR0_START_LSB,
 		PCIC_SYSMEM_ADDR0_START_MSB,
 		PCIC_SYSMEM_ADDR0_STOP_LSB,
 		PCIC_SYSMEM_ADDR0_STOP_MSB,
 		PCIC_CARDMEM_ADDR0_LSB,
 		PCIC_CARDMEM_ADDR0_MSB,
 		PCIC_ADDRWIN_ENABLE_MEM0,
 	},
+	{
 		PCIC_SYSMEM_ADDR1_START_LSB,
 		PCIC_SYSMEM_ADDR1_START_MSB,
 		PCIC_SYSMEM_ADDR1_STOP_LSB,
 		PCIC_SYSMEM_ADDR1_STOP_MSB,
 		PCIC_CARDMEM_ADDR1_LSB,
 		PCIC_CARDMEM_ADDR1_MSB,
 		PCIC_ADDRWIN_ENABLE_MEM1,
 	},
+	{
 		PCIC_SYSMEM_ADDR2_START_LSB,
 		PCIC_SYSMEM_ADDR2_START_MSB,
 		PCIC_SYSMEM_ADDR2_STOP_LSB,
 		PCIC_SYSMEM_ADDR2_STOP_MSB,
 		PCIC_CARDMEM_ADDR2_LSB,
 		PCIC_CARDMEM_ADDR2_MSB,
 		PCIC_ADDRWIN_ENABLE_MEM2,
 	},
+	{
 		PCIC_SYSMEM_ADDR3_START_LSB,
 		PCIC_SYSMEM_ADDR3_START_MSB,
 		PCIC_SYSMEM_ADDR3_STOP_LSB,
 		PCIC_SYSMEM_ADDR3_STOP_MSB,
 		PCIC_CARDMEM_ADDR3_LSB,
 		PCIC_CARDMEM_ADDR3_MSB,
 		PCIC_ADDRWIN_ENABLE_MEM3,
 	},
+	{
 		PCIC_SYSMEM_ADDR4_START_LSB,
 		PCIC_SYSMEM_ADDR4_START_MSB,
 		PCIC_SYSMEM_ADDR4_STOP_LSB,
 		PCIC_SYSMEM_ADDR4_STOP_MSB,
 		PCIC_CARDMEM_ADDR4_LSB,
 		PCIC_CARDMEM_ADDR4_MSB,
 		PCIC_ADDRWIN_ENABLE_MEM4,
 	},
 };
 void
 pcic_chip_do_mem_map(struct pcic_handle *h, int win)
+{
 	int reg;
 	int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
 	int mem8 =
 	    (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8
 	    || (kind == PCMCIA_MEM_ATTR);
 	DPRINTF(("mem8 %d\n", mem8));
 	/* mem8 = 1; */
 	pcic_write(h, mem_map_index[win].sysmem_start_lsb,
 	    (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
 	pcic_write(h, mem_map_index[win].sysmem_start_msb,
 	    ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
 	    PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) |
 	    (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT));
 	pcic_write(h, mem_map_index[win].sysmem_stop_lsb,
 	    ((h->mem[win].addr + h->mem[win].size) >>
 	    PCIC_SYSMEM_ADDRX_SHIFT) & 0xff);
 	pcic_write(h, mem_map_index[win].sysmem_stop_msb,
 	    (((h->mem[win].addr + h->mem[win].size) >>
 	    (PCIC_SYSMEM_ADDRX_SHIFT + 8)) &
 	    PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) |
 	    PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2);
 	pcic_write(h, mem_map_index[win].cardmem_lsb,
 	    (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff);
 	pcic_write(h, mem_map_index[win].cardmem_msb,
 	    ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) &
 	    PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) |
 	    ((kind == PCMCIA_MEM_ATTR) ?
 	    PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0));
 	reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 	reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16);
 	pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 	delay(100);
 #ifdef PCICDEBUG
+	{
 		int r1, r2, r3, r4, r5, r6;
 		r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb);
 		r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb);
 		r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb);
 		r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb);
 		r5 = pcic_read(h, mem_map_index[win].cardmem_msb);
 		r6 = pcic_read(h, mem_map_index[win].cardmem_lsb);
 		DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x "
 		    "%02x%02x\n", win, r1, r2, r3, r4, r5, r6));
+	}
 #endif
+}
 int
 pcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr,
     bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp,
     int *windowp)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	bus_addr_t busaddr;
 	long card_offset;
 	int i, win;
 	win = -1;
 	for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0]));
 	    i++) {
 		if ((h->memalloc & (1 << i)) == 0) {
 			win = i;
 			h->memalloc |= (1 << i);
 			break;
+		}
+	}
 	if (win == -1)
 		return 1;
 	*windowp = win;
 	/* XXX this is pretty gross */
+{
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	if (!bus_space_is_equal(sc->memt, pcmhp->memt))
 		panic("pcic_chip_mem_map memt is bogus");
+}
 	busaddr = pcmhp->addr;
 	/*
 	 * compute the address offset to the pcmcia address space for the
 	 * pcic.  this is intentionally signed.  The masks and shifts below
 	 * will cause TRT to happen in the pcic registers.  Deal with making
 	 * sure the address is aligned, and return the alignment offset.
 	 */
 	*offsetp = card_addr % PCIC_MEM_ALIGN;
 	card_addr -= *offsetp;
 	DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
 	    "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
 	    (u_long) card_addr));
 	/*
 	 * include the offset in the size, and decrement size by one, since
 	 * the hw wants start/stop
 	 */
 	size += *offsetp - 1;
 	card_offset = (((long) card_addr) - ((long) busaddr));
 	h->mem[win].addr = busaddr;
 	h->mem[win].size = size;
 	h->mem[win].offset = card_offset;
 	h->mem[win].kind = kind;
 	pcic_chip_do_mem_map(h, win);
 	return 0;
+}
 void
 pcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	int reg;
 	if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0])))
 		panic("pcic_chip_mem_unmap: window out of range");
 	reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 	reg &= ~mem_map_index[window].memenable;
 	pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 	h->memalloc &= ~(1 << window);
+}
 int
 pcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
     bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	bus_space_tag_t iot;
 	bus_space_handle_t ioh;
 	bus_addr_t ioaddr;
 	int flags = 0;
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	/*
 	 * Allocate some arbitrary I/O space.
 	 */
 	iot = sc->iot;
 	if (start) {
 		ioaddr = start;
 		if (bus_space_map(iot, start, size, 0, &ioh))
 			return 1;
 		DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n",
 		    (u_long) ioaddr, (u_long) size));
 	} else {
 		flags |= PCMCIA_IO_ALLOCATED;
 		if (bus_space_alloc(iot, sc->iobase,
 		    sc->iobase + sc->iosize, size, align, 0, 0,
 		    &ioaddr, &ioh))
 			return 1;
 		DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n",
 		    (u_long) ioaddr, (u_long) size));
+	}
 	pcihp->iot = iot;
 	pcihp->ioh = ioh;
 	pcihp->addr = ioaddr;
 	pcihp->size = size;
 	pcihp->flags = flags;
 	return 0;
+}
 void
 pcic_chip_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pcihp)
+{
 	bus_space_tag_t iot = pcihp->iot;
 	bus_space_handle_t ioh = pcihp->ioh;
 	bus_size_t size = pcihp->size;
 	if (pcihp->flags & PCMCIA_IO_ALLOCATED)
 		bus_space_free(iot, ioh, size);
 	else
 		bus_space_unmap(iot, ioh, size);
+}
 static const struct io_map_index_st {
 	int	start_lsb;
 	int	start_msb;
 	int	stop_lsb;
 	int	stop_msb;
 	int	ioenable;
 	int	ioctlmask;
 	int	ioctlbits[3];		/* indexed by PCMCIA_WIDTH_* */
 }               io_map_index[] = {
+	{
 		PCIC_IOADDR0_START_LSB,
 		PCIC_IOADDR0_START_MSB,
 		PCIC_IOADDR0_STOP_LSB,
 		PCIC_IOADDR0_STOP_MSB,
 		PCIC_ADDRWIN_ENABLE_IO0,
 		PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
 		PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK,
+		{
 			PCIC_IOCTL_IO0_IOCS16SRC_CARD,
 			PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
 			    PCIC_IOCTL_IO0_DATASIZE_8BIT,
 			PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
 			    PCIC_IOCTL_IO0_DATASIZE_16BIT,
 		},
 	},
+	{
 		PCIC_IOADDR1_START_LSB,
 		PCIC_IOADDR1_START_MSB,
 		PCIC_IOADDR1_STOP_LSB,
 		PCIC_IOADDR1_STOP_MSB,
 		PCIC_ADDRWIN_ENABLE_IO1,
 		PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
 		PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK,
+		{
 			PCIC_IOCTL_IO1_IOCS16SRC_CARD,
 			PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
 			    PCIC_IOCTL_IO1_DATASIZE_8BIT,
 			PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE |
 			    PCIC_IOCTL_IO1_DATASIZE_16BIT,
 		},
 	},
 };
 void
 pcic_chip_do_io_map(struct pcic_handle *h, int win)
+{
 	int reg;
 	DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
 	    win, (long) h->io[win].addr, (long) h->io[win].size,
 	    h->io[win].width * 8));
 	pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff);
 	pcic_write(h, io_map_index[win].start_msb,
 	    (h->io[win].addr >> 8) & 0xff);
 	pcic_write(h, io_map_index[win].stop_lsb,
 	    (h->io[win].addr + h->io[win].size - 1) & 0xff);
 	pcic_write(h, io_map_index[win].stop_msb,
 	    ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff);
 	reg = pcic_read(h, PCIC_IOCTL);
 	reg &= ~io_map_index[win].ioctlmask;
 	reg |= io_map_index[win].ioctlbits[h->io[win].width];
 	pcic_write(h, PCIC_IOCTL, reg);
 	reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 	reg |= io_map_index[win].ioenable;
 	pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
+}
 int
 pcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
     bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	bus_addr_t ioaddr = pcihp->addr + offset;
 	int i, win;
 #ifdef PCICDEBUG
 	static const char *width_names[] = { "auto", "io8", "io16" };
 #endif
 	struct pcic_softc *sc = device_private(h->ph_parent);
 	/* XXX Sanity check offset/size. */
 	win = -1;
 	for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) {
 		if ((h->ioalloc & (1 << i)) == 0) {
 			win = i;
 			h->ioalloc |= (1 << i);
 			break;
+		}
+	}
 	if (win == -1)
 		return 1;
 	*windowp = win;
 	/* XXX this is pretty gross */
 	if (!bus_space_is_equal(sc->iot, pcihp->iot))
 		panic("pcic_chip_io_map iot is bogus");
 	DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n",
 	    win, width_names[width], (u_long) ioaddr, (u_long) size));
 	/* XXX wtf is this doing here? */
 	printf("%s: port 0x%lx", device_xname(&sc->dev), (u_long) ioaddr);
 	if (size > 1)
 		printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
 	printf("\n");
 	h->io[win].addr = ioaddr;
 	h->io[win].size = size;
 	h->io[win].width = width;
 	pcic_chip_do_io_map(h, win);
 	return 0;
+}
 void
 pcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	int reg;
 	if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0])))
 		panic("pcic_chip_io_unmap: window out of range");
 	reg = pcic_read(h, PCIC_ADDRWIN_ENABLE);
 	reg &= ~io_map_index[window].ioenable;
 	pcic_write(h, PCIC_ADDRWIN_ENABLE, reg);
 	h->ioalloc &= ~(1 << window);
+}
 static int
 pcic_wait_ready(struct pcic_handle *h)
+{
 	uint8_t stat;
 	int i;
 	/* wait an initial 10ms for quick cards */
 	stat = pcic_read(h, PCIC_IF_STATUS);
 	if (stat & PCIC_IF_STATUS_READY)
 		return 0;
 	pcic_delay(h, 10, "pccwr0");
 	for (i = 0; i < 50; i++) {
 		stat = pcic_read(h, PCIC_IF_STATUS);
 		if (stat & PCIC_IF_STATUS_READY)
 			return 0;
 		if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) !=
 		    PCIC_IF_STATUS_CARDDETECT_PRESENT)
 			return ENXIO;
 		/* wait .1s (100ms) each iteration now */
 		pcic_delay(h, 100, "pccwr1");
+	}
 	printf("pcic_wait_ready: ready never happened, status=%02x\n", stat);
 	return EWOULDBLOCK;
+}
 /*
  * Perform long (msec order) delay.
  */
 static void
 pcic_delay(struct pcic_handle *h, int timo, const char *wmesg)
 	/* timo:			 in ms.  must not be zero */
+{
 #ifdef DIAGNOSTIC
 	if (timo <= 0)
 		panic("pcic_delay: called with timeout %d", timo);
 	if (!curlwp)
 		panic("pcic_delay: called in interrupt context");
 	if (!h->event_thread)
 		panic("pcic_delay: no event thread");
 #endif
 	DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n",
 	    wmesg, h->event_thread, timo));
 	if (doing_shutdown)
 		delay(timo * 1000);
 	else
 		tsleep(pcic_delay, PWAIT, wmesg,
 		    roundup(timo * hz, 1000) / 1000);
+}
 void
 pcic_chip_socket_enable(pcmcia_chipset_handle_t pch)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	int win;
 	uint8_t power, intr;
 #ifdef DIAGNOSTIC
 	int reg;
 #endif
 #ifdef DIAGNOSTIC
 	if (h->flags & PCIC_FLAG_ENABLED)
 		printf("pcic_chip_socket_enable: enabling twice\n");
 #endif
 	/* disable interrupts; assert RESET */
 	intr = pcic_read(h, PCIC_INTR);
 	intr &= PCIC_INTR_ENABLE;
 	pcic_write(h, PCIC_INTR, intr);
 	/* zero out the address windows */
 	pcic_write(h, PCIC_ADDRWIN_ENABLE, 0);
 	/* power off; assert output enable bit */
 	power = PCIC_PWRCTL_OE;
 	pcic_write(h, PCIC_PWRCTL, power);
 	/*
 	 * power hack for RICOH RF5C[23]96
 	 */
 	switch (h->vendor) {
 	case PCIC_VENDOR_RICOH_5C296:
 	case PCIC_VENDOR_RICOH_5C396:
+	    {
 		int regtmp;
 		regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2);
 #ifdef RICOH_POWER_HACK
 		regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT;
 #else
 		regtmp &=
 		    ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V);
 #endif
 		pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp);
+	    }
 		break;
 	default:
 		break;
+	}
 #ifdef VADEM_POWER_HACK
 	bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e);
 	bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37);
 	printf("prcr = %02x\n", pcic_read(h, 0x02));
 	printf("cvsr = %02x\n", pcic_read(h, 0x2f));
 	printf("DANGER WILL ROBINSON!  Changing voltage select!\n");
 	pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03);
 	printf("cvsr = %02x\n", pcic_read(h, 0x2f));
 #endif
 	/* power up the socket */
 	power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC;
 	pcic_write(h, PCIC_PWRCTL, power);
 	/*
 	 * Table 4-18 and figure 4-6 of the PC Card specifiction say:
 	 * Vcc Rising Time (Tpr) = 100ms
 	 * RESET Width (Th (Hi-z RESET)) = 1ms
 	 * RESET Width (Tw (RESET)) = 10us
+	 *
 	 * some machines require some more time to be settled
 	 * (100ms is added here).
 	 */
 	pcic_delay(h, 200 + 1, "pccen1");
 	/* negate RESET */
 	intr |= PCIC_INTR_RESET;
 	pcic_write(h, PCIC_INTR, intr);
 	/*
 	 * RESET Setup Time (Tsu (RESET)) = 20ms
 	 */
 	pcic_delay(h, 20, "pccen2");
 #ifdef DIAGNOSTIC
 	reg = pcic_read(h, PCIC_IF_STATUS);
 	if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0)
 		printf("pcic_chip_socket_enable: no power, status=%x\n", reg);
 #endif
 	/* wait for the chip to finish initializing */
 	if (pcic_wait_ready(h)) {
 		/* XXX return a failure status?? */
 		pcic_write(h, PCIC_PWRCTL, 0);
 		return;
+	}
 	/* reinstall all the memory and io mappings */
 	for (win = 0; win < PCIC_MEM_WINS; win++)
 		if (h->memalloc & (1 << win))
 			pcic_chip_do_mem_map(h, win);
 	for (win = 0; win < PCIC_IO_WINS; win++)
 		if (h->ioalloc & (1 << win))
 			pcic_chip_do_io_map(h, win);
 	h->flags |= PCIC_FLAG_ENABLED;
+}
 void
 pcic_chip_socket_disable(pcmcia_chipset_handle_t pch)
+{
 	struct pcic_handle *h = (struct pcic_handle *) pch;
 	uint8_t intr;
 	DPRINTF(("pcic_chip_socket_disable\n"));

 @@ -1,1292 +1,1290 @@
-/*	$NetBSD: tcic2.c,v 1.35 2010/04/19 18:24:26 dyoung Exp $	*/
+/*	$NetBSD: tcic2.c,v 1.36 2011/07/26 22:21:02 dyoung Exp $	*/
 /*
  * Copyright (c) 1998, 1999 Christoph Badura.  All rights reserved.
  * Copyright (c) 1997 Marc Horowitz.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed by Marc Horowitz.
  * 4. The name of the author may not be used to endorse or promote products
  *    derived from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.35 2010/04/19 18:24:26 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.36 2011/07/26 22:21:02 dyoung Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/extent.h>
 #include <sys/malloc.h>
 #include <sys/kthread.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/pcmcia/pcmciareg.h>
 #include <dev/pcmcia/pcmciavar.h>
 #include <dev/ic/tcic2reg.h>
 #include <dev/ic/tcic2var.h>
 #include "locators.h"
 #ifdef TCICDEBUG
 int	tcic_debug = 1;
 #define	DPRINTF(arg) if (tcic_debug) printf arg;
 #else
 #define	DPRINTF(arg)
 #endif
 /*
  * Individual drivers will allocate their own memory and io regions. Memory
  * regions must be a multiple of 4k, aligned on a 4k boundary.
  */
 #define	TCIC_MEM_ALIGN	TCIC_MEM_PAGESIZE
 void	tcic_attach_socket(struct tcic_handle *);
 void	tcic_init_socket(struct tcic_handle *);
 int	tcic_print(void *arg, const char *pnp);
 int	tcic_intr_socket(struct tcic_handle *);
 void	tcic_attach_card(struct tcic_handle *);
 void	tcic_detach_card(struct tcic_handle *, int);
 void	tcic_deactivate_card(struct tcic_handle *);
 void	tcic_chip_do_mem_map(struct tcic_handle *, int);
 void	tcic_chip_do_io_map(struct tcic_handle *, int);
 void	tcic_create_event_thread(void *);
 void	tcic_event_thread(void *);
 void	tcic_queue_event(struct tcic_handle *, int);
 /* Map between irq numbers and internal representation */
 #if 1
 int tcic_irqmap[] =
     { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 };
 int tcic_valid_irqs = 0x4cf8;
 #else
 int tcic_irqmap[] =	/* irqs 9 and 6 switched, some ISA cards */
     { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 };
 int tcic_valid_irqs = 0x4eb8;
 #endif
 int tcic_mem_speed = 250;	/* memory access time in nanoseconds */
 int tcic_io_speed = 165;	/* io access time in nanoseconds */
 /*
  * Check various reserved and otherwise in their value restricted bits.
  */
 int
 tcic_check_reserved_bits(bus_space_tag_t iot, bus_space_handle_t ioh)
+{
 	int val, auxreg;
 	DPRINTF(("tcic: chkrsvd 1\n"));
 	/* R_ADDR bit 30:28 have a restricted range. */
 	val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK)
 	    >> TCIC_SS_SHIFT;
 	if (val > 1)
 		return 0;
 	DPRINTF(("tcic: chkrsvd 2\n"));
 	/* R_SCTRL bits 6,2,1 are reserved. */
 	val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
 	if (val & TCIC_SCTRL_RSVD)
 		return 0;
 	DPRINTF(("tcic: chkrsvd 3\n"));
 	/* R_ICSR bit 2 must be same as bit 3. */
 	val = bus_space_read_1(iot, ioh, TCIC_R_ICSR);
 	if (((val >> 1) & 1) != ((val >> 2) & 1))
 		return 0;
 	DPRINTF(("tcic: chkrsvd 4\n"));
 	/* R_IENA bits 7,2 are reserverd. */
 	val = bus_space_read_1(iot, ioh, TCIC_R_IENA);
 	if (val & TCIC_IENA_RSVD)
 		return 0;
 	DPRINTF(("tcic: chkrsvd 5\n"));
 	/* Some aux registers have reserved bits. */
 	/* Which are we looking at? */
 	auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE)
 	    & TCIC_AR_MASK;
 	val = bus_space_read_2(iot, ioh, TCIC_R_AUX);
 	DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val));
 	switch (auxreg) {
 	case TCIC_AR_SYSCFG:
 		if (INVALID_AR_SYSCFG(val))
 			return 0;
 		break;
 	case TCIC_AR_ILOCK:
 		if (INVALID_AR_ILOCK(val))
 			return 0;
 		break;
 	case TCIC_AR_TEST:
 		if (INVALID_AR_TEST(val))
 			return 0;
 		break;
+	}
 	DPRINTF(("tcic: chkrsvd 6\n"));
 	/* XXX fails if pcmcia bios is enabled. */
 	/* Various bits set or not depending if in RESET mode. */
 	val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL);
 	if (val & TCIC_SCTRL_RESET) {
 		DPRINTF(("tcic: chkrsvd 7\n"));
 		/* Address bits must be 0 */
 		val = bus_space_read_2(iot, ioh, TCIC_R_ADDR);
 		if (val != 0)
 			return 0;
 		val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2);
 		if (val != 0)
 			return 0;
 		DPRINTF(("tcic: chkrsvd 8\n"));
 		/* EDC bits must be 0 */
 		val = bus_space_read_2(iot, ioh, TCIC_R_EDC);
 		if (val != 0)
 			return 0;
 		/* We're OK, so take it out of reset. XXX -chb */
 		bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0);
+	}
 	else {	/* not in RESET mode */
 		int omode;
 		int val1, val2;
 		DPRINTF(("tcic: chkrsvd 9\n"));
 		/* Programming timers must have expired. */
 		val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT);
 		if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
 		    != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME))
 			return 0;
 		DPRINTF(("tcic: chkrsvd 10\n"));
 		/*
 		 * EDC bits should change on read from data space
 		 * as long as either EDC or the data are nonzero.
 		 */
 		 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2)
 		     & TCIC_ADDR2_INDREG) != 0) {
 			val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
 			val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA);
 			if (val1 | val2) {
 				val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC);
 				if (val1 == val2)
 					return 0;
+			}
+		}
 		DPRINTF(("tcic: chkrsvd 11\n"));
 		/* XXX what does this check? -chb */
 		omode = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 		val1 = omode ^ TCIC_AR_MASK;
 		bus_space_write_1(iot, ioh, TCIC_R_MODE, val1);
 		val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE);
 		bus_space_write_1(iot, ioh, TCIC_R_MODE, omode);
 		if ( val1 != val2)
 			return 0;
+	}
 	/* All tests passed */
 	return 1;
+}
 /*
  * Read chip ID from AR_ILOCK in test mode.
  */
 int
 tcic_chipid(bus_space_tag_t iot, bus_space_handle_t ioh)
+{
 	unsigned id, otest;
 	otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST);
 	tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG);
 	id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK);
 	tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest);
 	id &= TCIC_ILOCKTEST_ID_MASK;
 	id >>= TCIC_ILOCKTEST_ID_SHFT;
 	/* clear up IRQs inside tcic. XXX -chb */
 	while (bus_space_read_1(iot, ioh, TCIC_R_ICSR))
 		bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM);
 	return id;
+}
 /*
  * Indicate whether the driver can handle the chip.
  */
 int
 tcic_chipid_known(int id)
+{
 	/* XXX only know how to handle DB86082 -chb */
 	switch (id) {
 	case TCIC_CHIPID_DB86082_1:
 	case TCIC_CHIPID_DB86082A:
 	case TCIC_CHIPID_DB86082B_ES:
 	case TCIC_CHIPID_DB86082B:
 	case TCIC_CHIPID_DB86084_1:
 	case TCIC_CHIPID_DB86084A:
 	case TCIC_CHIPID_DB86184_1:
 	case TCIC_CHIPID_DB86072_1_ES:
 	case TCIC_CHIPID_DB86072_1:
 		return 1;
+	}
 	return 0;
+}
 const char *
 tcic_chipid_to_string(int id)
+{
 	switch (id) {
 	case TCIC_CHIPID_DB86082_1:
 		return ("Databook DB86082");
 	case TCIC_CHIPID_DB86082A:
 		return ("Databook DB86082A");
 	case TCIC_CHIPID_DB86082B_ES:
 		return ("Databook DB86082B-es");
 	case TCIC_CHIPID_DB86082B:
 		return ("Databook DB86082B");
 	case TCIC_CHIPID_DB86084_1:
 		return ("Databook DB86084");
 	case TCIC_CHIPID_DB86084A:
 		return ("Databook DB86084A");
 	case TCIC_CHIPID_DB86184_1:
 		return ("Databook DB86184");
 	case TCIC_CHIPID_DB86072_1_ES:
 		return ("Databook DB86072-es");
 	case TCIC_CHIPID_DB86072_1:
 		return ("Databook DB86072");
+	}
 	return ("Unknown controller");
+}
 /*
  * Return bitmask of IRQs that the chip can handle.
  * XXX should be table driven.
  */
 int
 tcic_validirqs(int chipid)
+{
 	switch (chipid) {
 	case TCIC_CHIPID_DB86082_1:
 	case TCIC_CHIPID_DB86082A:
 	case TCIC_CHIPID_DB86082B_ES:
 	case TCIC_CHIPID_DB86082B:
 	case TCIC_CHIPID_DB86084_1:
 	case TCIC_CHIPID_DB86084A:
 	case TCIC_CHIPID_DB86184_1:
 	case TCIC_CHIPID_DB86072_1_ES:
 	case TCIC_CHIPID_DB86072_1:
 		return tcic_valid_irqs;
+	}
 	return 0;
+}
 void
 tcic_attach(struct tcic_softc *sc)
+{
 	int i, reg;
 	/* set more chipset dependent parameters in the softc. */
 	switch (sc->chipid) {
 	case TCIC_CHIPID_DB86084_1:
 	case TCIC_CHIPID_DB86084A:
 	case TCIC_CHIPID_DB86184_1:
 		sc->pwrena = TCIC_PWR_ENA;
 		break;
 	default:
 		sc->pwrena = 0;
 		break;
+	}
 	/* set up global config registers */
 	reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;
 	reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);
 	tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);
 	reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;
 	tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
 	reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);
 	reg |= TCIC_ILOCK_HOLD_CCLK;
 	tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);
 	/* the TCIC has two sockets */
 	/* XXX should i check for actual presence of sockets? -chb */
 	for (i = 0; i < TCIC_NSLOTS; i++) {
 		sc->handle[i].sc = sc;
 		sc->handle[i].sock = i;
 		sc->handle[i].flags = TCIC_FLAG_SOCKETP;
 		sc->handle[i].memwins
 		    = sc->chipid == TCIC_CHIPID_DB86082_1 ?  4 : 5;
+	}
 	/* establish the interrupt */
 	reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);
 	tcic_write_1(&sc->handle[0], TCIC_R_IENA,
 	    (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH);
 	reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
 	tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG,
 	    (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]);
 	/* XXX block interrupts? */
 	for (i = 0; i < TCIC_NSLOTS; i++) {
 		/* XXX make more clear what happens here -chb */
 		tcic_sel_sock(&sc->handle[i]);
 		tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0);
 		tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i),
 		    (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY
 #if 1		/* XXX explain byte routing issue */
 		    |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR));
 #else
 		    |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1));
 #endif
 		tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0);
 		reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG);
 		reg &= ~TCIC_SYSCFG_AUTOBUSY;
 		tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
 		SIMPLEQ_INIT(&sc->handle[i].events);
+	}
 	if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) ||
 	    (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) {
 		printf("%s: %s has ", device_xname(&sc->dev),
 		       tcic_chipid_to_string(sc->chipid));
 		if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) &&
 		    (sc->handle[1].flags & TCIC_FLAG_SOCKETP))
 			printf("sockets A and B\n");
 		else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP)
 			printf("socket A only\n");
 		else
 			printf("socket B only\n");
+	}
+}
 void
 tcic_attach_sockets(struct tcic_softc *sc)
+{
 	int i;
 	for (i = 0; i < TCIC_NSLOTS; i++)
 		if (sc->handle[i].flags & TCIC_FLAG_SOCKETP)
 			tcic_attach_socket(&sc->handle[i]);
+}
 void
 tcic_attach_socket(struct tcic_handle *h)
+{
 	struct pcmciabus_attach_args paa;
 	int locs[PCMCIABUSCF_NLOCS];
 	/* initialize the rest of the handle */
 	h->shutdown = 0;
 	h->memalloc = 0;
 	h->ioalloc = 0;
 	h->ih_irq = 0;
 	/* now, config one pcmcia device per socket */
 	paa.paa_busname = "pcmcia";
 	paa.pct = (pcmcia_chipset_tag_t) h->sc->pct;
 	paa.pch = (pcmcia_chipset_handle_t) h;
 	paa.iobase = h->sc->iobase;
 	paa.iosize = h->sc->iosize;
 	locs[PCMCIABUSCF_CONTROLLER] = 0;
 	locs[PCMCIABUSCF_SOCKET] = h->sock;
 	h->pcmcia = config_found_sm_loc(&h->sc->dev, "pcmciabus", locs, &paa,
 					tcic_print, config_stdsubmatch);
 	/* if there's actually a pcmcia device attached, initialize the slot */
 	if (h->pcmcia)
 		tcic_init_socket(h);
+}
 void
 tcic_create_event_thread(void *arg)
+{
 	struct tcic_handle *h = arg;
 	const char *cs;
 	switch (h->sock) {
 	case 0:
 		cs = "0";
 		break;
 	case 1:
 		cs = "1";
 		break;
 	default:
 		panic("tcic_create_event_thread: unknown tcic socket");
+	}
 	if (kthread_create(PRI_NONE, 0, NULL, tcic_event_thread, h,
 	    &h->event_thread, "%s,%s", device_xname(&h->sc->dev), cs)) {
 		aprint_error_dev(&h->sc->dev, "unable to create event thread for sock 0x%02x\n", h->sock);
 		panic("tcic_create_event_thread");
+	}
+}
 void
 tcic_event_thread(void *arg)
+{
 	struct tcic_handle *h = arg;
 	struct tcic_event *pe;
 	int s;
 	while (h->shutdown == 0) {
 		s = splhigh();
 		if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) {
 			splx(s);
 			(void) tsleep(&h->events, PWAIT, "tcicev", 0);
 			continue;
+		}
 		SIMPLEQ_REMOVE_HEAD(&h->events, pe_q);
 		splx(s);
 		switch (pe->pe_type) {
 		case TCIC_EVENT_INSERTION:
 			DPRINTF(("%s: insertion event\n", device_xname(&h->sc->dev)));
 			tcic_attach_card(h);
 			break;
 		case TCIC_EVENT_REMOVAL:
 			DPRINTF(("%s: removal event\n", device_xname(&h->sc->dev)));
 			tcic_detach_card(h, DETACH_FORCE);
 			break;
 		default:
 			panic("tcic_event_thread: unknown event %d",
 			    pe->pe_type);
+		}
 		free(pe, M_TEMP);
+	}
 	h->event_thread = NULL;
 	/* In case parent is waiting for us to exit. */
 	wakeup(h->sc);
 	kthread_exit(0);
+}
 void
 tcic_init_socket(struct tcic_handle *h)
+{
 	int reg;
 	/* select this socket's config registers */
 	tcic_sel_sock(h);
 	/* set up the socket to interrupt on card detect */
 	reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock));
 	tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD);
 	/* enable CD irq in R_IENA */
 	reg = tcic_read_2(h, TCIC_R_IENA);
 	tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG);
 	/* if there's a card there, then attach it. also save sstat */
 	h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK;
 	if (reg & TCIC_SSTAT_CD)
 		tcic_attach_card(h);
+}
 int
 tcic_print(void *arg, const char *pnp)
+{
 	struct pcmciabus_attach_args *paa = arg;
 	struct tcic_handle *h = (struct tcic_handle *) paa->pch;
 	/* Only "pcmcia"s can attach to "tcic"s... easy. */
 	if (pnp)
 		aprint_normal("pcmcia at %s", pnp);
 	aprint_normal(" socket %d", h->sock);
 	return (UNCONF);
+}
 int
 tcic_intr(void *arg)
+{
 	struct tcic_softc *sc = arg;
 	int i, ret = 0;
 	DPRINTF(("%s: intr\n", device_xname(&sc->dev)));
 	for (i = 0; i < TCIC_NSLOTS; i++)
 		if (sc->handle[i].flags & TCIC_FLAG_SOCKETP)
 			ret += tcic_intr_socket(&sc->handle[i]);
 	return (ret ? 1 : 0);
+}
 int
 tcic_intr_socket(struct tcic_handle *h)
+{
 	int icsr, rv;
 	rv = 0;
 	tcic_sel_sock(h);
 	icsr = tcic_read_1(h, TCIC_R_ICSR);
 	DPRINTF(("%s: %d icsr: 0x%02x \n", device_xname(&h->sc->dev), h->sock, icsr));
 	/* XXX or should the next three be handled in tcic_intr? -chb */
 	if (icsr & TCIC_ICSR_PROGTIME) {
 		DPRINTF(("%s: %02x PROGTIME\n", device_xname(&h->sc->dev), h->sock));
 		rv = 1;
+	}
 	if (icsr & TCIC_ICSR_ILOCK) {
 		DPRINTF(("%s: %02x ILOCK\n", device_xname(&h->sc->dev), h->sock));
 		rv = 1;
+	}
 	if (icsr & TCIC_ICSR_ERR) {
 		DPRINTF(("%s: %02x ERR\n", device_xname(&h->sc->dev), h->sock));
 		rv = 1;
+	}
 	if (icsr & TCIC_ICSR_CDCHG) {
 		int sstat, delta;
 		/* compute what changed since last interrupt */
 		sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh,
 		    TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK;
 		delta = h->sstat ^ sstat;
 		h->sstat = sstat;
 		if (delta)
 			rv = 1;
 		DPRINTF(("%s: %02x CDCHG %x\n", device_xname(&h->sc->dev), h->sock,
 		    delta));
 		/*
 		 * XXX This should probably schedule something to happen
 		 * after the interrupt handler completes
 		 */
 		if (delta & TCIC_SSTAT_CD) {
 			if (sstat & TCIC_SSTAT_CD) {
 				if (!(h->flags & TCIC_FLAG_CARDP)) {
 					DPRINTF(("%s: enqueing INSERTION event\n",
 					    device_xname(&h->sc->dev)));
 					tcic_queue_event(h, TCIC_EVENT_INSERTION);
+				}
 			} else {
 				if (h->flags & TCIC_FLAG_CARDP) {
 					/* Deactivate the card now. */
 					DPRINTF(("%s: deactivating card\n",
 					    device_xname(&h->sc->dev)));
 					tcic_deactivate_card(h);
 					DPRINTF(("%s: enqueing REMOVAL event\n",
 					    device_xname(&h->sc->dev)));
 					tcic_queue_event(h, TCIC_EVENT_REMOVAL);
+				}
+			}
+		}
 		if (delta & TCIC_SSTAT_RDY) {
 			DPRINTF(("%s: %02x READY\n", device_xname(&h->sc->dev), h->sock));
 			/* shouldn't happen */
+		}
 		if (delta & TCIC_SSTAT_LBAT1) {
 			DPRINTF(("%s: %02x LBAT1\n", device_xname(&h->sc->dev), h->sock));
+		}
 		if (delta & TCIC_SSTAT_LBAT2) {
 			DPRINTF(("%s: %02x LBAT2\n", device_xname(&h->sc->dev), h->sock));
+		}
 		if (delta & TCIC_SSTAT_WP) {
 			DPRINTF(("%s: %02x WP\n", device_xname(&h->sc->dev), h->sock));
+		}
+	}
 	return rv;
+}
 void
 tcic_queue_event(struct tcic_handle *h, int event)
+{
 	struct tcic_event *pe;
 	int s;
 	pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT);
 	if (pe == NULL)
 		panic("tcic_queue_event: can't allocate event");
 	pe->pe_type = event;
 	s = splhigh();
 	SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q);
 	splx(s);
 	wakeup(&h->events);
+}
 void
 tcic_attach_card(struct tcic_handle *h)
+{
 	DPRINTF(("tcic_attach_card\n"));
 	if (h->flags & TCIC_FLAG_CARDP)
 		panic("tcic_attach_card: already attached");
 	/* call the MI attach function */
 	pcmcia_card_attach(h->pcmcia);
 	h->flags |= TCIC_FLAG_CARDP;
+}
 void
 tcic_detach_card(struct tcic_handle *h, int flags)
 	/* flags:		 DETACH_* */
+{
 	DPRINTF(("tcic_detach_card\n"));
 	if (!(h->flags & TCIC_FLAG_CARDP))
 		panic("tcic_detach_card: already detached");
 	h->flags &= ~TCIC_FLAG_CARDP;
 	/* call the MI detach function */
 	pcmcia_card_detach(h->pcmcia, flags);
+}
 void
 tcic_deactivate_card(struct tcic_handle *h)
+{
 	int val, reg;
 	if (!(h->flags & TCIC_FLAG_CARDP))
 		 panic("tcic_deactivate_card: already detached");
 	/* call the MI deactivate function */
 	pcmcia_card_deactivate(h->pcmcia);
 	tcic_sel_sock(h);
 	/* XXX disable card detect resume and configuration reset??? */
 	/* power down the socket */
 	tcic_write_1(h, TCIC_R_PWR, 0);
 	/* reset the card XXX ? -chb */
 	/* turn off irq's for this socket */
 	reg = TCIC_IR_SCF1_N(h->sock);
 	val = tcic_read_ind_2(h, reg);
 	tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF);
 	reg = TCIC_IR_SCF2_N(h->sock);
 	val = tcic_read_ind_2(h, reg);
 	tcic_write_ind_2(h, reg,
 	    (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY
 		|TCIC_SCF2_MWP|TCIC_SCF2_MCD)));
+}
 /* XXX the following routine may need to be rewritten. -chb */
 int
 tcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	bus_space_handle_t memh;
 	bus_addr_t addr;
 	bus_size_t sizepg;
 	int i, mask, mhandle, got = 0;
 	/* out of sc->memh, allocate as many pages as necessary */
 	/*
 	 * The TCIC can map memory only in sizes that are
 	 * powers of two, aligned at the natural boundary for the size.
 	 */
 	i = tcic_log2((u_int)size);
 	if ((1<<i) < size)
 		i++;
 	sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1);
 	DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", (u_long)size,
 	    (u_long)sizepg));
 	/* can't allocate that much anyway */
 	if (sizepg > TCIC_MEM_PAGES)	/* XXX -chb */
 		return 1;
 	mask = (1 << sizepg) - 1;
 	addr = 0;		/* XXX gcc -Wuninitialized */
 	mhandle = 0;		/* XXX gcc -Wuninitialized */
 	/* XXX i should be initialised to always lay on boundary. -chb */
 	for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) {
 		if ((h->sc->subregionmask & (mask << i)) == (mask << i)) {
 			if (bus_space_subregion(h->sc->memt, h->sc->memh,
 			    i * TCIC_MEM_PAGESIZE,
 			    sizepg * TCIC_MEM_PAGESIZE, &memh))
 				return (1);
 			mhandle = mask << i;
 			addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE);
 			h->sc->subregionmask &= ~(mhandle);
 			got = 1;
 			break;
+		}
+	}
 	if (got == 0)
 		return (1);
 	DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr,
 		 (u_long) size));
 	pcmhp->memt = h->sc->memt;
 	pcmhp->memh = memh;
 	pcmhp->addr = addr;
 	pcmhp->size = size;
 	pcmhp->mhandle = mhandle;
 	pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE;
 	return (0);
+}
 /* XXX the following routine may need to be rewritten. -chb */
 void
 tcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	h->sc->subregionmask |= pcmhp->mhandle;
+}
 void
 tcic_chip_do_mem_map(struct tcic_handle *h, int win)
+{
 	int reg, hwwin, wscnt;
 	int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK;
 	int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8;
 	DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n",
 		win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size,
 		(u_long)h->mem[win].offset));
 	/*
 	 * the even windows are used for socket 0,
 	 * the odd ones for socket 1.
 	 */
 	hwwin = (win << 1) + h->sock;
 	/* the WR_MEXT register is MBZ */
 	tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0);
 	/* set the host base address and window size */
 	if (h->mem[win].size2 <= 1) {
 		reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
 		    TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K;
 	} else {
 		reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) &
 		    TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1);
+	}
 	tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg);
 	/* set the card address and address space */
 	reg = 0;
 	reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK);
 	reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0;
 	DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n",
 	    win, hwwin, reg));
 	tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg);
 	/* set the MCTL register */
 	/* must save WSCNT field in case this is a DB86082 rev 0 */
 	/* XXX why can't I do the following two in one statement? */
 	reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK;
 	reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET;
 	reg |= mem8 ? TCIC_MCTL_B8 : 0;
 	reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK;
 #ifdef notyet	/* XXX must get speed from CIS somehow. -chb */
 	wscnt = tcic_ns2wscnt(h->mem[win].speed);
 #else
 	wscnt = tcic_ns2wscnt(tcic_mem_speed);	/*  300 is "save" default for CIS memory */
 #endif
 	if (h->sc->chipid == TCIC_CHIPID_DB86082_1) {
 		/*
 		 * this chip has the wait state count in window
 		 * register 7 - hwwin.
 		 */
 		int reg2;
 		reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin));
 		reg2 &= ~TCIC_MCTL_WSCNT_MASK;
 		reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK;
 		tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2);
 	} else {
 		reg |= wscnt & TCIC_MCTL_WSCNT_MASK;
+	}
 	tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg);
 #ifdef TCICDEBUG
+	{
 		int r1, r2, r3;
 		r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin));
 		r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin));
 		r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin));
 		DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n",
 		    win, hwwin, r1, r2, r3));
+	}
 #endif
+}
 /* XXX needs work */
 int
 tcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	bus_addr_t busaddr;
 	long card_offset;
 	int i, win;
 	win = -1;
 	for (i = 0; i < h->memwins; i++) {
 		if ((h->memalloc & (1 << i)) == 0) {
 			win = i;
 			h->memalloc |= (1 << i);
 			break;
+		}
+	}
 	if (win == -1)
 		return (1);
 	*windowp = win;
 	/* XXX this is pretty gross */
 	if (!bus_space_is_equal(h->sc->memt, pcmhp->memt))
 		panic("tcic_chip_mem_map memt is bogus");
 	busaddr = pcmhp->addr;
 	/*
 	 * compute the address offset to the pcmcia address space for the
 	 * tcic.  this is intentionally signed.  The masks and shifts below
 	 * will cause TRT to happen in the tcic registers.  Deal with making
 	 * sure the address is aligned, and return the alignment offset.
 	 */
 	*offsetp = card_addr % TCIC_MEM_ALIGN;
 	card_addr -= *offsetp;
 	DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr "
 	    "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
 	    (u_long) card_addr));
 	/* XXX we can't use size. -chb */
 	/*
 	 * include the offset in the size, and decrement size by one, since
 	 * the hw wants start/stop
 	 */
 	size += *offsetp - 1;
 	card_offset = (((long) card_addr) - ((long) busaddr));
 	DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n",
 	    win, (u_long)card_offset));
 	h->mem[win].addr = busaddr;
 	h->mem[win].size = size;
 	h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT;
 	h->mem[win].offset = card_offset;
 	h->mem[win].kind = kind;
 	tcic_chip_do_mem_map(h, win);
 	return (0);
+}
 void
 tcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	int hwwin;
 	if (window >= h->memwins)
 		panic("tcic_chip_mem_unmap: window out of range");
 	hwwin = (window << 1) + h->sock;
 	tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), 0);
 	h->memalloc &= ~(1 << window);
+}
 int
 tcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	bus_space_tag_t iot;
 	bus_space_handle_t ioh;
 	bus_addr_t ioaddr;
 	int size2, flags = 0;
 	/*
 	 * Allocate some arbitrary I/O space.
 	 */
 	DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n",
 	    (u_long) start, (u_long) size, (u_long) align));
 	/*
 	 * The TCIC can map I/O space only in sizes that are
 	 * powers of two, aligned at the natural boundary for the size.
 	 */
 	size2 = tcic_log2((u_int)size);
 	if ((1 << size2) < size)
 		size2++;
 	/* can't allocate that much anyway */
 	if (size2 > 16)	/* XXX 64K -chb */
 		return 1;
 	if (align) {
 		if ((1 << size2) != align)
 			return 1;	/* not suitably  aligned */
 	} else {
 		align = 1 << size2;	/* no alignment given, make it natural */
+	}
 	if (start & (align - 1))
 		return 1;	/* not suitably aligned */
 	iot = h->sc->iot;
 	if (start) {
 		ioaddr = start;
 		if (bus_space_map(iot, start, size, 0, &ioh))
 			return (1);
 		DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n",
 		    (u_long) ioaddr, (u_long) size));
 	} else {
 		flags |= PCMCIA_IO_ALLOCATED;
 		if (bus_space_alloc(iot, h->sc->iobase,
 		    h->sc->iobase + h->sc->iosize, size, align, 0, 0,
 		    &ioaddr, &ioh))
 			return (1);
 		DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n",
 		    (u_long) ioaddr, (u_long) size));
+	}
 	pcihp->iot = iot;
 	pcihp->ioh = ioh;
 	pcihp->addr = ioaddr;
 	pcihp->size = size;
 	pcihp->flags = flags;
 	return (0);
+}
 void
 tcic_chip_io_free(pcmcia_chipset_handle_t pch,
     struct pcmcia_io_handle *pcihp)
+{
 	bus_space_tag_t iot = pcihp->iot;
 	bus_space_handle_t ioh = pcihp->ioh;
 	bus_size_t size = pcihp->size;
 	if (pcihp->flags & PCMCIA_IO_ALLOCATED)
 		bus_space_free(iot, ioh, size);
 	else
 		bus_space_unmap(iot, ioh, size);
+}
 static int tcic_iowidth_map[] =
     { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 };
 void
 tcic_chip_do_io_map(struct tcic_handle *h, int win)
+{
 	int reg, size2, iotiny, wbase, hwwin, wscnt;
 	DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n",
 	    win, (long) h->io[win].addr, (long) h->io[win].size,
 	    h->io[win].width * 8));
 	/*
 	 * the even windows are used for socket 0,
 	 * the odd ones for socket 1.
 	 */
 	hwwin = (win << 1) + h->sock;
 	/* set the WR_BASE register */
 	/* XXX what if size isn't power of 2? -chb */
 	size2 = tcic_log2((u_int)h->io[win].size);
 	DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2));
 	if (size2 < 1) {
 		iotiny = TCIC_ICTL_TINY;
 		wbase = h->io[win].addr;
 	} else {
 		iotiny = 0;
 		/* XXX we should do better -chb */
 		wbase = h->io[win].addr | (1 << (size2 - 1));
+	}
 	tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase);
 	/* set the WR_ICTL register */
 	reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET;
 	reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK;
 	reg |= iotiny | tcic_iowidth_map[h->io[win].width];
 	if (h->sc->chipid != TCIC_CHIPID_DB86082_1)
 		reg |= TCIC_ICTL_PASS16;
 #ifdef notyet	/* XXX must get speed from CIS somehow. -chb */
 	wscnt = tcic_ns2wscnt(h->io[win].speed);
 #else
 	wscnt = tcic_ns2wscnt(tcic_io_speed);	/* linux uses 0 as default */
 #endif
 	reg |= wscnt & TCIC_ICTL_WSCNT_MASK;
 	tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg);
 #ifdef TCICDEBUG
+	{
 		int r1, r2;
 		r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin));
 		r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin));
 		DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n",
 		    win, hwwin, r1, r2));
+	}
 #endif
+}
 int
 tcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	bus_addr_t ioaddr = pcihp->addr + offset;
 	int i, win;
 #ifdef TCICDEBUG
 	static const char *width_names[] = { "auto", "io8", "io16" };
 #endif
 	/* XXX Sanity check offset/size. */
 	win = -1;
 	for (i = 0; i < TCIC_IO_WINS; i++) {
 		if ((h->ioalloc & (1 << i)) == 0) {
 			win = i;
 			h->ioalloc |= (1 << i);
 			break;
+		}
+	}
 	if (win == -1)
 		return (1);
 	*windowp = win;
 	/* XXX this is pretty gross */
 	if (!bus_space_is_equal(h->sc->iot, pcihp->iot))
 		panic("tcic_chip_io_map iot is bogus");
 	DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n",
 		 win, width_names[width], (u_long) ioaddr, (u_long) size));
 	/* XXX wtf is this doing here? */
 	printf("%s: port 0x%lx", device_xname(&h->sc->dev), (u_long) ioaddr);
 	if (size > 1)
 		printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
 	printf("\n");
 	h->io[win].addr = ioaddr;
 	h->io[win].size = size;
 	h->io[win].width = width;
 	tcic_chip_do_io_map(h, win);
 	return (0);
+}
 void
 tcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	int hwwin;
 	if (window >= TCIC_IO_WINS)
 		panic("tcic_chip_io_unmap: window out of range");
 	hwwin = (window << 1) + h->sock;
 	tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), 0);
 	h->ioalloc &= ~(1 << window);
+}
 void
 tcic_chip_socket_enable(pcmcia_chipset_handle_t pch)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	int reg, win;
 	tcic_sel_sock(h);
 	/*
 	 * power down the socket to reset it.
 	 * put card reset into high-z, put chip outputs to card into high-z
 	 */
 	tcic_write_1(h, TCIC_R_PWR, 0);
 	reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
 	reg |= TCIC_ILOCK_CWAIT;
 	reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA);
 	tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 	tcic_write_1(h, TCIC_R_SCTRL, 0);	/* clear TCIC_SCTRL_ENA */
 	/* zero out the address windows */
 	tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), 0);
 	/* writing to WR_MBASE_N disables the window */
 	for (win = 0; win < h->memwins; win++) {
 		tcic_write_ind_2(h, TCIC_WR_MBASE_N((win << 1) + h->sock), 0);
+	}
 	/* writing to WR_IBASE_N disables the window */
 	for (win = 0; win < TCIC_IO_WINS; win++) {
 		tcic_write_ind_2(h, TCIC_WR_IBASE_N((win << 1) + h->sock), 0);
+	}
 	/* power up the socket */
 	/* turn on VCC, turn of VPP */
 	reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena;
 	if (h->sc->pwrena)		/* this is a '84 type chip */
 		reg |= TCIC_PWR_VCC5V;
 	tcic_write_1(h, TCIC_R_PWR, reg);
 	delay(10000);
 	/* enable reset and wiggle it to reset the card */
 	reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
 	reg |= TCIC_ILOCK_CRESENA;
 	tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 	/* XXX need bus_space_barrier here */
 	reg |= TCIC_ILOCK_CRESET;
 	tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 	/* enable card signals */
 	tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA);
 	delay(10);	/* wait 10 us */
 	/* clear the reset flag */
 	reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
 	reg &= ~(TCIC_ILOCK_CRESET);
 	tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg);
 	/* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
 	delay(20000);
 	/* wait for the chip to finish initializing */
 	tcic_wait_ready(h);
 	/* WWW */
 	/* reinstall all the memory and io mappings */
 	for (win = 0; win < h->memwins; win++)
 		if (h->memalloc & (1 << win))
 			tcic_chip_do_mem_map(h, win);
 	for (win = 0; win < TCIC_IO_WINS; win++)
 		if (h->ioalloc & (1 << win))
 			tcic_chip_do_io_map(h, win);
+}
 void
 tcic_chip_socket_settype(pcmcia_chipset_handle_t pch, int type)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	int reg;
 	tcic_sel_sock(h);
 	/* set the card type */
 	reg = 0;
 	if (type == PCMCIA_IFTYPE_IO) {
 		reg |= TCIC_SCF1_IOSTS;
 		reg |= tcic_irqmap[h->ih_irq];		/* enable interrupts */
+	}
 	tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg);
 	DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n",
 	    device_xname(&h->sc->dev), h->sock,
 	    ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg));
+}
 void
 tcic_chip_socket_disable(pcmcia_chipset_handle_t pch)
+{
 	struct tcic_handle *h = (struct tcic_handle *) pch;
 	int val;
 	DPRINTF(("tcic_chip_socket_disable\n"));
 	tcic_sel_sock(h);
 	/* disable interrupts */
 	val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock));
 	val &= TCIC_SCF1_IRQ_MASK;
 	tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val);
 	/* disable the output signals */
 	tcic_write_1(h, TCIC_R_SCTRL, 0);
 	val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK);
 	val &= ~TCIC_ILOCK_CRESENA;
 	tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val);
 	/* power down the socket */
 	tcic_write_1(h, TCIC_R_PWR, 0);
+}
 /*
  * XXX The following is Linux driver but doesn't match the table
  * in the manual.
  */
 int
 tcic_ns2wscnt(int ns)
+{
 	if (ns < 14) {
 		return 0;
 	} else {
 		return (2*(ns-14))/70;	/* XXX assumes 14.31818 MHz clock. */
+	}
+}
 int
 tcic_log2(u_int val)
+{
 	int i, l2;
 	l2 = i = 0;
 	while (val) {
 		if (val & 1)
 			l2 = i;
 		i++;
 		val >>= 1;
+	}
 	return l2;
+}