Sun Jul 31 15:35:04 2011 UTC ()
Add define for loongson2 DIAG register


(matt)
diff -r1.83 -r1.84 src/sys/arch/mips/include/cpuregs.h
cvs diff -r1.83 -r1.84 src/sys/arch/mips/include/cpuregs.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cpuregs.h 2011/04/06 05:42:45 1.83
+++ src/sys/arch/mips/include/cpuregs.h 2011/07/31 15:35:04 1.84
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpuregs.h,v 1.83 2011/04/06 05:42:45 matt Exp $ */ 1/* $NetBSD: cpuregs.h,v 1.84 2011/07/31 15:35:04 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem. 8 * Ralph Campbell and Rick Macklem.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -490,26 +490,27 @@ @@ -490,26 +490,27 @@
490 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier. 490 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
491 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base. 491 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base.
492 * 16 MIPS_COP_0_CONFIG 3333 Configuration register. 492 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
493 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1. 493 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
494 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2. 494 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
495 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3. 495 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
496 * 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6. 496 * 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6.
497 * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7. 497 * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
498 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address. 498 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
499 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register. 499 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
500 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register. 500 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
501 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register. 501 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
502 * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7) 502 * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7)
 503 * 22 MIPS_COP_0_DIAG ...6 [LOONGSON2] Diagnostic register.
503 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register. 504 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
504 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register. 505 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
505 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register. 506 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
506 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register. 507 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
507 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register. 508 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
508 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr). 509 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
509 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr). 510 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
510 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data). 511 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
511 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data). 512 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
512 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr). 513 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
513 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr). 514 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
514 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data). 515 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
515 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data). 516 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
@@ -552,26 +553,27 @@ @@ -552,26 +553,27 @@
552#define MIPS_COP_0_LLADDR _(17) 553#define MIPS_COP_0_LLADDR _(17)
553#define MIPS_COP_0_WATCH_LO _(18) 554#define MIPS_COP_0_WATCH_LO _(18)
554#define MIPS_COP_0_WATCH_HI _(19) 555#define MIPS_COP_0_WATCH_HI _(19)
555#define MIPS_COP_0_TLB_XCONTEXT _(20) 556#define MIPS_COP_0_TLB_XCONTEXT _(20)
556#define MIPS_COP_0_ECC _(26) 557#define MIPS_COP_0_ECC _(26)
557#define MIPS_COP_0_CACHE_ERR _(27) 558#define MIPS_COP_0_CACHE_ERR _(27)
558#define MIPS_COP_0_TAG_LO _(28) 559#define MIPS_COP_0_TAG_LO _(28)
559#define MIPS_COP_0_TAG_HI _(29) 560#define MIPS_COP_0_TAG_HI _(29)
560#define MIPS_COP_0_ERROR_PC _(30) 561#define MIPS_COP_0_ERROR_PC _(30)
561 562
562/* MIPS32/64 */ 563/* MIPS32/64 */
563#define MIPS_COP_0_HWRENA _(7) 564#define MIPS_COP_0_HWRENA _(7)
564#define MIPS_COP_0_OSSCRATCH _(22) 565#define MIPS_COP_0_OSSCRATCH _(22)
 566#define MIPS_COP_0_DIAG _(22)
565#define MIPS_COP_0_DEBUG _(23) 567#define MIPS_COP_0_DEBUG _(23)
566#define MIPS_COP_0_DEPC _(24) 568#define MIPS_COP_0_DEPC _(24)
567#define MIPS_COP_0_PERFCNT _(25) 569#define MIPS_COP_0_PERFCNT _(25)
568#define MIPS_COP_0_DATA_LO _(28) 570#define MIPS_COP_0_DATA_LO _(28)
569#define MIPS_COP_0_DATA_HI _(29) 571#define MIPS_COP_0_DATA_HI _(29)
570#define MIPS_COP_0_DESAVE _(31) 572#define MIPS_COP_0_DESAVE _(31)
571 573
572/* 574/*
573 * Values for the code field in a break instruction. 575 * Values for the code field in a break instruction.
574 */ 576 */
575#define MIPS_BREAK_INSTR 0x0000000d 577#define MIPS_BREAK_INSTR 0x0000000d
576#define MIPS_BREAK_VAL_MASK 0x03ff0000 578#define MIPS_BREAK_VAL_MASK 0x03ff0000
577#define MIPS_BREAK_VAL_SHIFT 16 579#define MIPS_BREAK_VAL_SHIFT 16