Sun Jul 31 15:36:28 2011 UTC ()
Add CPU_MIPS_LOONGSON2 flag (rather defining a CPU_ARCH_MIPS3_LOONGSON2).
This is much less intrusive and disruptive.


(matt)
diff -r1.103 -r1.104 src/sys/arch/mips/include/cpu.h
cvs diff -r1.103 -r1.104 src/sys/arch/mips/include/cpu.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/cpu.h 2011/07/06 09:27:35 1.103
+++ src/sys/arch/mips/include/cpu.h 2011/07/31 15:36:28 1.104
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: cpu.h,v 1.103 2011/07/06 09:27:35 matt Exp $ */ 1/* $NetBSD: cpu.h,v 1.104 2011/07/31 15:36:28 matt Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem. 8 * Ralph Campbell and Rick Macklem.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -270,26 +270,27 @@ extern struct mips_options mips_options; @@ -270,26 +270,27 @@ extern struct mips_options mips_options;
270#define CPU_MIPS_R4K_MMU 0x0001 270#define CPU_MIPS_R4K_MMU 0x0001
271#define CPU_MIPS_NO_LLSC 0x0002 271#define CPU_MIPS_NO_LLSC 0x0002
272#define CPU_MIPS_CAUSE_IV 0x0004 272#define CPU_MIPS_CAUSE_IV 0x0004
273#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 273#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */
274#define CPU_MIPS_CACHED_CCA_MASK 0x0070 274#define CPU_MIPS_CACHED_CCA_MASK 0x0070
275#define CPU_MIPS_CACHED_CCA_SHIFT 4 275#define CPU_MIPS_CACHED_CCA_SHIFT 4
276#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 276#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
277#define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 277#define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */
278#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 278#define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */
279#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 279#define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */
280#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 280#define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */
281#define CPU_MIPS_NO_LLADDR 0x1000 281#define CPU_MIPS_NO_LLADDR 0x1000
282#define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 282#define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */
 283#define CPU_MIPS_LOONGSON2 0x4000
283#define MIPS_NOT_SUPP 0x8000 284#define MIPS_NOT_SUPP 0x8000
284 285
285#endif /* !_LOCORE */ 286#endif /* !_LOCORE */
286 287
287#if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 288#if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE)
288 289
289#if defined(MIPS1) 290#if defined(MIPS1)
290 291
291# define CPUISMIPS3 0 292# define CPUISMIPS3 0
292# define CPUIS64BITS 0 293# define CPUIS64BITS 0
293# define CPUISMIPS32 0 294# define CPUISMIPS32 0
294# define CPUISMIPS32R2 0 295# define CPUISMIPS32R2 0
295# define CPUISMIPS64 0 296# define CPUISMIPS64 0