 @@ -1,14 +1,14 @@
-/*	$NetBSD: mipsX_subr.S,v 1.50 2011/07/10 23:21:59 matt Exp $	*/
+/*	$NetBSD: mipsX_subr.S,v 1.51 2011/07/31 15:39:29 matt Exp $	*/
 /*
  * Copyright 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -218,27 +218,29 @@
 #if defined(MIPS64)
 	.set	mips64
 #endif
 #if defined(MIPS64R2)
 	.set	mips64r2
 #endif
 /*
  * CPP function renaming macros.
  */
-#if defined(MIPS3)
+#if defined(MIPS3_LOONGSON2)
 #define	MIPSX(name)	__CONCAT(loongson2_,name)
 #elif defined(MIPS3)
 #define	MIPSX(name)	__CONCAT(mips3_,name)
 #endif
 #if defined(MIPS32)
 #define	MIPSX(name)	__CONCAT(mips32_,name)
 #endif
 #if defined(MIPS32R2)
 #define	MIPSX(name)	__CONCAT(mips32r2_,name)
 #endif
 #if defined(MIPS64)
 #define	MIPSX(name)	__CONCAT(mips64_,name)
 @@ -1629,27 +1631,30 @@ LEAF_NOPROFILE(MIPSX(tlb_invalid_excepti
 	_SLL	k0, k0, WIRED_SHIFT
 	mfc0	k1, MIPS_COP_0_TLB_INDEX
 	_SRL	k0, k0, WIRED_SHIFT
 	sltiu	k1, k1, MIPS3_TLB_WIRED_UPAGES	# Luckily this is MIPS3_PG_G
 	or	k1, k1, k0
 	_MTC0	k0, MIPS_COP_0_TLB_LO1		# load PTE entry
 	COP0_SYNC
 #ifdef MIPS3
 	nop
 	nop					# required for QED5230
 #endif
 	tlbwi					# write TLB
 	COP0_SYNC
-#ifdef MIPS3
+#ifdef MIPS3_LOONGSON2
 	li	k0, 4				# ugly
 	mtc0	k0, MIPS_COP_0_DIAG		# invalidate ITLB
 #elif defined(MIPS3)
 	nop
 	nop
 #endif
 	eret
 MIPSX(kern_tlbi_odd):
 	INT_L	k0, 0(k1)			# get PTE entry
 	_SLL	k0, k0, WIRED_SHIFT		# get rid of wired bit
 	_SRL	k0, k0, WIRED_SHIFT
 	_MTC0	k0, MIPS_COP_0_TLB_LO1		# save PTE entry
 	COP0_SYNC
 	and	k0, k0, MIPS3_PG_V		# check for valid entry
 #ifdef MIPS3
 @@ -1661,27 +1666,30 @@ MIPSX(kern_tlbi_odd):
 	INT_L	k0, -4(k1)			# get even PTE entry
 	_SLL	k0, k0, WIRED_SHIFT
 	mfc0	k1, MIPS_COP_0_TLB_INDEX
 	_SRL	k0, k0, WIRED_SHIFT
 	sltiu	k1, k1, MIPS3_TLB_WIRED_UPAGES	# Luckily this is MIPS3_PG_G
 	or	k1, k1, k0
 	_MTC0	k0, MIPS_COP_0_TLB_LO0		# save PTE entry
 	COP0_SYNC
 #ifdef MIPS3
 	nop					# required for QED5230
 #endif
 	tlbwi					# update TLB
 	COP0_SYNC
-#ifdef MIPS3
+#ifdef MIPS3_LOONGSON2
 	li	k0, 4				# ugly
 	mtc0	k0, MIPS_COP_0_DIAG		# invalidate ITLB
 #elif defined(MIPS3)
 	nop
 	nop
 #endif
 	eret
 END(MIPSX(tlb_invalid_exception))
 /*
  * Mark where code entered from exception hander jumptable
  * ends, for stack traceback code.
  */
 	.globl	_C_LABEL(MIPSX(exceptionentry_end))
 _C_LABEL(MIPSX(exceptionentry_end)):
 @@ -1743,46 +1751,52 @@ LEAF(MIPSX(tlb_update))
 	 nop
 # EVEN
 	bltz	v0, 1f				# index < 0 => !found
 	 nop
 #ifdef MIPS3
 	nop					# required for QED5230
 #endif
 	tlbr					# update, read entry first
 	COP0_SYNC
 	_MTC0	a1, MIPS_COP_0_TLB_LO0		# init low reg0.
 	COP0_SYNC
 	tlbwi					# update slot found
 	COP0_SYNC
-#ifdef MIPS3
+#ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #elif defined(MIPS3)
 	nop					# required for QED5230
 	nop					# required for QED5230
 #endif
 	b	4f
 	 nop
 :
 # ODD
 	bltz	v0, 4f				# index < 0 => !found
 	 nop
 #ifdef MIPS3
 	nop					# required for QED5230
 #endif
 	tlbr					# read the entry first
 	COP0_SYNC
 	_MTC0	a1, MIPS_COP_0_TLB_LO1		# init low reg1.
 	COP0_SYNC
 	tlbwi					# update slot found
 	COP0_SYNC
-#ifdef MIPS3
+#ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #elif defined(MIPS3)
 	nop					# required for QED5230
 	nop					# required for QED5230
 #endif
 :
 #ifdef MIPS3
 	nop					# Make sure pipeline
 	nop					# advances before we
 	nop					# use the TLB.
 	nop
 #endif
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# restore PID
 	COP0_SYNC
 #ifdef MIPS3
 @@ -1880,27 +1894,30 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_addr
 	_MTC0	zero, MIPS_COP_0_TLB_LO0	# zero out entryLo0
 	_MTC0	zero, MIPS_COP_0_TLB_LO1	# zero out entryLo1
 #if 0
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out pageMask
 #endif
 	COP0_SYNC
 #ifdef MIPS3
 	nop
 	nop
 #endif
 	tlbwi
 	COP0_SYNC
-#ifdef MIPS3
+#ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #elif defined(MIPS3)
 	nop
 	nop
 #endif
 :
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# restore current ASID
 	mtc0	t3, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	COP0_SYNC
 	mtc0	v1, MIPS_COP_0_STATUS		# restore status register
 	JR_HB_RA
 END(MIPSX(tlb_invalidate_addr))
 /*
  * void mipsN_tlb_invalidate_asids(uint32_t base, uint32_t limit);
 @@ -1946,26 +1963,32 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_asid
 	_MTC0	zero, MIPS_COP_0_TLB_LO1	# zero out entryLo1
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out mask entry
 	COP0_SYNC
 	tlbwi					# invalidate the TLB entry
 	COP0_SYNC
 :
 	addu	t1, 1
 	bne	t1, t2, 1b
 	 nop
 	_MFC0	t0, MIPS_COP_0_TLB_HI		# restore PID.
 	mtc0	t3, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	COP0_SYNC
 #ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #endif
 	mtc0	v1, MIPS_COP_0_STATUS		# restore status register
 	JR_HB_RA				# new ASID will be set soon
 END(MIPSX(tlb_invalidate_asids))
 /*
  * void mipsN_tlb_invalidate_globals(void);
+ *
  * Invalidate the non-wired TLB entries belonging to kernel space while
  * leaving entries for user space (not marked global) intact.
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_globals))
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 @@ -1995,26 +2018,32 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_glob
 	_MTC0	zero, MIPS_COP_0_TLB_LO1	# zero out entryLo1
 	mtc0	zero, MIPS_COP_0_TLB_PG_MASK	# zero out mask entry
 	COP0_SYNC
 	tlbwi					# invalidate the TLB entry
 	COP0_SYNC
 :
 	addu	t1, 1
 	bne	t1, t2, 1b
 	 nop
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# restore current ASID
 	mtc0	t3, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	COP0_SYNC
 #ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #endif
 	mtc0	v1, MIPS_COP_0_STATUS		# restore status register
 	JR_HB_RA
 END(MIPSX(tlb_invalidate_globals))
 /*
  * void mipsN_tlb_invalidate_all(void);
+ *
  * Invalidate all of non-wired TLB entries.
  */
 LEAF_NOPROFILE(MIPSX(tlb_invalidate_all))
 	mfc0	v1, MIPS_COP_0_STATUS		# save status register
 	mtc0	zero, MIPS_COP_0_STATUS		# disable interrupts
 	COP0_SYNC
 @@ -2037,26 +2066,32 @@ LEAF_NOPROFILE(MIPSX(tlb_invalidate_all)
 	sll	ta0, t1, PGSHIFT + 1		# PAGE_SHIFT + 1
 	PTR_ADDU ta0, v0
 	_MTC0	ta0, MIPS_COP_0_TLB_HI		# make entryHi invalid
 	COP0_SYNC
 	tlbwi					# clear the entry
 	COP0_SYNC
 	addu	t1, 1				# increment index
 	bne	t1, a0, 1b
 	 nop
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# restore ASID
 	mtc0	t2, MIPS_COP_0_TLB_PG_MASK	# restore pgMask
 	COP0_SYNC
 #ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #endif
 	mtc0	v1, MIPS_COP_0_STATUS		# restore status register
 	JR_HB_RA
 END(MIPSX(tlb_invalidate_all))
 /*
  * u_int mipsN_tlb_record_asids(u_long *bitmap, uint32_t asid_mask)
+ *
  * Record all the ASIDs in use in the TLB and return the number of different
  * ASIDs present.
  */
 LEAF_NOPROFILE(MIPSX(tlb_record_asids))
 	_MFC0	a3, MIPS_COP_0_TLB_HI		# Save the current PID.
 	mfc0	ta0, MIPS_COP_0_TLB_WIRED
 @@ -2194,26 +2229,32 @@ LEAF(MIPSX(tlb_enter))
 	or	t2, ta2, ta3			# t2 = (v1 & t2) | (~v1 & a2)
 	and	ta2, t3, v0
 	and	ta3, a2, v1
 	or	t3, ta2, ta3			# t3 = (~v1 & t3) | (v1 & a2)
 	mtc0	t2, MIPS_COP_0_TLB_LO0		# set tlb_lo0 (even)
 	mtc0	t3, MIPS_COP_0_TLB_LO1		# set tlb_lo1 (odd)
 	COP0_SYNC
 	tlbwi					# enter it into the TLB
 	COP0_SYNC
 	_MTC0	ta1, MIPS_COP_0_TLB_HI		# restore EntryHi
 #ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #endif
 	JR_HB_RA
 	.set	at
 END(MIPSX(tlb_enter))
 /*
  * mipsN_lwp_trampoline()
+ *
  * Arrange for a function to be invoked neatly, after a cpu_switch().
  * Call the service function with one argument, specified by the s0
  * and s1 respectively.  There is no need register save operation.
  */
 LEAF(MIPSX(lwp_trampoline))
 	PTR_ADDU sp, -CALLFRAME_SIZ
 @@ -2422,26 +2463,32 @@ LEAF(MIPSX(tlb_write_indexed))
 	mtc0	a0, MIPS_COP_0_TLB_INDEX	# Set the index.
 	mtc0	a2, MIPS_COP_0_TLB_PG_MASK	# Set up entry pagemask.
 	_MTC0	a3, MIPS_COP_0_TLB_HI		# Set up entry high.
 	COP0_SYNC
 	tlbwi					# Write the TLB
 	COP0_SYNC
 #ifdef MIPS3
 	nop
 #endif
 	_MTC0	t0, MIPS_COP_0_TLB_HI		# Restore the PID.
 	mtc0	v0, MIPS_COP_0_TLB_PG_MASK	# Restore page mask.
 	COP0_SYNC
 #ifdef MIPS3_LOONGSON2
 	li	v0, 4				# ugly
 	mtc0	v0, MIPS_COP_0_DIAG		# invalidate ITLB
 #endif
 	mtc0	v1, MIPS_COP_0_STATUS		# Restore the status register
 	JR_HB_RA
 END(MIPSX(tlb_write_indexed))
 #if defined(MIPS3)
 /*----------------------------------------------------------------------------
+ *
  * mipsN_VCED --
+ *
  *	Handle virtual coherency exceptions.
  *	Called directly from the mips3 exception-table code.
  *	only k0, k1 are available on entry
+ *

 @@ -1,14 +1,14 @@
-/*	$NetBSD: mips_machdep.c,v 1.244 2011/06/14 05:30:40 matt Exp $	*/
+/*	$NetBSD: mips_machdep.c,v 1.245 2011/07/31 15:39:29 matt Exp $	*/
 /*
  * Copyright 2002 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Simon Burge for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -102,27 +102,27 @@
  * Junior University. All Rights Reserved.
+ *
  * Permission to use, copy, modify, and distribute this
  * software and its documentation for any purpose and without
  * fee is hereby granted, provided that the above copyright
  * notice appear in all copies.  Stanford University
  * makes no representations about the suitability of this
  * software for any purpose.  It is provided "as is" without
  * express or implied warranty.
  */
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.244 2011/06/14 05:30:40 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.245 2011/07/31 15:39:29 matt Exp $");
 #define __INTR_PRIVATE
 #include "opt_cputype.h"
 #include "opt_compat_netbsd32.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/proc.h>
 #include <sys/intr.h>
 #include <sys/exec.h>
 #include <sys/reboot.h>
 #include <sys/mount.h>			/* fsid_t for syscallargs */
 #include <sys/lwp.h>
 @@ -210,26 +210,32 @@ int safepri = IPL_SOFTSERIAL;
 #if defined(MIPS1)
 static void	mips1_vector_init(const struct splsw *);
 extern const struct locoresw mips1_locoresw;
 extern const mips_locore_jumpvec_t mips1_locore_vec;
 #endif
 #if defined(MIPS3)
 static void	mips3_vector_init(const struct splsw *);
 extern const struct locoresw mips3_locoresw;
 extern const mips_locore_jumpvec_t mips3_locore_vec;
 #endif
 #if defined(MIPS3_LOONGSON2)
 static void	loongson2_vector_init(const struct splsw *);
 extern const struct locoresw loongson2_locoresw;
 extern const mips_locore_jumpvec_t loongson2_locore_vec;
 #endif
 #if defined(MIPS32)
 static void	mips32_vector_init(const struct splsw *);
 extern const struct locoresw mips32_locoresw;
 extern const mips_locore_jumpvec_t mips32_locore_vec;
 #endif
 #if defined(MIPS32R2)
 static void	mips32r2_vector_init(const struct splsw *);
 extern const struct locoresw mips32r2_locoresw;
 extern const mips_locore_jumpvec_t mips32r2_locore_vec;
 #endif
 #if defined(MIPS64)
 @@ -422,31 +428,31 @@ static const struct pridtab cputab[] = {
 	/*
 	 * ICT Loongson2 is a MIPS64 CPU with a few quirks.  For some reason
 	 * the virtual aliases present with 4KB pages make the caches misbehave
 	 * so we make all accesses uncached.  With 16KB pages, no virtual
 	 * aliases are possible so we can use caching.
 	 */
 #ifdef ENABLE_MIPS_16KB_PAGE
 #define	MIPS_LOONGSON2_CCA	0
 #else
 #define	MIPS_LOONGSON2_CCA	(CPU_MIPS_HAVE_SPECIAL_CCA | \
 				(2 << CPU_MIPS_CACHED_CCA_SHIFT))
 #endif
 	{ 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2E, -1, CPU_ARCH_MIPS3, 64,
-	  CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | MIPS_LOONGSON2_CCA, 0, 0,
+	  CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2
-						"ICT Loongson 2E CPU"	},
+	  | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2E CPU"	},
 	{ 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2F, -1, CPU_ARCH_MIPS3, 64,
-	  CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | MIPS_LOONGSON2_CCA, 0, 0,
+	  CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2
-						"ICT Loongson 2F CPU"	},
+	  | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2F CPU"	},
 #if 0 /* ID collisions : can we use a CU1 test or similar? */
 	{ 0, MIPS_R3SONY, -1, -1,		CPU_ARCH_MIPS1, -1,
 	  MIPS_NOT_SUPP, 0, 0,			"SONY R3000 derivative"	},	/* 0x21; crash R4700? */
 	{ 0, MIPS_R3NKK, -1, -1,		CPU_ARCH_MIPS1, -1,
 	  MIPS_NOT_SUPP, 0, 0,			"NKK R3000 derivative"	},	/* 0x23; crash R5000? */
 #endif
 	{ MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1,	-1, 0,
 	  MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4Kc"		},
 	{ MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1,	-1, 0,
 	  MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc"		},
 	{ MIPS_PRID_CID_MTI, MIPS_4KEc_R2, -1, -1, -1, 0,
 @@ -469,26 +475,27 @@ static const struct pridtab cputab[] = {
 	  MIPS_CP0FL_USE |
 	  MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
 	  MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
 	  MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
 , "24KE" },
 	{ MIPS_PRID_CID_MTI, MIPS_34K, -1, -1,	-1, 0,
 	  MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
 	  MIPS_CP0FL_USE |
 	  MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
 	  MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
 	  MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7,
 , "34K" },
 	{ MIPS_PRID_CID_MTI, MIPS_74K, -1, -1,	-1, 0,
 	  CPU_MIPS_HAVE_SPECIAL_CCA | (0 << CPU_MIPS_CACHED_CCA_SHIFT) |
 	  MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
 	  MIPS_CP0FL_USE |
 	  MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
 	  MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
 	  MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
 , "74K" },
 	{ MIPS_PRID_CID_MTI, MIPS_1004K, -1, -1,	-1, 0,
 	  MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT,
 	  MIPS_CP0FL_USE |
 	  MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA |
 	  MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 |
 	  MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7,
 , "1004K" },
 @@ -732,26 +739,73 @@ mips3_vector_init(const struct splsw *sp
 	/*
 	 * Copy locore-function vector.
 	 */
 	mips_locore_jumpvec = mips3_locore_vec;
 	mips_icache_sync_all();
 	mips_dcache_wbinv_all();
 	/* Clear BEV in SR so we start handling our own exceptions */
 	mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+}
 #endif /* MIPS3 */
 #if defined(MIPS3_LOONGSON2)
 static void
 loongson2_vector_init(const struct splsw *splsw)
+{
 	/* r4000 exception handler address and end */
 	extern char loongson2_exception[], loongson2_exception_end[];
 	/* TLB miss handler address and end */
 	extern char loongson2_tlb_miss[];
 	extern char loongson2_xtlb_miss[];
 	/* Cache error handler */
 	extern char loongson2_cache[];
 	/*
 	 * Copy down exception vector code.
 	 */
 	if (loongson2_xtlb_miss - loongson2_tlb_miss != 0x80)
 		panic("startup: %s vector code not 128 bytes in length",
 		    "UTLB");
 	if (loongson2_cache - loongson2_xtlb_miss != 0x80)
 		panic("startup: %s vector code not 128 bytes in length",
 		    "XTLB");
 	if (loongson2_exception - loongson2_cache != 0x80)
 		panic("startup: %s vector code not 128 bytes in length",
 		    "Cache error");
 	if (loongson2_exception_end - loongson2_exception > 0x80)
 		panic("startup: %s vector code too large",
 		    "General exception");
 	memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, loongson2_tlb_miss,
 	      loongson2_exception_end - loongson2_tlb_miss);
 	/*
 	 * Copy locore-function vector.
 	 */
 	mips_locore_jumpvec = loongson2_locore_vec;
 	mips_icache_sync_all();
 	mips_dcache_wbinv_all();
 	/* Clear BEV in SR so we start handling our own exceptions */
 	mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV);
+}
 #endif /* MIPS3_LOONGSON2 */
 #if defined(MIPS32)
 static void
 mips32_vector_init(const struct splsw *splsw)
+{
 	/* r4000 exception handler address */
 	extern char mips32_exception[];
 	/* TLB miss handler addresses */
 	extern char mips32_tlb_miss[];
 	/* Cache error handler */
 	extern char mips32_cache[];
 @@ -1164,32 +1218,41 @@ mips_vector_init(const struct splsw *spl
 		break;
 #endif
 #if defined(MIPS3)
 	case CPU_ARCH_MIPS3:
 	case CPU_ARCH_MIPS4:
 		mips3_tlb_probe();
 #if defined(MIPS3_4100)
 		if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100)
 			mips3_cp0_pg_mask_write(MIPS4100_PG_SIZE_TO_MASK(PAGE_SIZE));
 		else
 #endif
 		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE));
 		mips3_cp0_wired_write(0);
 #if defined(MIPS3_LOONGSON2)
 		if (opts->mips_cpu_flags & CPU_MIPS_LOONGSON2) {
 			(*loongson2_locore_vec.ljv_tlb_invalidate_all)();
 			mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
 			loongson2_vector_init(splsw);
 			mips_locoresw = loongson2_locoresw;
 			break;
+		}
 #endif /* MIPS3_LOONGSON2 */
 		(*mips3_locore_vec.ljv_tlb_invalidate_all)();
 		mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
 		mips3_vector_init(splsw);
 		mips_locoresw = mips3_locoresw;
 		break;
-#endif
+#endif /* MIPS3 */
 #if defined(MIPS32)
 	case CPU_ARCH_MIPS32:
 		mips3_tlb_probe();
 		mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE));
 		mips3_cp0_wired_write(0);
 		(*mips32_locore_vec.ljv_tlb_invalidate_all)();
 		mips3_cp0_wired_write(pmap_tlb0_info.ti_wired);
 		mips32_vector_init(splsw);
 		mips_locoresw = mips32_locoresw;
 		break;
 #endif
 #if defined(MIPS32R2)
 	case CPU_ARCH_MIPS32R2:

 @@ -1,42 +1,43 @@
-#	$NetBSD: files.mips,v 1.70 2011/06/12 03:35:43 rmind Exp $
+#	$NetBSD: files.mips,v 1.71 2011/07/31 15:39:28 matt Exp $
+#
 defflag	opt_cputype.h		NOFPU FPEMUL
 				MIPS64_SB1
 				MIPS3_LOONGSON2F
 				ENABLE_MIPS_16KB_PAGE
 				MIPS64_XLP MIPS64_XLR MIPS64_XLS
 					# and the rest...
 					# MIPS1	MIPS2 MIPS3 MIPS4 MIPS5
 					# MIPS3_LOONGSON2
 					# MIPS32 MIPS32R2 MIPS64 MIPS64R2
 					# MIPS3_4100
 					# ENABLE_MIPS_4KB_PAGE
 					# ENABLE_MIPS_TX3900
 					# ENABLE_MIPS_R4700
 					# ENABLE_MIPS_R3NKK
 defflag	opt_mips_cache.h		MIPS3_NO_PV_UNCACHED
 					ENABLE_MIPS4_CACHE_R10K
 defflag opt_mips3_wired.h		ENABLE_MIPS3_WIRED_MAP
 defflag	opt_ddb.h		DDB_TRACE
 file	arch/mips/mips/locore_mips1.S		mips1
 file	arch/mips/mips/locore_mips3.S		mips3|mips4|mips32|mips32r2|mips64|mips64r2
 file	arch/mips/mips/mips3_subr.S		mips3|mips4
 file	arch/mips/mips/mips32_subr.S		mips32
 file	arch/mips/mips/mips32r2_subr.S		mips32r2
 file	arch/mips/mips/mips64_subr.S		mips64
 file	arch/mips/mips/mips64r2_subr.S		mips64r2
 file	arch/mips/mips/loongson2_subr.S		mips3_loongson2
 file	arch/mips/mips/sigcode.S
 file	arch/mips/mips/copy.S
 file	arch/mips/mips/lock_stubs_llsc.S	multiprocessor
 file	arch/mips/mips/lock_stubs_ras.S
 file	arch/mips/mips/spl.S
 file	arch/mips/mips/spl_stubs.c
 file	arch/mips/mips/core_machdep.c		coredump
 file	arch/mips/mips/cpu_subr.c
 file	arch/mips/mips/db_disasm.c		ddb
 file	arch/mips/mips/db_interface.c		ddb | kgdb
 file	arch/mips/mips/db_trace.c		ddb
 file	arch/mips/mips/ipifuncs.c		multiprocessor

 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore_mips3.S,v 1.100 2011/07/10 23:21:59 matt Exp $	*/
+/*	$NetBSD: locore_mips3.S,v 1.101 2011/07/31 15:39:29 matt Exp $	*/
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -141,26 +141,27 @@
  *	Return when the write buffer is empty.
+ *
  *	Common for all MIPS3 and greater ISAs
+ *
  * Results:
  *	None.
+ *
  * Side effects:
  *	None.
+ *
  *----------------------------------------------------------------------------
  */
 LEAF(mips3_wbflush)
 XLEAF(loongson2_wbflush)
 XLEAF(mips32_wbflush)
 XLEAF(mips32r2_wbflush)
 XLEAF(mips64_wbflush)
 XLEAF(mips64r2_wbflush)
 	nop
 	sync
 	j	ra
 	 nop
 END(mips3_wbflush)
 /*
  * mips_wait_idle:

 @@ -1,14 +1,15 @@
-/*	$NetBSD: mips32_subr.S,v 1.5 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: mips32_subr.S,v 1.6 2011/07/31 15:39:29 matt Exp $	*/
 #undef MIPS1
 #undef MIPS3
 #undef MIPS3_LOONGSON2
 /* #undef MIPS32 */
 #undef MIPS32R2
 #undef MIPS64
 #undef MIPS64R2
 #undef MIPS64_SB1
 #undef MIPS64_XLP
 #undef MIPS64_XLR
 #undef MIPS64_XLS
 #include <mips/mips/mipsX_subr.S>

 @@ -1,14 +1,15 @@
-/*	$NetBSD: mips3_subr.S,v 1.5 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: mips3_subr.S,v 1.6 2011/07/31 15:39:29 matt Exp $	*/
 #undef MIPS1
 /* #undef MIPS3 */
 #undef MIPS3_LOONGSON2
 #undef MIPS32
 #undef MIPS32R2
 #undef MIPS64
 #undef MIPS64R2
 #undef MIPS64_SB1
 #undef MIPS64_XLP
 #undef MIPS64_XLR
 #undef MIPS64_XLS
 #include <mips/mips/mipsX_subr.S>

 @@ -1,14 +1,15 @@
-/*	$NetBSD: mips64_subr.S,v 1.5 2011/03/15 07:39:22 matt Exp $	*/
+/*	$NetBSD: mips64_subr.S,v 1.6 2011/07/31 15:39:29 matt Exp $	*/
 #undef MIPS1
 #undef MIPS3
 #undef MIPS3_LOONGSON2
 #undef MIPS32
 #undef MIPS32R2
 /* #undef MIPS64 */
 #undef MIPS64R2
 #undef MIPS64_SB1
 #undef MIPS64_XLP
 #undef MIPS64_XLR
 #undef MIPS64_XLS
 #include <mips/mips/mipsX_subr.S>