 @@ -1,14 +1,14 @@
-/*      $NetBSD: amdtemp.c,v 1.11 2011/06/15 03:30:15 jruoho Exp $ */
+/*      $NetBSD: amdtemp.c,v 1.12 2011/07/31 22:04:07 jmcneill Exp $ */
 /*      $OpenBSD: kate.c,v 1.2 2008/03/27 04:52:03 cnst Exp $   */
 /*
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Christoph Egger.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -38,27 +38,27 @@
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.11 2011/06/15 03:30:15 jruoho Exp $ ");
+__KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v 1.12 2011/07/31 22:04:07 jmcneill Exp $ ");
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kmem.h>
 #include <sys/module.h>
 #include <machine/specialreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 @@ -71,52 +71,52 @@ __KERNEL_RCSID(0, "$NetBSD: amdtemp.c,v
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
  * AMD K8 Errata: #141
  * http://support.amd.com/us/Processor_TechDocs/33610_PUB_Rev3%2042v3.pdf
+ *
  * Family10h:
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/31116.PDF
  * Family10h Errata: #319
  * http://support.amd.com/de/Processor_TechDocs/41322.pdf
+ *
  * Family11h:
  * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/41256.pdf
  */
-/* AMD Proessors, Function 3 -- Miscellaneous Control
+/* AMD Processors, Function 3 -- Miscellaneous Control
  */
 /* Function 3 Registers */
 #define THERMTRIP_STAT_R      0xe4
 #define NORTHBRIDGE_CAP_R     0xe8
 #define CPUID_FAMILY_MODEL_R  0xfc
 /*
  * AMD NPT Family 0Fh Processors, Function 3 -- Miscellaneous Control
  */
 /* Bits within Thermtrip Status Register */
 #define K8_THERM_SENSE_SEL       (1 << 6)
 #define K8_THERM_SENSE_CORE_SEL  (1 << 2)
 /* Flip core and sensor selection bits */
 #define K8_T_SEL_C0(v)           (v |= K8_THERM_SENSE_CORE_SEL)
 #define K8_T_SEL_C1(v)           (v &= ~(K8_THERM_SENSE_CORE_SEL))
 #define K8_T_SEL_S0(v)           (v &= ~(K8_THERM_SENSE_SEL))
 #define K8_T_SEL_S1(v)           (v |= K8_THERM_SENSE_SEL)
 /*
- * AMD Family 10h Processorcs, Function 3 -- Miscellaneous Control
+ * AMD Family 10h Processors, Function 3 -- Miscellaneous Control
  */
 /* Function 3 Registers */
 #define F10_TEMPERATURE_CTL_R	0xa4
 /* Bits within Reported Temperature Control Register */
 #define F10_TEMP_CURTEMP	(1 << 21)
 /*
  * Revision Guide for AMD NPT Family 0Fh Processors,
  * Publication # 33610, Revision 3.30, February 2008
  */
 #define K8_SOCKET_F	1	/* Server */
 @@ -186,26 +186,27 @@ static int
 amdtemp_match(device_t parent, cfdata_t match, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	pcireg_t cpu_signature;
 	uint32_t family;
 	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_AMD)
 		return 0;
 	switch (PCI_PRODUCT(pa->pa_id)) {
 	case PCI_PRODUCT_AMD_AMD64_MISC:
 	case PCI_PRODUCT_AMD_AMD64_F10_MISC:
 	case PCI_PRODUCT_AMD_AMD64_F11_MISC:
 	case PCI_PRODUCT_AMD_F14_NB:
 		break;
 	default:
 		return 0;
+	}
 	cpu_signature = pci_conf_read(pa->pa_pc,
 	    pa->pa_tag, CPUID_FAMILY_MODEL_R);
 	/* This CPUID northbridge register has been introduced
 	 * in Revision F */
 	if (cpu_signature == 0x0)
 		return 0;
 @@ -214,27 +215,27 @@ amdtemp_match(device_t parent, cfdata_t
 		family += CPUID2EXTFAMILY(cpu_signature);
 	/* Errata #319: This has been fixed in Revision C2. */
 	if (family == 0x10) {
 		if (CPUID2MODEL(cpu_signature) < 4)
 			return 0;
 		if (CPUID2MODEL(cpu_signature) == 4
 		    && CPUID2STEPPING(cpu_signature) < 2)
 			return 0;
+	}
 	/* Not yet supported CPUs */
-	if (family >= 0x12)
+	if (family > 0x14)
 		return 0;
 	return 2;	/* supercede pchb(4) */
+}
 static void
 amdtemp_attach(device_t parent, device_t self, void *aux)
+{
 	struct amdtemp_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	pcireg_t cpu_signature;
 	int error;
 	uint8_t i;
 @@ -257,26 +258,27 @@ amdtemp_attach(device_t parent, device_t
 	sc->sc_sensor = NULL;
 	sc->sc_pc = pa->pa_pc;
 	sc->sc_pcitag = pa->pa_tag;
 	sc->sc_adjustment = 0;
 	switch (sc->sc_family) {
 	case 0xf:  /* AMD K8 NPT */
 		amdtemp_k8_init(sc, cpu_signature);
 		break;
 	case 0x10: /* AMD Barcelona/Phenom */
 	case 0x11: /* AMD Griffin */
 	case 0x14: /* AMD Fusion */
 		amdtemp_family10_init(sc);
 		break;
 	default:
 		aprint_normal(", family 0x%x not supported\n",
 			     sc->sc_family);
 		return;
+	}
 	aprint_normal("\n");
 	if (sc->sc_adjustment != 0)
 		aprint_debug_dev(self, "Workaround enabled\n");
 @@ -284,51 +286,53 @@ amdtemp_attach(device_t parent, device_t
 	sc->sc_sme = sysmon_envsys_create();
 	sc->sc_sensor_len = sizeof(envsys_data_t) * sc->sc_numsensors;
 	sc->sc_sensor = kmem_zalloc(sc->sc_sensor_len, KM_SLEEP);
 	if (sc->sc_sensor == NULL)
 		goto bad;
 	switch (sc->sc_family) {
 	case 0xf:
 		amdtemp_k8_setup_sensors(sc, device_unit(self));
 		break;
 	case 0x10:
 	case 0x11:
 	case 0x14:
 		amdtemp_family10_setup_sensors(sc, device_unit(self));
 		break;
+	}
 	/*
 	 * Set properties in sensors.
 	 */
 	for (i = 0; i < sc->sc_numsensors; i++) {
 		if (sysmon_envsys_sensor_attach(sc->sc_sme,
 						&sc->sc_sensor[i]))
 			goto bad;
+	}
 	/*
 	 * Register the sysmon_envsys device.
 	 */
 	sc->sc_sme->sme_name = device_xname(self);
 	sc->sc_sme->sme_cookie = sc;
 	switch (sc->sc_family) {
 	case 0xf:
 		sc->sc_sme->sme_refresh = amdtemp_k8_refresh;
 		break;
 	case 0x10:
 	case 0x11:
 	case 0x14:
 		sc->sc_sme->sme_refresh = amdtemp_family10_refresh;
 		break;
+	}
 	error = sysmon_envsys_register(sc->sc_sme);
 	if (error) {
 		aprint_error_dev(self, "unable to register with sysmon "
 			"(error=%d)\n", error);
 		goto bad;
+	}
 	(void)pmf_device_register(self, NULL, NULL);
 @@ -471,46 +475,46 @@ amdtemp_k8_refresh(struct sysmon_envsys
 	edata->state = ENVSYS_SINVALID;
 	if ((tmp == match) && ((value & ~0x3) != 0)) {
 		edata->state = ENVSYS_SVALID;
 		edata->value_cur = (value * 250000 - 49000000) + 273150000
 			+ sc->sc_adjustment;
+	}
+}
 static void
 amdtemp_family10_init(struct amdtemp_softc *sc)
+{
-	aprint_normal(" (Family10h / Family11h)");
+	aprint_normal(" (Family%02xh)", sc->sc_family);
 	sc->sc_numsensors = 1;
+}
 static void
 amdtemp_family10_setup_sensors(struct amdtemp_softc *sc, int dv_unit)
+{
 	/* sanity check for future enhancements */
 	KASSERT(sc->sc_numsensors == 1);
 	/* There's one sensor per memory controller (= socket)
 	 * so we use the device unit as socket counter
 	 * to correctly enumerate the CPUs
 	 */
 	sc->sc_sensor[0].units = ENVSYS_STEMP;
 	sc->sc_sensor[0].state = ENVSYS_SVALID;
 	snprintf(sc->sc_sensor[0].desc, sizeof(sc->sc_sensor[0].desc),
-		"CPU%u Sensor0", dv_unit);
+		"cpu%u temperature", dv_unit);
+}
 static void
 amdtemp_family10_refresh(struct sysmon_envsys *sme, envsys_data_t *edata)
+{
 	struct amdtemp_softc *sc = sme->sme_cookie;
 	pcireg_t status;
 	uint32_t value;
 	status = pci_conf_read(sc->sc_pc,
 	    sc->sc_pcitag, F10_TEMPERATURE_CTL_R);