Mon Aug 1 10:42:24 2011 UTC ()
if checking whether an interrupt is shared, don't compare pin numbers
if it is "-1" -- this is a hack to allow MSIs which don't have a concept
of pin numbers, and are generally not shared
(This doesn't give us sensible event names for statistics display. The
whole abstraction has more exceptions than regular cases, it should
be redesigned imho.)


(drochner)
diff -r1.42 -r1.43 src/sys/arch/x86/include/intr.h
diff -r1.71 -r1.72 src/sys/arch/x86/x86/intr.c
cvs diff -r1.42 -r1.43 src/sys/arch/x86/include/intr.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/intr.h 2011/04/03 22:29:27 1.42
+++ src/sys/arch/x86/include/intr.h 2011/08/01 10:42:23 1.43
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: intr.h,v 1.42 2011/04/03 22:29:27 dyoung Exp $ */ 1/* $NetBSD: intr.h,v 1.43 2011/08/01 10:42:23 drochner Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc. 4 * Copyright (c) 1998, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, and by Jason R. Thorpe. 8 * by Charles M. Hannum, and by Jason R. Thorpe.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -63,27 +63,28 @@ @@ -63,27 +63,28 @@
63 * (32), instead of 32 per CPU. It also would mean that having multiple 63 * (32), instead of 32 per CPU. It also would mean that having multiple
64 * IO APICs which deliver interrupts from an equal pin number would 64 * IO APICs which deliver interrupts from an equal pin number would
65 * overlap if they were to be sent to the same CPU. 65 * overlap if they were to be sent to the same CPU.
66 */ 66 */
67 67
68struct intrstub { 68struct intrstub {
69 void *ist_entry; 69 void *ist_entry;
70 void *ist_recurse;  70 void *ist_recurse;
71 void *ist_resume; 71 void *ist_resume;
72}; 72};
73 73
74struct intrsource { 74struct intrsource {
75 int is_maxlevel; /* max. IPL for this source */ 75 int is_maxlevel; /* max. IPL for this source */
76 int is_pin; /* IRQ for legacy; pin for IO APIC */ 76 int is_pin; /* IRQ for legacy; pin for IO APIC,
 77 -1 for MSI */
77 struct intrhand *is_handlers; /* handler chain */ 78 struct intrhand *is_handlers; /* handler chain */
78 struct pic *is_pic; /* originating PIC */ 79 struct pic *is_pic; /* originating PIC */
79 void *is_recurse; /* entry for spllower */ 80 void *is_recurse; /* entry for spllower */
80 void *is_resume; /* entry for doreti */ 81 void *is_resume; /* entry for doreti */
81 lwp_t *is_lwp; /* for soft interrupts */ 82 lwp_t *is_lwp; /* for soft interrupts */
82 struct evcnt is_evcnt; /* interrupt counter */ 83 struct evcnt is_evcnt; /* interrupt counter */
83 int is_flags; /* see below */ 84 int is_flags; /* see below */
84 int is_type; /* level, edge */ 85 int is_type; /* level, edge */
85 int is_idtvec; 86 int is_idtvec;
86 int is_minlevel; 87 int is_minlevel;
87 char is_evname[32]; /* event counter name */ 88 char is_evname[32]; /* event counter name */
88}; 89};
89 90
cvs diff -r1.71 -r1.72 src/sys/arch/x86/x86/intr.c (expand / switch to unified diff)

--- src/sys/arch/x86/x86/intr.c 2011/04/03 22:29:27 1.71
+++ src/sys/arch/x86/x86/intr.c 2011/08/01 10:42:24 1.72
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: intr.c,v 1.71 2011/04/03 22:29:27 dyoung Exp $ */ 1/* $NetBSD: intr.c,v 1.72 2011/08/01 10:42:24 drochner Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc. 4 * Copyright (c) 2007, 2008, 2009 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran. 8 * by Andrew Doran.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -123,27 +123,27 @@ @@ -123,27 +123,27 @@
123 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 123 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
124 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 124 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
125 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 125 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
126 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 126 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
127 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 127 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
128 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 128 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
129 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 129 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
130 * SUCH DAMAGE. 130 * SUCH DAMAGE.
131 * 131 *
132 * @(#)isa.c 7.2 (Berkeley) 5/13/91 132 * @(#)isa.c 7.2 (Berkeley) 5/13/91
133 */ 133 */
134 134
135#include <sys/cdefs.h> 135#include <sys/cdefs.h>
136__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.71 2011/04/03 22:29:27 dyoung Exp $"); 136__KERNEL_RCSID(0, "$NetBSD: intr.c,v 1.72 2011/08/01 10:42:24 drochner Exp $");
137 137
138#include "opt_intrdebug.h" 138#include "opt_intrdebug.h"
139#include "opt_multiprocessor.h" 139#include "opt_multiprocessor.h"
140#include "opt_acpi.h" 140#include "opt_acpi.h"
141 141
142#include <sys/param.h> 142#include <sys/param.h>
143#include <sys/systm.h> 143#include <sys/systm.h>
144#include <sys/kernel.h> 144#include <sys/kernel.h>
145#include <sys/syslog.h> 145#include <sys/syslog.h>
146#include <sys/device.h> 146#include <sys/device.h>
147#include <sys/kmem.h> 147#include <sys/kmem.h>
148#include <sys/proc.h> 148#include <sys/proc.h>
149#include <sys/errno.h> 149#include <sys/errno.h>
@@ -470,27 +470,28 @@ intr_allocate_slot(struct pic *pic, int  @@ -470,27 +470,28 @@ intr_allocate_slot(struct pic *pic, int
470 CPU_INFO_ITERATOR cii; 470 CPU_INFO_ITERATOR cii;
471 struct cpu_info *ci, *lci; 471 struct cpu_info *ci, *lci;
472 struct intrsource *isp; 472 struct intrsource *isp;
473 int slot = 0, idtvec, error; 473 int slot = 0, idtvec, error;
474 474
475 KASSERT(mutex_owned(&cpu_lock)); 475 KASSERT(mutex_owned(&cpu_lock));
476 476
477 /* First check if this pin is already used by an interrupt vector. */ 477 /* First check if this pin is already used by an interrupt vector. */
478 for (CPU_INFO_FOREACH(cii, ci)) { 478 for (CPU_INFO_FOREACH(cii, ci)) {
479 for (slot = 0 ; slot < MAX_INTR_SOURCES ; slot++) { 479 for (slot = 0 ; slot < MAX_INTR_SOURCES ; slot++) {
480 if ((isp = ci->ci_isources[slot]) == NULL) { 480 if ((isp = ci->ci_isources[slot]) == NULL) {
481 continue; 481 continue;
482 } 482 }
483 if (isp->is_pic == pic && isp->is_pin == pin) { 483 if (isp->is_pic == pic &&
 484 pin != -1 && isp->is_pin == pin) {
484 *idt_slot = isp->is_idtvec; 485 *idt_slot = isp->is_idtvec;
485 *index = slot; 486 *index = slot;
486 *cip = ci; 487 *cip = ci;
487 return 0; 488 return 0;
488 } 489 }
489 } 490 }
490 } 491 }
491 492
492 /* 493 /*
493 * The pic/pin combination doesn't have an existing mapping. 494 * The pic/pin combination doesn't have an existing mapping.
494 * Find a slot for a new interrupt source. For the i8259 case, 495 * Find a slot for a new interrupt source. For the i8259 case,
495 * we always use reserved slots of the primary CPU. Otherwise, 496 * we always use reserved slots of the primary CPU. Otherwise,
496 * we make an attempt to balance the interrupt load. 497 * we make an attempt to balance the interrupt load.