| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
| 1 | /* $NetBSD: ralink_eth.c,v 1.4 2011/08/03 17:34:27 matt Exp $ */ | | 1 | /* $NetBSD: ralink_eth.c,v 1.5 2011/08/23 08:10:08 oki Exp $ */ |
| 2 | /*- | | 2 | /*- |
| 3 | * Copyright (c) 2011 CradlePoint Technology, Inc. | | 3 | * Copyright (c) 2011 CradlePoint Technology, Inc. |
| 4 | * All rights reserved. | | 4 | * All rights reserved. |
| 5 | * | | 5 | * |
| 6 | * | | 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without | | 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions | | 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: | | 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright | | 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. | | 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright | | 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the | | 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. | | 14 | * documentation and/or other materials provided with the distribution. |
| @@ -19,27 +19,27 @@ | | | @@ -19,27 +19,27 @@ |
| 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS | | 19 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 23 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 24 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 25 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 26 | * POSSIBILITY OF SUCH DAMAGE. | | 26 | * POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ | | 27 | */ |
| 28 | | | 28 | |
| 29 | /* ralink_eth.c -- Ralink Ethernet Driver */ | | 29 | /* ralink_eth.c -- Ralink Ethernet Driver */ |
| 30 | | | 30 | |
| 31 | #include <sys/cdefs.h> | | 31 | #include <sys/cdefs.h> |
| 32 | __KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.4 2011/08/03 17:34:27 matt Exp $"); | | 32 | __KERNEL_RCSID(0, "$NetBSD: ralink_eth.c,v 1.5 2011/08/23 08:10:08 oki Exp $"); |
| 33 | | | 33 | |
| 34 | #include <sys/param.h> | | 34 | #include <sys/param.h> |
| 35 | #include <sys/bus.h> | | 35 | #include <sys/bus.h> |
| 36 | #include <sys/callout.h> | | 36 | #include <sys/callout.h> |
| 37 | #include <sys/device.h> | | 37 | #include <sys/device.h> |
| 38 | #include <sys/endian.h> | | 38 | #include <sys/endian.h> |
| 39 | #include <sys/errno.h> | | 39 | #include <sys/errno.h> |
| 40 | #include <sys/ioctl.h> | | 40 | #include <sys/ioctl.h> |
| 41 | #include <sys/intr.h> | | 41 | #include <sys/intr.h> |
| 42 | #include <sys/kernel.h> | | 42 | #include <sys/kernel.h> |
| 43 | #include <sys/malloc.h> | | 43 | #include <sys/malloc.h> |
| 44 | #include <sys/mbuf.h> | | 44 | #include <sys/mbuf.h> |
| 45 | #include <sys/socket.h> | | 45 | #include <sys/socket.h> |
| @@ -724,27 +724,27 @@ ralink_eth_hw_init(ralink_eth_softc_t *s | | | @@ -724,27 +724,27 @@ ralink_eth_hw_init(ralink_eth_softc_t *s |
| 724 | RALINK_DEBUG_FUNC_ENTRY(); | | 724 | RALINK_DEBUG_FUNC_ENTRY(); |
| 725 | struct ralink_eth_txstate *txs; | | 725 | struct ralink_eth_txstate *txs; |
| 726 | uint32_t r; | | 726 | uint32_t r; |
| 727 | int i; | | 727 | int i; |
| 728 | | | 728 | |
| 729 | /* reset to a known good state */ | | 729 | /* reset to a known good state */ |
| 730 | ralink_eth_reset(sc); | | 730 | ralink_eth_reset(sc); |
| 731 | | | 731 | |
| 732 | #if defined(RT3050) || defined(RT3052) | | 732 | #if defined(RT3050) || defined(RT3052) |
| 733 | /* Bring the switch to a sane default state (from linux driver) */ | | 733 | /* Bring the switch to a sane default state (from linux driver) */ |
| 734 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SGC2, | | 734 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SGC2, |
| 735 | 0x00000000); | | 735 | 0x00000000); |
| 736 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PFC1, | | 736 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PFC1, |
| 737 | 0x00405555); /* check VLAN tag on port forward */); | | 737 | 0x00405555); /* check VLAN tag on port forward */ |
| 738 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VLANI0, | | 738 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VLANI0, |
| 739 | 0x00002001); | | 739 | 0x00002001); |
| 740 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC0, | | 740 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC0, |
| 741 | 0x00001002); | | 741 | 0x00001002); |
| 742 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC1, | | 742 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC1, |
| 743 | 0x00001001); | | 743 | 0x00001001); |
| 744 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC2, | | 744 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_PVIDC2, |
| 745 | 0x00001001); | | 745 | 0x00001001); |
| 746 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0, | | 746 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_VMSC0, |
| 747 | 0xffff417e); | | 747 | 0xffff417e); |
| 748 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0, | | 748 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC0, |
| 749 | 0x00007f7f); | | 749 | 0x00007f7f); |
| 750 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2, | | 750 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_POC2, |
| @@ -754,58 +754,58 @@ ralink_eth_hw_init(ralink_eth_softc_t *s | | | @@ -754,58 +754,58 @@ ralink_eth_hw_init(ralink_eth_softc_t *s |
| 754 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SWGC, | | 754 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SWGC, |
| 755 | 0x0008a301); /* hashing algorithm=XOR48 */ | | 755 | 0x0008a301); /* hashing algorithm=XOR48 */ |
| 756 | /* aging interval=300sec */ | | 756 | /* aging interval=300sec */ |
| 757 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SOCPC, | | 757 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_SOCPC, |
| 758 | 0x02404040); | | 758 | 0x02404040); |
| 759 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPORT, | | 759 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPORT, |
| 760 | 0x3f502b28); /* Change polling Ext PHY Addr=0x0 */ | | 760 | 0x3f502b28); /* Change polling Ext PHY Addr=0x0 */ |
| 761 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPA, | | 761 | bus_space_write_4(sc->sc_memt, sc->sc_sw_memh, RA_ETH_SW_FPA, |
| 762 | 0x00000000); | | 762 | 0x00000000); |
| 763 | | | 763 | |
| 764 | /* do some mii magic TODO: define these registers/bits */ | | 764 | /* do some mii magic TODO: define these registers/bits */ |
| 765 | /* lower down PHY 10Mbps mode power */ | | 765 | /* lower down PHY 10Mbps mode power */ |
| 766 | /* select local register */ | | 766 | /* select local register */ |
| 767 | ralink_eth_mii_write(&sc->sc_dev, 0, 31, 0x8000); | | 767 | ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x8000); |
| 768 | | | 768 | |
| 769 | for (i=0;i<5;i++){ | | 769 | for (i=0;i<5;i++){ |
| 770 | /* set TX10 waveform coefficient */ | | 770 | /* set TX10 waveform coefficient */ |
| 771 | ralink_eth_mii_write(&sc->sc_dev, i, 26, 0x1601); | | 771 | ralink_eth_mii_write(sc->sc_dev, i, 26, 0x1601); |
| 772 | | | 772 | |
| 773 | /* set TX100/TX10 AD/DA current bias */ | | 773 | /* set TX100/TX10 AD/DA current bias */ |
| 774 | ralink_eth_mii_write(&sc->sc_dev, i, 29, 0x7058); | | 774 | ralink_eth_mii_write(sc->sc_dev, i, 29, 0x7058); |
| 775 | | | 775 | |
| 776 | /* set TX100 slew rate control */ | | 776 | /* set TX100 slew rate control */ |
| 777 | ralink_eth_mii_write(&sc->sc_dev, i, 30, 0x0018); | | 777 | ralink_eth_mii_write(sc->sc_dev, i, 30, 0x0018); |
| 778 | } | | 778 | } |
| 779 | | | 779 | |
| 780 | /* PHY IOT */ | | 780 | /* PHY IOT */ |
| 781 | | | 781 | |
| 782 | /* select global register */ | | 782 | /* select global register */ |
| 783 | ralink_eth_mii_write(&sc->sc_dev, 0, 31, 0x0); | | 783 | ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x0); |
| 784 | | | 784 | |
| 785 | /* tune TP_IDL tail and head waveform */ | | 785 | /* tune TP_IDL tail and head waveform */ |
| 786 | ralink_eth_mii_write(&sc->sc_dev, 0, 22, 0x052f); | | 786 | ralink_eth_mii_write(sc->sc_dev, 0, 22, 0x052f); |
| 787 | | | 787 | |
| 788 | /* set TX10 signal amplitude threshold to minimum */ | | 788 | /* set TX10 signal amplitude threshold to minimum */ |
| 789 | ralink_eth_mii_write(&sc->sc_dev, 0, 17, 0x0fe0); | | 789 | ralink_eth_mii_write(sc->sc_dev, 0, 17, 0x0fe0); |
| 790 | | | 790 | |
| 791 | /* set squelch amplitude to higher threshold */ | | 791 | /* set squelch amplitude to higher threshold */ |
| 792 | ralink_eth_mii_write(&sc->sc_dev, 0, 18, 0x40ba); | | 792 | ralink_eth_mii_write(sc->sc_dev, 0, 18, 0x40ba); |
| 793 | | | 793 | |
| 794 | /* longer TP_IDL tail length */ | | 794 | /* longer TP_IDL tail length */ |
| 795 | ralink_eth_mii_write(&sc->sc_dev, 0, 14, 0x65); | | 795 | ralink_eth_mii_write(sc->sc_dev, 0, 14, 0x65); |
| 796 | | | 796 | |
| 797 | /* select local register */ | | 797 | /* select local register */ |
| 798 | ralink_eth_mii_write(&sc->sc_dev, 0, 31, 0x8000); | | 798 | ralink_eth_mii_write(sc->sc_dev, 0, 31, 0x8000); |
| 799 | #else | | 799 | #else |
| 800 | /* GE1 + GigSW */ | | 800 | /* GE1 + GigSW */ |
| 801 | fe_write(sc, RA_FE_MDIO_CFG1, | | 801 | fe_write(sc, RA_FE_MDIO_CFG1, |
| 802 | MDIO_CFG_PHY_ADDR(0x1f) | | | 802 | MDIO_CFG_PHY_ADDR(0x1f) | |
| 803 | MDIO_CFG_BP_EN | | | 803 | MDIO_CFG_BP_EN | |
| 804 | MDIO_CFG_FORCE_CFG | | | 804 | MDIO_CFG_FORCE_CFG | |
| 805 | MDIO_CFG_SPEED(MDIO_CFG_SPEED_1000M) | | | 805 | MDIO_CFG_SPEED(MDIO_CFG_SPEED_1000M) | |
| 806 | MDIO_CFG_FULL_DUPLEX | | | 806 | MDIO_CFG_FULL_DUPLEX | |
| 807 | MDIO_CFG_FC_TX | | | 807 | MDIO_CFG_FC_TX | |
| 808 | MDIO_CFG_FC_RX | | | 808 | MDIO_CFG_FC_RX | |
| 809 | MDIO_CFG_TX_CLK_MODE(MDIO_CFG_TX_CLK_MODE_3COM)); | | 809 | MDIO_CFG_TX_CLK_MODE(MDIO_CFG_TX_CLK_MODE_3COM)); |
| 810 | #endif | | 810 | #endif |
| 811 | | | 811 | |
| @@ -1561,27 +1561,27 @@ ralink_eth_txintr(ralink_eth_softc_t *sc | | | @@ -1561,27 +1561,27 @@ ralink_eth_txintr(ralink_eth_softc_t *sc |
| 1561 | * ralink_eth_mdio_enable | | 1561 | * ralink_eth_mdio_enable |
| 1562 | */ | | 1562 | */ |
| 1563 | #if defined (RT3050) || defined(RT3052) | | 1563 | #if defined (RT3050) || defined(RT3052) |
| 1564 | static void | | 1564 | static void |
| 1565 | ralink_eth_mdio_enable(ralink_eth_softc_t *sc, bool enable) | | 1565 | ralink_eth_mdio_enable(ralink_eth_softc_t *sc, bool enable) |
| 1566 | { | | 1566 | { |
| 1567 | uint32_t data = sy_read(sc, RA_SYSCTL_GPIOMODE); | | 1567 | uint32_t data = sy_read(sc, RA_SYSCTL_GPIOMODE); |
| 1568 | | | 1568 | |
| 1569 | if (enable) | | 1569 | if (enable) |
| 1570 | data &= ~GPIOMODE_MDIO; | | 1570 | data &= ~GPIOMODE_MDIO; |
| 1571 | else | | 1571 | else |
| 1572 | data |= GPIOMODE_MDIO; | | 1572 | data |= GPIOMODE_MDIO; |
| 1573 | | | 1573 | |
| 1574 | sy_write(sc, RA__GPIOMODE, data); | | 1574 | sy_write(sc, RA_SYSCTL_GPIOMODE, data); |
| 1575 | } | | 1575 | } |
| 1576 | #else | | 1576 | #else |
| 1577 | #define ralink_eth_mdio_enable(sc, enable) | | 1577 | #define ralink_eth_mdio_enable(sc, enable) |
| 1578 | #endif | | 1578 | #endif |
| 1579 | | | 1579 | |
| 1580 | /* | | 1580 | /* |
| 1581 | * ralink_eth_mii_statchg | | 1581 | * ralink_eth_mii_statchg |
| 1582 | */ | | 1582 | */ |
| 1583 | static void | | 1583 | static void |
| 1584 | ralink_eth_mii_statchg(device_t self) | | 1584 | ralink_eth_mii_statchg(device_t self) |
| 1585 | { | | 1585 | { |
| 1586 | #if 0 | | 1586 | #if 0 |
| 1587 | ralink_eth_softc_t * const sc = device_private(self); | | 1587 | ralink_eth_softc_t * const sc = device_private(self); |
| @@ -1602,27 +1602,27 @@ ralink_eth_mii_tick(void *arg) | | | @@ -1602,27 +1602,27 @@ ralink_eth_mii_tick(void *arg) |
| 1602 | const int s = splnet(); | | 1602 | const int s = splnet(); |
| 1603 | mii_tick(&sc->sc_mii); | | 1603 | mii_tick(&sc->sc_mii); |
| 1604 | splx(s); | | 1604 | splx(s); |
| 1605 | | | 1605 | |
| 1606 | callout_reset(&sc->sc_tick_callout, hz, ralink_eth_mii_tick, sc); | | 1606 | callout_reset(&sc->sc_tick_callout, hz, ralink_eth_mii_tick, sc); |
| 1607 | } | | 1607 | } |
| 1608 | | | 1608 | |
| 1609 | /* | | 1609 | /* |
| 1610 | * ralink_eth_mii_read | | 1610 | * ralink_eth_mii_read |
| 1611 | */ | | 1611 | */ |
| 1612 | static int | | 1612 | static int |
| 1613 | ralink_eth_mii_read(device_t self, int phy_addr, int phy_reg) | | 1613 | ralink_eth_mii_read(device_t self, int phy_addr, int phy_reg) |
| 1614 | { | | 1614 | { |
| 1615 | const ralink_eth_softc_t *sc = device_private(self); | | 1615 | ralink_eth_softc_t *sc = device_private(self); |
| 1616 | KASSERT(sc != NULL); | | 1616 | KASSERT(sc != NULL); |
| 1617 | #if 0 | | 1617 | #if 0 |
| 1618 | printf("%s() phy_addr: %d phy_reg: %d\n", __func__, phy_addr, phy_reg); | | 1618 | printf("%s() phy_addr: %d phy_reg: %d\n", __func__, phy_addr, phy_reg); |
| 1619 | #endif | | 1619 | #endif |
| 1620 | #if defined(RT3050) || defined(RT3052) | | 1620 | #if defined(RT3050) || defined(RT3052) |
| 1621 | if (phy_addr > 5) | | 1621 | if (phy_addr > 5) |
| 1622 | return 0; | | 1622 | return 0; |
| 1623 | #endif | | 1623 | #endif |
| 1624 | | | 1624 | |
| 1625 | /* We enable mdio gpio purpose register, and disable it when exit. */ | | 1625 | /* We enable mdio gpio purpose register, and disable it when exit. */ |
| 1626 | ralink_eth_mdio_enable(sc, true); | | 1626 | ralink_eth_mdio_enable(sc, true); |
| 1627 | | | 1627 | |
| 1628 | /* | | 1628 | /* |
| @@ -1632,27 +1632,27 @@ ralink_eth_mii_read(device_t self, int p | | | @@ -1632,27 +1632,27 @@ ralink_eth_mii_read(device_t self, int p |
| 1632 | for (;;) { | | 1632 | for (;;) { |
| 1633 | /* rd_rdy: read operation is complete */ | | 1633 | /* rd_rdy: read operation is complete */ |
| 1634 | #if defined(RT3050) || defined(RT3052) | | 1634 | #if defined(RT3050) || defined(RT3052) |
| 1635 | if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0) | | 1635 | if ((sw_read(sc, RA_ETH_SW_PCTL1) & PCTL1_RD_DONE) == 0) |
| 1636 | break; | | 1636 | break; |
| 1637 | #else | | 1637 | #else |
| 1638 | if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) | | 1638 | if ((fe_read(sc, RA_FE_MDIO_ACCESS) & MDIO_ACCESS_TRG) == 0) |
| 1639 | break; | | 1639 | break; |
| 1640 | #endif | | 1640 | #endif |
| 1641 | } | | 1641 | } |
| 1642 | | | 1642 | |
| 1643 | #if defined(RT3050) || defined(RT3052) | | 1643 | #if defined(RT3050) || defined(RT3052) |
| 1644 | sw_write(sc, RA_ETH_SW_PCTL0, | | 1644 | sw_write(sc, RA_ETH_SW_PCTL0, |
| 1645 | PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr); | | 1645 | PCTL0_RD_CMD | PCTL0_REG(phy_reg) | PCTL0_ADDR(phy_addr)); |
| 1646 | #else | | 1646 | #else |
| 1647 | fe_write(sc, RA_FE_MDIO_ACCESS, | | 1647 | fe_write(sc, RA_FE_MDIO_ACCESS, |
| 1648 | MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg)); | | 1648 | MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg)); |
| 1649 | fe_write(sc, RA_FE_MDIO_ACCESS, | | 1649 | fe_write(sc, RA_FE_MDIO_ACCESS, |
| 1650 | MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) | | | 1650 | MDIO_ACCESS_PHY_ADDR(phy_addr) | MDIO_ACCESS_REG(phy_reg) | |
| 1651 | MDIO_ACCESS_TRG); | | 1651 | MDIO_ACCESS_TRG); |
| 1652 | #endif | | 1652 | #endif |
| 1653 | | | 1653 | |
| 1654 | /* | | 1654 | /* |
| 1655 | * make sure read operation is complete | | 1655 | * make sure read operation is complete |
| 1656 | * TODO: timeout (linux uses jiffies to measure 5 seconds) | | 1656 | * TODO: timeout (linux uses jiffies to measure 5 seconds) |
| 1657 | */ | | 1657 | */ |
| 1658 | for (;;) { | | 1658 | for (;;) { |
| @@ -1670,27 +1670,27 @@ ralink_eth_mii_read(device_t self, int p | | | @@ -1670,27 +1670,27 @@ ralink_eth_mii_read(device_t self, int p |
| 1670 | ralink_eth_mdio_enable(sc, false); | | 1670 | ralink_eth_mdio_enable(sc, false); |
| 1671 | return data; | | 1671 | return data; |
| 1672 | } | | 1672 | } |
| 1673 | #endif | | 1673 | #endif |
| 1674 | } | | 1674 | } |
| 1675 | } | | 1675 | } |
| 1676 | | | 1676 | |
| 1677 | /* | | 1677 | /* |
| 1678 | * ralink_eth_mii_write | | 1678 | * ralink_eth_mii_write |
| 1679 | */ | | 1679 | */ |
| 1680 | static void | | 1680 | static void |
| 1681 | ralink_eth_mii_write(device_t self, int phy_addr, int phy_reg, int val) | | 1681 | ralink_eth_mii_write(device_t self, int phy_addr, int phy_reg, int val) |
| 1682 | { | | 1682 | { |
| 1683 | const ralink_eth_softc_t *sc = device_private(self); | | 1683 | ralink_eth_softc_t *sc = device_private(self); |
| 1684 | KASSERT(sc != NULL); | | 1684 | KASSERT(sc != NULL); |
| 1685 | #if 0 | | 1685 | #if 0 |
| 1686 | printf("%s() phy_addr: %d phy_reg: %d val: 0x%04x\n", | | 1686 | printf("%s() phy_addr: %d phy_reg: %d val: 0x%04x\n", |
| 1687 | __func__, phy_addr, phy_reg, val); | | 1687 | __func__, phy_addr, phy_reg, val); |
| 1688 | #endif | | 1688 | #endif |
| 1689 | ralink_eth_mdio_enable(sc, true); | | 1689 | ralink_eth_mdio_enable(sc, true); |
| 1690 | | | 1690 | |
| 1691 | /* | | 1691 | /* |
| 1692 | * make sure previous write operation is complete | | 1692 | * make sure previous write operation is complete |
| 1693 | * TODO: timeout (linux uses jiffies to measure 5 seconds) | | 1693 | * TODO: timeout (linux uses jiffies to measure 5 seconds) |
| 1694 | */ | | 1694 | */ |
| 1695 | for (;;) { | | 1695 | for (;;) { |
| 1696 | #if defined(RT3050) || defined(RT3052) | | 1696 | #if defined(RT3050) || defined(RT3052) |