| @@ -1,2359 +1,2360 @@ | | | @@ -1,2359 +1,2360 @@ |
1 | /* $NetBSD: mips_machdep.c,v 1.247 2011/08/24 16:01:53 matt Exp $ */ | | 1 | /* $NetBSD: mips_machdep.c,v 1.248 2011/08/27 16:54:14 bouyer Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright 2002 Wasabi Systems, Inc. | | 4 | * Copyright 2002 Wasabi Systems, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * Written by Simon Burge for Wasabi Systems, Inc. | | 7 | * Written by Simon Burge for Wasabi Systems, Inc. |
8 | * | | 8 | * |
9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
11 | * are met: | | 11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the | | 15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. | | 16 | * documentation and/or other materials provided with the distribution. |
17 | * 3. All advertising materials mentioning features or use of this software | | 17 | * 3. All advertising materials mentioning features or use of this software |
18 | * must display the following acknowledgement: | | 18 | * must display the following acknowledgement: |
19 | * This product includes software developed for the NetBSD Project by | | 19 | * This product includes software developed for the NetBSD Project by |
20 | * Wasabi Systems, Inc. | | 20 | * Wasabi Systems, Inc. |
21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse | | 21 | * 4. The name of Wasabi Systems, Inc. may not be used to endorse |
22 | * or promote products derived from this software without specific prior | | 22 | * or promote products derived from this software without specific prior |
23 | * written permission. | | 23 | * written permission. |
24 | * | | 24 | * |
25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND | | 25 | * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND |
26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 26 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 27 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC | | 28 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC |
29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 29 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
35 | * POSSIBILITY OF SUCH DAMAGE. | | 35 | * POSSIBILITY OF SUCH DAMAGE. |
36 | */ | | 36 | */ |
37 | | | 37 | |
38 | /* | | 38 | /* |
39 | * Copyright 2000, 2001 | | 39 | * Copyright 2000, 2001 |
40 | * Broadcom Corporation. All rights reserved. | | 40 | * Broadcom Corporation. All rights reserved. |
41 | * | | 41 | * |
42 | * This software is furnished under license and may be used and copied only | | 42 | * This software is furnished under license and may be used and copied only |
43 | * in accordance with the following terms and conditions. Subject to these | | 43 | * in accordance with the following terms and conditions. Subject to these |
44 | * conditions, you may download, copy, install, use, modify and distribute | | 44 | * conditions, you may download, copy, install, use, modify and distribute |
45 | * modified or unmodified copies of this software in source and/or binary | | 45 | * modified or unmodified copies of this software in source and/or binary |
46 | * form. No title or ownership is transferred hereby. | | 46 | * form. No title or ownership is transferred hereby. |
47 | * | | 47 | * |
48 | * 1) Any source code used, modified or distributed must reproduce and | | 48 | * 1) Any source code used, modified or distributed must reproduce and |
49 | * retain this copyright notice and list of conditions as they appear in | | 49 | * retain this copyright notice and list of conditions as they appear in |
50 | * the source file. | | 50 | * the source file. |
51 | * | | 51 | * |
52 | * 2) No right is granted to use any trade name, trademark, or logo of | | 52 | * 2) No right is granted to use any trade name, trademark, or logo of |
53 | * Broadcom Corporation. The "Broadcom Corporation" name may not be | | 53 | * Broadcom Corporation. The "Broadcom Corporation" name may not be |
54 | * used to endorse or promote products derived from this software | | 54 | * used to endorse or promote products derived from this software |
55 | * without the prior written permission of Broadcom Corporation. | | 55 | * without the prior written permission of Broadcom Corporation. |
56 | * | | 56 | * |
57 | * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED | | 57 | * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED |
58 | * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF | | 58 | * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF |
59 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR | | 59 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR |
60 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE | | 60 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE |
61 | * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE | | 61 | * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE |
62 | * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 62 | * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
63 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 63 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
64 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | | 64 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
65 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | | 65 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
66 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | | 66 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
67 | * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | | 67 | * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
68 | */ | | 68 | */ |
69 | | | 69 | |
70 | /*- | | 70 | /*- |
71 | * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. | | 71 | * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. |
72 | * All rights reserved. | | 72 | * All rights reserved. |
73 | * | | 73 | * |
74 | * This code is derived from software contributed to The NetBSD Foundation | | 74 | * This code is derived from software contributed to The NetBSD Foundation |
75 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, | | 75 | * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, |
76 | * NASA Ames Research Center and by Chris Demetriou. | | 76 | * NASA Ames Research Center and by Chris Demetriou. |
77 | * | | 77 | * |
78 | * Redistribution and use in source and binary forms, with or without | | 78 | * Redistribution and use in source and binary forms, with or without |
79 | * modification, are permitted provided that the following conditions | | 79 | * modification, are permitted provided that the following conditions |
80 | * are met: | | 80 | * are met: |
81 | * 1. Redistributions of source code must retain the above copyright | | 81 | * 1. Redistributions of source code must retain the above copyright |
82 | * notice, this list of conditions and the following disclaimer. | | 82 | * notice, this list of conditions and the following disclaimer. |
83 | * 2. Redistributions in binary form must reproduce the above copyright | | 83 | * 2. Redistributions in binary form must reproduce the above copyright |
84 | * notice, this list of conditions and the following disclaimer in the | | 84 | * notice, this list of conditions and the following disclaimer in the |
85 | * documentation and/or other materials provided with the distribution. | | 85 | * documentation and/or other materials provided with the distribution. |
86 | * | | 86 | * |
87 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 87 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
88 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 88 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
89 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 89 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
90 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 90 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
91 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 91 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
92 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 92 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
93 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 93 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
94 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 94 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
95 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 95 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
96 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 96 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
97 | * POSSIBILITY OF SUCH DAMAGE. | | 97 | * POSSIBILITY OF SUCH DAMAGE. |
98 | */ | | 98 | */ |
99 | | | 99 | |
100 | /* | | 100 | /* |
101 | * Copyright 1996 The Board of Trustees of The Leland Stanford | | 101 | * Copyright 1996 The Board of Trustees of The Leland Stanford |
102 | * Junior University. All Rights Reserved. | | 102 | * Junior University. All Rights Reserved. |
103 | * | | 103 | * |
104 | * Permission to use, copy, modify, and distribute this | | 104 | * Permission to use, copy, modify, and distribute this |
105 | * software and its documentation for any purpose and without | | 105 | * software and its documentation for any purpose and without |
106 | * fee is hereby granted, provided that the above copyright | | 106 | * fee is hereby granted, provided that the above copyright |
107 | * notice appear in all copies. Stanford University | | 107 | * notice appear in all copies. Stanford University |
108 | * makes no representations about the suitability of this | | 108 | * makes no representations about the suitability of this |
109 | * software for any purpose. It is provided "as is" without | | 109 | * software for any purpose. It is provided "as is" without |
110 | * express or implied warranty. | | 110 | * express or implied warranty. |
111 | */ | | 111 | */ |
112 | | | 112 | |
113 | #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ | | 113 | #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ |
114 | | | 114 | |
115 | __KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.247 2011/08/24 16:01:53 matt Exp $"); | | 115 | __KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.248 2011/08/27 16:54:14 bouyer Exp $"); |
116 | | | 116 | |
117 | #define __INTR_PRIVATE | | 117 | #define __INTR_PRIVATE |
118 | #include "opt_cputype.h" | | 118 | #include "opt_cputype.h" |
119 | #include "opt_compat_netbsd32.h" | | 119 | #include "opt_compat_netbsd32.h" |
120 | | | 120 | |
121 | #include <sys/param.h> | | 121 | #include <sys/param.h> |
122 | #include <sys/systm.h> | | 122 | #include <sys/systm.h> |
123 | #include <sys/proc.h> | | 123 | #include <sys/proc.h> |
124 | #include <sys/intr.h> | | 124 | #include <sys/intr.h> |
125 | #include <sys/exec.h> | | 125 | #include <sys/exec.h> |
126 | #include <sys/reboot.h> | | 126 | #include <sys/reboot.h> |
127 | #include <sys/mount.h> /* fsid_t for syscallargs */ | | 127 | #include <sys/mount.h> /* fsid_t for syscallargs */ |
128 | #include <sys/lwp.h> | | 128 | #include <sys/lwp.h> |
129 | #include <sys/sysctl.h> | | 129 | #include <sys/sysctl.h> |
130 | #include <sys/msgbuf.h> | | 130 | #include <sys/msgbuf.h> |
131 | #include <sys/conf.h> | | 131 | #include <sys/conf.h> |
132 | #include <sys/core.h> | | 132 | #include <sys/core.h> |
133 | #include <sys/device.h> | | 133 | #include <sys/device.h> |
134 | #include <sys/kcore.h> | | 134 | #include <sys/kcore.h> |
135 | #include <sys/kmem.h> | | 135 | #include <sys/kmem.h> |
136 | #include <sys/ras.h> | | 136 | #include <sys/ras.h> |
137 | #include <sys/sa.h> | | 137 | #include <sys/sa.h> |
138 | #include <sys/savar.h> | | 138 | #include <sys/savar.h> |
139 | #include <sys/cpu.h> | | 139 | #include <sys/cpu.h> |
140 | #include <sys/atomic.h> | | 140 | #include <sys/atomic.h> |
141 | #include <sys/ucontext.h> | | 141 | #include <sys/ucontext.h> |
142 | #include <sys/bitops.h> | | 142 | #include <sys/bitops.h> |
143 | | | 143 | |
144 | #include <mips/kcore.h> | | 144 | #include <mips/kcore.h> |
145 | | | 145 | |
146 | #ifdef COMPAT_NETBSD32 | | 146 | #ifdef COMPAT_NETBSD32 |
147 | #include <compat/netbsd32/netbsd32.h> | | 147 | #include <compat/netbsd32/netbsd32.h> |
148 | #endif | | 148 | #endif |
149 | | | 149 | |
150 | #include <uvm/uvm.h> | | 150 | #include <uvm/uvm.h> |
151 | | | 151 | |
152 | #include <dev/cons.h> | | 152 | #include <dev/cons.h> |
153 | #include <dev/mm.h> | | 153 | #include <dev/mm.h> |
154 | | | 154 | |
155 | #include <mips/pcb.h> | | 155 | #include <mips/pcb.h> |
156 | #include <mips/cache.h> | | 156 | #include <mips/cache.h> |
157 | #include <mips/frame.h> | | 157 | #include <mips/frame.h> |
158 | #include <mips/regnum.h> | | 158 | #include <mips/regnum.h> |
159 | #include <mips/mips_opcode.h> | | 159 | #include <mips/mips_opcode.h> |
160 | | | 160 | |
161 | #include <mips/cpu.h> | | 161 | #include <mips/cpu.h> |
162 | #include <mips/locore.h> | | 162 | #include <mips/locore.h> |
163 | #include <mips/psl.h> | | 163 | #include <mips/psl.h> |
164 | #include <mips/pte.h> | | 164 | #include <mips/pte.h> |
165 | #include <mips/userret.h> | | 165 | #include <mips/userret.h> |
166 | | | 166 | |
167 | #ifdef __HAVE_BOOTINFO_H | | 167 | #ifdef __HAVE_BOOTINFO_H |
168 | #include <machine/bootinfo.h> | | 168 | #include <machine/bootinfo.h> |
169 | #endif | | 169 | #endif |
170 | | | 170 | |
171 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 | | 171 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 |
172 | #include <mips/mipsNN.h> /* MIPS32/MIPS64 registers */ | | 172 | #include <mips/mipsNN.h> /* MIPS32/MIPS64 registers */ |
173 | | | 173 | |
174 | #define _MKINSN(a,b,c,d,e) ((uint32_t)(((a) << 26)|((b) << 21)|((c) << 16)|((d) << 11)|(e))) | | 174 | #define _MKINSN(a,b,c,d,e) ((uint32_t)(((a) << 26)|((b) << 21)|((c) << 16)|((d) << 11)|(e))) |
175 | | | 175 | |
176 | #ifdef _LP64 | | 176 | #ifdef _LP64 |
177 | #define _LOAD_V0_L_PRIVATE_A0 _MKINSN(OP_LD, _R_A0, _R_V0, 0, offsetof(lwp_t, l_private)) | | 177 | #define _LOAD_V0_L_PRIVATE_A0 _MKINSN(OP_LD, _R_A0, _R_V0, 0, offsetof(lwp_t, l_private)) |
178 | #define _MTC0_V0_USERLOCAL _MKINSN(OP_COP0, OP_DMT, _R_V0, MIPS_COP_0_TLB_CONTEXT, 2) | | 178 | #define _MTC0_V0_USERLOCAL _MKINSN(OP_COP0, OP_DMT, _R_V0, MIPS_COP_0_TLB_CONTEXT, 2) |
179 | #else | | 179 | #else |
180 | #define _LOAD_V0_L_PRIVATE_A0 _MKINSN(OP_LW, _R_A0, _R_V0, 0, offsetof(lwp_t, l_private)) | | 180 | #define _LOAD_V0_L_PRIVATE_A0 _MKINSN(OP_LW, _R_A0, _R_V0, 0, offsetof(lwp_t, l_private)) |
181 | #define _MTC0_V0_USERLOCAL _MKINSN(OP_COP0, OP_MT, _R_V0, MIPS_COP_0_TLB_CONTEXT, 2) | | 181 | #define _MTC0_V0_USERLOCAL _MKINSN(OP_COP0, OP_MT, _R_V0, MIPS_COP_0_TLB_CONTEXT, 2) |
182 | #endif | | 182 | #endif |
183 | #define JR_RA _MKINSN(OP_SPECIAL, _R_RA, 0, 0, OP_JR) | | 183 | #define JR_RA _MKINSN(OP_SPECIAL, _R_RA, 0, 0, OP_JR) |
184 | | | 184 | |
185 | #endif | | 185 | #endif |
186 | | | 186 | |
187 | /* Internal routines. */ | | 187 | /* Internal routines. */ |
188 | int cpu_dumpsize(void); | | 188 | int cpu_dumpsize(void); |
189 | u_long cpu_dump_mempagecnt(void); | | 189 | u_long cpu_dump_mempagecnt(void); |
190 | int cpu_dump(void); | | 190 | int cpu_dump(void); |
191 | | | 191 | |
192 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 | | 192 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 |
193 | static void mips_watchpoint_init(void); | | 193 | static void mips_watchpoint_init(void); |
194 | #endif | | 194 | #endif |
195 | | | 195 | |
196 | #if defined(_LP64) && defined(ENABLE_MIPS_16KB_PAGE) | | 196 | #if defined(_LP64) && defined(ENABLE_MIPS_16KB_PAGE) |
197 | vaddr_t mips_vm_maxuser_address = MIPS_VM_MAXUSER_ADDRESS; | | 197 | vaddr_t mips_vm_maxuser_address = MIPS_VM_MAXUSER_ADDRESS; |
198 | #endif | | 198 | #endif |
199 | | | 199 | |
200 | #if defined(MIPS3_PLUS) | | 200 | #if defined(MIPS3_PLUS) |
201 | uint32_t mips3_cp0_tlb_page_mask_probe(void); | | 201 | uint32_t mips3_cp0_tlb_page_mask_probe(void); |
202 | uint64_t mips3_cp0_tlb_entry_hi_probe(void); | | 202 | uint64_t mips3_cp0_tlb_entry_hi_probe(void); |
203 | uint64_t mips3_cp0_tlb_entry_lo_probe(void); | | 203 | uint64_t mips3_cp0_tlb_entry_lo_probe(void); |
204 | | | 204 | |
205 | static void mips3_tlb_probe(void); | | 205 | static void mips3_tlb_probe(void); |
206 | #endif | | 206 | #endif |
207 | | | 207 | |
208 | /* | | 208 | /* |
209 | * safepri is a safe priority for sleepq to set for a spin-wait during | | 209 | * safepri is a safe priority for sleepq to set for a spin-wait during |
210 | * autoconfiguration or after a panic which will allows interrupts to | | 210 | * autoconfiguration or after a panic which will allows interrupts to |
211 | * be delivered. Used as an argument to splx(). | | 211 | * be delivered. Used as an argument to splx(). |
212 | */ | | 212 | */ |
213 | int safepri = IPL_SOFTSERIAL; | | 213 | int safepri = IPL_SOFTSERIAL; |
214 | | | 214 | |
215 | #if defined(MIPS1) | | 215 | #if defined(MIPS1) |
216 | static void mips1_vector_init(const struct splsw *); | | 216 | static void mips1_vector_init(const struct splsw *); |
217 | extern const struct locoresw mips1_locoresw; | | 217 | extern const struct locoresw mips1_locoresw; |
218 | extern const mips_locore_jumpvec_t mips1_locore_vec; | | 218 | extern const mips_locore_jumpvec_t mips1_locore_vec; |
219 | #endif | | 219 | #endif |
220 | | | 220 | |
221 | #if defined(MIPS3) | | 221 | #if defined(MIPS3) |
222 | static void mips3_vector_init(const struct splsw *); | | 222 | static void mips3_vector_init(const struct splsw *); |
223 | extern const struct locoresw mips3_locoresw; | | 223 | extern const struct locoresw mips3_locoresw; |
224 | extern const mips_locore_jumpvec_t mips3_locore_vec; | | 224 | extern const mips_locore_jumpvec_t mips3_locore_vec; |
225 | #endif | | 225 | #endif |
226 | | | 226 | |
227 | #if defined(MIPS3_LOONGSON2) | | 227 | #if defined(MIPS3_LOONGSON2) |
228 | static void loongson2_vector_init(const struct splsw *); | | 228 | static void loongson2_vector_init(const struct splsw *); |
229 | extern const struct locoresw loongson2_locoresw; | | 229 | extern const struct locoresw loongson2_locoresw; |
230 | extern const mips_locore_jumpvec_t loongson2_locore_vec; | | 230 | extern const mips_locore_jumpvec_t loongson2_locore_vec; |
231 | #endif | | 231 | #endif |
232 | | | 232 | |
233 | #if defined(MIPS32) | | 233 | #if defined(MIPS32) |
234 | static void mips32_vector_init(const struct splsw *); | | 234 | static void mips32_vector_init(const struct splsw *); |
235 | extern const struct locoresw mips32_locoresw; | | 235 | extern const struct locoresw mips32_locoresw; |
236 | extern const mips_locore_jumpvec_t mips32_locore_vec; | | 236 | extern const mips_locore_jumpvec_t mips32_locore_vec; |
237 | #endif | | 237 | #endif |
238 | | | 238 | |
239 | #if defined(MIPS32R2) | | 239 | #if defined(MIPS32R2) |
240 | static void mips32r2_vector_init(const struct splsw *); | | 240 | static void mips32r2_vector_init(const struct splsw *); |
241 | extern const struct locoresw mips32r2_locoresw; | | 241 | extern const struct locoresw mips32r2_locoresw; |
242 | extern const mips_locore_jumpvec_t mips32r2_locore_vec; | | 242 | extern const mips_locore_jumpvec_t mips32r2_locore_vec; |
243 | #endif | | 243 | #endif |
244 | | | 244 | |
245 | #if defined(MIPS64) | | 245 | #if defined(MIPS64) |
246 | static void mips64_vector_init(const struct splsw *); | | 246 | static void mips64_vector_init(const struct splsw *); |
247 | extern const struct locoresw mips64_locoresw; | | 247 | extern const struct locoresw mips64_locoresw; |
248 | extern const mips_locore_jumpvec_t mips64_locore_vec; | | 248 | extern const mips_locore_jumpvec_t mips64_locore_vec; |
249 | #endif | | 249 | #endif |
250 | | | 250 | |
251 | #if defined(MIPS64R2) | | 251 | #if defined(MIPS64R2) |
252 | static void mips64r2_vector_init(const struct splsw *); | | 252 | static void mips64r2_vector_init(const struct splsw *); |
253 | extern const struct locoresw mips64r2_locoresw; | | 253 | extern const struct locoresw mips64r2_locoresw; |
254 | extern const mips_locore_jumpvec_t mips64r2_locore_vec; | | 254 | extern const mips_locore_jumpvec_t mips64r2_locore_vec; |
255 | #endif | | 255 | #endif |
256 | | | 256 | |
257 | #if defined(PARANOIA) | | 257 | #if defined(PARANOIA) |
258 | void std_splsw_test(void); | | 258 | void std_splsw_test(void); |
259 | #endif | | 259 | #endif |
260 | | | 260 | |
261 | mips_locore_jumpvec_t mips_locore_jumpvec; | | 261 | mips_locore_jumpvec_t mips_locore_jumpvec; |
262 | | | 262 | |
263 | struct locoresw mips_locoresw; | | 263 | struct locoresw mips_locoresw; |
264 | | | 264 | |
265 | extern const struct splsw std_splsw; | | 265 | extern const struct splsw std_splsw; |
266 | struct splsw mips_splsw; | | 266 | struct splsw mips_splsw; |
267 | | | 267 | |
268 | struct mips_options mips_options = { | | 268 | struct mips_options mips_options = { |
269 | .mips_cpu_id = 0xffffffff, | | 269 | .mips_cpu_id = 0xffffffff, |
270 | .mips_fpu_id = 0xffffffff, | | 270 | .mips_fpu_id = 0xffffffff, |
271 | }; | | 271 | }; |
272 | | | 272 | |
273 | struct user *proc0paddr; | | 273 | struct user *proc0paddr; |
274 | | | 274 | |
275 | void * msgbufaddr; | | 275 | void * msgbufaddr; |
276 | | | 276 | |
277 | /* the following is used externally (sysctl_hw) */ | | 277 | /* the following is used externally (sysctl_hw) */ |
278 | char machine[] = MACHINE; /* from <machine/param.h> */ | | 278 | char machine[] = MACHINE; /* from <machine/param.h> */ |
279 | char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ | | 279 | char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */ |
280 | char cpu_model[128]; | | 280 | char cpu_model[128]; |
281 | | | 281 | |
282 | | | 282 | |
283 | /* | | 283 | /* |
284 | * Assumptions: | | 284 | * Assumptions: |
285 | * - All MIPS3+ have an r4k-style MMU. _Many_ assumptions throughout | | 285 | * - All MIPS3+ have an r4k-style MMU. _Many_ assumptions throughout |
286 | * much of the mips code about this. Includes overloaded usage of | | 286 | * much of the mips code about this. Includes overloaded usage of |
287 | * MIPS3_PLUS. | | 287 | * MIPS3_PLUS. |
288 | * - All MIPS3+ use the same exception model (cp0 status, cause bits, | | 288 | * - All MIPS3+ use the same exception model (cp0 status, cause bits, |
289 | * etc). _Many_ assumptions throughout much of the mips code about | | 289 | * etc). _Many_ assumptions throughout much of the mips code about |
290 | * this. Includes overloaded usage of MIPS3_PLUS. | | 290 | * this. Includes overloaded usage of MIPS3_PLUS. |
291 | * - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h> | | 291 | * - All MIPS3+ have a count register. MIPS_HAS_CLOCK in <mips/cpu.h> |
292 | * will need to be revised if this is false. | | 292 | * will need to be revised if this is false. |
293 | */ | | 293 | */ |
294 | #define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_USE_WAIT | | 294 | #define MIPS32_FLAGS CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_USE_WAIT |
295 | #define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */ | | 295 | #define MIPS64_FLAGS MIPS32_FLAGS /* same as MIPS32 flags (for now) */ |
296 | | | 296 | |
297 | static const struct pridtab cputab[] = { | | 297 | static const struct pridtab cputab[] = { |
298 | { 0, MIPS_R2000, -1, -1, CPU_ARCH_MIPS1, 64, | | 298 | { 0, MIPS_R2000, -1, -1, CPU_ARCH_MIPS1, 64, |
299 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000 CPU" }, | | 299 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000 CPU" }, |
300 | { 0, MIPS_R3000, MIPS_REV_R2000A, -1, CPU_ARCH_MIPS1, 64, | | 300 | { 0, MIPS_R3000, MIPS_REV_R2000A, -1, CPU_ARCH_MIPS1, 64, |
301 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000A CPU" }, | | 301 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R2000A CPU" }, |
302 | { 0, MIPS_R3000, MIPS_REV_R3000, -1, CPU_ARCH_MIPS1, 64, | | 302 | { 0, MIPS_R3000, MIPS_REV_R3000, -1, CPU_ARCH_MIPS1, 64, |
303 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000 CPU" }, | | 303 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000 CPU" }, |
304 | { 0, MIPS_R3000, MIPS_REV_R3000A, -1, CPU_ARCH_MIPS1, 64, | | 304 | { 0, MIPS_R3000, MIPS_REV_R3000A, -1, CPU_ARCH_MIPS1, 64, |
305 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000A CPU" }, | | 305 | CPU_MIPS_NO_LLSC, 0, 0, "MIPS R3000A CPU" }, |
306 | { 0, MIPS_R6000, -1, -1, CPU_ARCH_MIPS2, 32, | | 306 | { 0, MIPS_R6000, -1, -1, CPU_ARCH_MIPS2, 32, |
307 | MIPS_NOT_SUPP, 0, 0, "MIPS R6000 CPU" }, | | 307 | MIPS_NOT_SUPP, 0, 0, "MIPS R6000 CPU" }, |
308 | | | 308 | |
309 | /* | | 309 | /* |
310 | * rev 0x00, 0x22 and 0x30 are R4000, 0x40, 0x50 and 0x60 are R4400. | | 310 | * rev 0x00, 0x22 and 0x30 are R4000, 0x40, 0x50 and 0x60 are R4400. |
311 | * should we allow ranges and use 0x00 - 0x3f for R4000 and | | 311 | * should we allow ranges and use 0x00 - 0x3f for R4000 and |
312 | * 0x40 - 0xff for R4400? | | 312 | * 0x40 - 0xff for R4400? |
313 | */ | | 313 | */ |
314 | { 0, MIPS_R4000, MIPS_REV_R4000_A, -1, CPU_ARCH_MIPS3, 48, | | 314 | { 0, MIPS_R4000, MIPS_REV_R4000_A, -1, CPU_ARCH_MIPS3, 48, |
315 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 315 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
316 | "MIPS R4000 CPU" }, | | 316 | "MIPS R4000 CPU" }, |
317 | { 0, MIPS_R4000, MIPS_REV_R4000_B, -1, CPU_ARCH_MIPS3, 48, | | 317 | { 0, MIPS_R4000, MIPS_REV_R4000_B, -1, CPU_ARCH_MIPS3, 48, |
318 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 318 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
319 | "MIPS R4000 CPU" }, | | 319 | "MIPS R4000 CPU" }, |
320 | { 0, MIPS_R4000, MIPS_REV_R4000_C, -1, CPU_ARCH_MIPS3, 48, | | 320 | { 0, MIPS_R4000, MIPS_REV_R4000_C, -1, CPU_ARCH_MIPS3, 48, |
321 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 321 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
322 | "MIPS R4000 CPU" }, | | 322 | "MIPS R4000 CPU" }, |
323 | { 0, MIPS_R4000, MIPS_REV_R4400_A, -1, CPU_ARCH_MIPS3, 48, | | 323 | { 0, MIPS_R4000, MIPS_REV_R4400_A, -1, CPU_ARCH_MIPS3, 48, |
324 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 324 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
325 | "MIPS R4400 CPU" }, | | 325 | "MIPS R4400 CPU" }, |
326 | { 0, MIPS_R4000, MIPS_REV_R4400_B, -1, CPU_ARCH_MIPS3, 48, | | 326 | { 0, MIPS_R4000, MIPS_REV_R4400_B, -1, CPU_ARCH_MIPS3, 48, |
327 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 327 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
328 | "MIPS R4400 CPU" }, | | 328 | "MIPS R4400 CPU" }, |
329 | { 0, MIPS_R4000, MIPS_REV_R4400_C, -1, CPU_ARCH_MIPS3, 48, | | 329 | { 0, MIPS_R4000, MIPS_REV_R4400_C, -1, CPU_ARCH_MIPS3, 48, |
330 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 330 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
331 | "MIPS R4400 CPU" }, | | 331 | "MIPS R4400 CPU" }, |
332 | | | 332 | |
333 | { 0, MIPS_R3LSI, -1, -1, CPU_ARCH_MIPS1, -1, | | 333 | { 0, MIPS_R3LSI, -1, -1, CPU_ARCH_MIPS1, -1, |
334 | MIPS_NOT_SUPP, 0, 0, "LSI Logic R3000 derivative" }, | | 334 | MIPS_NOT_SUPP, 0, 0, "LSI Logic R3000 derivative" }, |
335 | { 0, MIPS_R6000A, -1, -1, CPU_ARCH_MIPS2, 32, | | 335 | { 0, MIPS_R6000A, -1, -1, CPU_ARCH_MIPS2, 32, |
336 | MIPS_NOT_SUPP, 0, 0, "MIPS R6000A CPU" }, | | 336 | MIPS_NOT_SUPP, 0, 0, "MIPS R6000A CPU" }, |
337 | { 0, MIPS_R3IDT, -1, -1, CPU_ARCH_MIPS1, -1, | | 337 | { 0, MIPS_R3IDT, -1, -1, CPU_ARCH_MIPS1, -1, |
338 | MIPS_NOT_SUPP, 0, 0, "IDT R3041 or RC36100 CPU" }, | | 338 | MIPS_NOT_SUPP, 0, 0, "IDT R3041 or RC36100 CPU" }, |
339 | { 0, MIPS_R4100, -1, -1, CPU_ARCH_MIPS3, 32, | | 339 | { 0, MIPS_R4100, -1, -1, CPU_ARCH_MIPS3, 32, |
340 | CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, 0, 0, | | 340 | CPU_MIPS_R4K_MMU | CPU_MIPS_NO_LLSC, 0, 0, |
341 | "NEC VR4100 CPU" }, | | 341 | "NEC VR4100 CPU" }, |
342 | { 0, MIPS_R4200, -1, -1, CPU_ARCH_MIPS3, -1, | | 342 | { 0, MIPS_R4200, -1, -1, CPU_ARCH_MIPS3, -1, |
343 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 343 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
344 | "NEC VR4200 CPU" }, | | 344 | "NEC VR4200 CPU" }, |
345 | { 0, MIPS_R4300, -1, -1, CPU_ARCH_MIPS3, 32, | | 345 | { 0, MIPS_R4300, -1, -1, CPU_ARCH_MIPS3, 32, |
346 | CPU_MIPS_R4K_MMU, 0, 0, "NEC VR4300 CPU" }, | | 346 | CPU_MIPS_R4K_MMU, 0, 0, "NEC VR4300 CPU" }, |
347 | { 0, MIPS_R4600, -1, -1, CPU_ARCH_MIPS3, 48, | | 347 | { 0, MIPS_R4600, -1, -1, CPU_ARCH_MIPS3, 48, |
348 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 348 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
349 | "QED R4600 Orion CPU" }, | | 349 | "QED R4600 Orion CPU" }, |
350 | { 0, MIPS_R4700, -1, -1, CPU_ARCH_MIPS3, 48, | | 350 | { 0, MIPS_R4700, -1, -1, CPU_ARCH_MIPS3, 48, |
351 | CPU_MIPS_R4K_MMU, 0, 0, "QED R4700 Orion CPU" }, | | 351 | CPU_MIPS_R4K_MMU, 0, 0, "QED R4700 Orion CPU" }, |
352 | | | 352 | |
353 | { 0, MIPS_R8000, -1, -1, CPU_ARCH_MIPS4, 384, | | 353 | { 0, MIPS_R8000, -1, -1, CPU_ARCH_MIPS4, 384, |
354 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 354 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
355 | "MIPS R8000 Blackbird/TFP CPU" }, | | 355 | "MIPS R8000 Blackbird/TFP CPU" }, |
356 | { 0, MIPS_R10000, -1, -1, CPU_ARCH_MIPS4, 64, | | 356 | { 0, MIPS_R10000, -1, -1, CPU_ARCH_MIPS4, 64, |
357 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 357 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
358 | "MIPS R10000 CPU" }, | | 358 | "MIPS R10000 CPU" }, |
359 | { 0, MIPS_R12000, -1, -1, CPU_ARCH_MIPS4, 64, | | 359 | { 0, MIPS_R12000, -1, -1, CPU_ARCH_MIPS4, 64, |
360 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 360 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
361 | "MIPS R12000 CPU" }, | | 361 | "MIPS R12000 CPU" }, |
362 | { 0, MIPS_R14000, -1, -1, CPU_ARCH_MIPS4, 64, | | 362 | { 0, MIPS_R14000, -1, -1, CPU_ARCH_MIPS4, 64, |
363 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 363 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
364 | "MIPS R14000 CPU" }, | | 364 | "MIPS R14000 CPU" }, |
365 | | | 365 | |
366 | /* XXX | | 366 | /* XXX |
367 | * If the Processor Revision ID of the 4650 isn't 0, the following | | 367 | * If the Processor Revision ID of the 4650 isn't 0, the following |
368 | * entry needs to be adjusted. Can't use a wildcard match because | | 368 | * entry needs to be adjusted. Can't use a wildcard match because |
369 | * the TX39 series processors share the same Processor ID value. | | 369 | * the TX39 series processors share the same Processor ID value. |
370 | * Or maybe put TX39 CPUs first if the revid doesn't overlap with | | 370 | * Or maybe put TX39 CPUs first if the revid doesn't overlap with |
371 | * the 4650... | | 371 | * the 4650... |
372 | */ | | 372 | */ |
373 | { 0, MIPS_R4650, 0, -1, CPU_ARCH_MIPS3, -1, | | 373 | { 0, MIPS_R4650, 0, -1, CPU_ARCH_MIPS3, -1, |
374 | MIPS_NOT_SUPP /* no MMU! */, 0, 0, "QED R4650 CPU" }, | | 374 | MIPS_NOT_SUPP /* no MMU! */, 0, 0, "QED R4650 CPU" }, |
375 | { 0, MIPS_TX3900, MIPS_REV_TX3912, -1, CPU_ARCH_MIPS1, 32, | | 375 | { 0, MIPS_TX3900, MIPS_REV_TX3912, -1, CPU_ARCH_MIPS1, 32, |
376 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3912 CPU" }, | | 376 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3912 CPU" }, |
377 | { 0, MIPS_TX3900, MIPS_REV_TX3922, -1, CPU_ARCH_MIPS1, 64, | | 377 | { 0, MIPS_TX3900, MIPS_REV_TX3922, -1, CPU_ARCH_MIPS1, 64, |
378 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3922 CPU" }, | | 378 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3922 CPU" }, |
379 | { 0, MIPS_TX3900, MIPS_REV_TX3927, -1, CPU_ARCH_MIPS1, 64, | | 379 | { 0, MIPS_TX3900, MIPS_REV_TX3927, -1, CPU_ARCH_MIPS1, 64, |
380 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3927 CPU" }, | | 380 | CPU_MIPS_NO_LLSC, 0, 0, "Toshiba TX3927 CPU" }, |
381 | { 0, MIPS_R5000, -1, -1, CPU_ARCH_MIPS4, 48, | | 381 | { 0, MIPS_R5000, -1, -1, CPU_ARCH_MIPS4, 48, |
382 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 382 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
383 | "MIPS R5000 CPU" }, | | 383 | "MIPS R5000 CPU" }, |
384 | { 0, MIPS_RM5200, -1, -1, CPU_ARCH_MIPS4, 48, | | 384 | { 0, MIPS_RM5200, -1, -1, CPU_ARCH_MIPS4, 48, |
385 | CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | | | 385 | CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | |
386 | CPU_MIPS_USE_WAIT, 0, 0, "QED RM5200 CPU" }, | | 386 | CPU_MIPS_USE_WAIT, 0, 0, "QED RM5200 CPU" }, |
387 | | | 387 | |
388 | /* XXX | | 388 | /* XXX |
389 | * The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See | | 389 | * The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See |
390 | * "Migrating to the RM7000 from other MIPS Microprocessors" | | 390 | * "Migrating to the RM7000 from other MIPS Microprocessors" |
391 | * for more details. | | 391 | * for more details. |
392 | */ | | 392 | */ |
393 | { 0, MIPS_RM7000, -1, -1, CPU_ARCH_MIPS4, 48, | | 393 | { 0, MIPS_RM7000, -1, -1, CPU_ARCH_MIPS4, 48, |
394 | MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | | | 394 | MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT | |
395 | CPU_MIPS_USE_WAIT, 0, 0, "QED RM7000 CPU" }, | | 395 | CPU_MIPS_USE_WAIT, 0, 0, "QED RM7000 CPU" }, |
396 | | | 396 | |
397 | /* | | 397 | /* |
398 | * IDT RC32300 core is a 32 bit MIPS2 processor with | | 398 | * IDT RC32300 core is a 32 bit MIPS2 processor with |
399 | * MIPS3/MIPS4 extensions. It has an R4000-style TLB, | | 399 | * MIPS3/MIPS4 extensions. It has an R4000-style TLB, |
400 | * while all registers are 32 bits and any 64 bit | | 400 | * while all registers are 32 bits and any 64 bit |
401 | * instructions like ld/sd/dmfc0/dmtc0 are not allowed. | | 401 | * instructions like ld/sd/dmfc0/dmtc0 are not allowed. |
402 | * | | 402 | * |
403 | * note that the Config register has a non-standard base | | 403 | * note that the Config register has a non-standard base |
404 | * for IC and DC (2^9 instead of 2^12). | | 404 | * for IC and DC (2^9 instead of 2^12). |
405 | * | | 405 | * |
406 | */ | | 406 | */ |
407 | { 0, MIPS_RC32300, -1, -1, CPU_ARCH_MIPS3, 16, | | 407 | { 0, MIPS_RC32300, -1, -1, CPU_ARCH_MIPS3, 16, |
408 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 408 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
409 | "IDT RC32300 CPU" }, | | 409 | "IDT RC32300 CPU" }, |
410 | { 0, MIPS_RC32364, -1, -1, CPU_ARCH_MIPS3, 16, | | 410 | { 0, MIPS_RC32364, -1, -1, CPU_ARCH_MIPS3, 16, |
411 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 411 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
412 | "IDT RC32364 CPU" }, | | 412 | "IDT RC32364 CPU" }, |
413 | { 0, MIPS_RC64470, -1, -1, CPU_ARCH_MIPSx, -1, | | 413 | { 0, MIPS_RC64470, -1, -1, CPU_ARCH_MIPSx, -1, |
414 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 414 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
415 | "IDT RC64474/RC64475 CPU" }, | | 415 | "IDT RC64474/RC64475 CPU" }, |
416 | | | 416 | |
417 | { 0, MIPS_R5400, -1, -1, CPU_ARCH_MIPSx, -1, | | 417 | { 0, MIPS_R5400, -1, -1, CPU_ARCH_MIPSx, -1, |
418 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, | | 418 | MIPS_NOT_SUPP | CPU_MIPS_R4K_MMU, 0, 0, |
419 | "NEC VR5400 CPU" }, | | 419 | "NEC VR5400 CPU" }, |
420 | { 0, MIPS_R5900, -1, -1, CPU_ARCH_MIPS3, 48, | | 420 | { 0, MIPS_R5900, -1, -1, CPU_ARCH_MIPS3, 48, |
421 | CPU_MIPS_NO_LLSC | CPU_MIPS_R4K_MMU, 0, 0, | | 421 | CPU_MIPS_NO_LLSC | CPU_MIPS_R4K_MMU, 0, 0, |
422 | "Toshiba R5900 CPU" }, | | 422 | "Toshiba R5900 CPU" }, |
423 | | | 423 | |
424 | { 0, MIPS_TX4900, MIPS_REV_TX4927, -1, CPU_ARCH_MIPS3, 48, | | 424 | { 0, MIPS_TX4900, MIPS_REV_TX4927, -1, CPU_ARCH_MIPS3, 48, |
425 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 425 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
426 | "Toshiba TX4927 CPU" }, | | 426 | "Toshiba TX4927 CPU" }, |
427 | | | 427 | |
428 | { 0, MIPS_TX4900, -1, -1, CPU_ARCH_MIPS3, 48, | | 428 | { 0, MIPS_TX4900, -1, -1, CPU_ARCH_MIPS3, 48, |
429 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, | | 429 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT, 0, 0, |
430 | "Toshiba TX4900 CPU" }, | | 430 | "Toshiba TX4900 CPU" }, |
431 | | | 431 | |
432 | /* | | 432 | /* |
433 | * ICT Loongson2 is a MIPS64 CPU with a few quirks. For some reason | | 433 | * ICT Loongson2 is a MIPS64 CPU with a few quirks. For some reason |
434 | * the virtual aliases present with 4KB pages make the caches misbehave | | 434 | * the virtual aliases present with 4KB pages make the caches misbehave |
435 | * so we make all accesses uncached. With 16KB pages, no virtual | | 435 | * so we make all accesses uncached. With 16KB pages, no virtual |
436 | * aliases are possible so we can use caching. | | 436 | * aliases are possible so we can use caching. |
437 | */ | | 437 | */ |
438 | #ifdef ENABLE_MIPS_16KB_PAGE | | 438 | #ifdef ENABLE_MIPS_16KB_PAGE |
439 | #define MIPS_LOONGSON2_CCA 0 | | 439 | #define MIPS_LOONGSON2_CCA 0 |
440 | #else | | 440 | #else |
441 | #define MIPS_LOONGSON2_CCA (CPU_MIPS_HAVE_SPECIAL_CCA | \ | | 441 | #define MIPS_LOONGSON2_CCA (CPU_MIPS_HAVE_SPECIAL_CCA | \ |
442 | (2 << CPU_MIPS_CACHED_CCA_SHIFT)) | | 442 | (2 << CPU_MIPS_CACHED_CCA_SHIFT)) |
443 | #endif | | 443 | #endif |
444 | { 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2E, -1, CPU_ARCH_MIPS3, 64, | | 444 | { 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2E, -1, CPU_ARCH_MIPS3, 64, |
445 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2 | | 445 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2 |
446 | | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2E CPU" }, | | 446 | | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2E CPU" }, |
447 | { 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2F, -1, CPU_ARCH_MIPS3, 64, | | 447 | { 0, MIPS_LOONGSON2, MIPS_REV_LOONGSON2F, -1, CPU_ARCH_MIPS3, 64, |
448 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2 | | 448 | CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT | CPU_MIPS_LOONGSON2 |
449 | | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2F CPU" }, | | 449 | | MIPS_LOONGSON2_CCA, 0, 0, "ICT Loongson 2F CPU" }, |
450 | | | 450 | |
451 | #if 0 /* ID collisions : can we use a CU1 test or similar? */ | | 451 | #if 0 /* ID collisions : can we use a CU1 test or similar? */ |
452 | { 0, MIPS_R3SONY, -1, -1, CPU_ARCH_MIPS1, -1, | | 452 | { 0, MIPS_R3SONY, -1, -1, CPU_ARCH_MIPS1, -1, |
453 | MIPS_NOT_SUPP, 0, 0, "SONY R3000 derivative" }, /* 0x21; crash R4700? */ | | 453 | MIPS_NOT_SUPP, 0, 0, "SONY R3000 derivative" }, /* 0x21; crash R4700? */ |
454 | { 0, MIPS_R3NKK, -1, -1, CPU_ARCH_MIPS1, -1, | | 454 | { 0, MIPS_R3NKK, -1, -1, CPU_ARCH_MIPS1, -1, |
455 | MIPS_NOT_SUPP, 0, 0, "NKK R3000 derivative" }, /* 0x23; crash R5000? */ | | 455 | MIPS_NOT_SUPP, 0, 0, "NKK R3000 derivative" }, /* 0x23; crash R5000? */ |
456 | #endif | | 456 | #endif |
457 | | | 457 | |
458 | { MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1, -1, 0, | | 458 | { MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1, -1, 0, |
459 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4Kc" }, | | 459 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4Kc" }, |
460 | { MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1, -1, 0, | | 460 | { MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1, -1, 0, |
461 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc" }, | | 461 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc" }, |
462 | { MIPS_PRID_CID_MTI, MIPS_4KEc_R2, -1, -1, -1, 0, | | 462 | { MIPS_PRID_CID_MTI, MIPS_4KEc_R2, -1, -1, -1, 0, |
463 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc (Rev 2)" }, | | 463 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KEc (Rev 2)" }, |
464 | { MIPS_PRID_CID_MTI, MIPS_4KSc, -1, -1, -1, 0, | | 464 | { MIPS_PRID_CID_MTI, MIPS_4KSc, -1, -1, -1, 0, |
465 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KSc" }, | | 465 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "4KSc" }, |
466 | { MIPS_PRID_CID_MTI, MIPS_5Kc, -1, -1, -1, 0, | | 466 | { MIPS_PRID_CID_MTI, MIPS_5Kc, -1, -1, -1, 0, |
467 | MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "5Kc" }, | | 467 | MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, 0, 0, "5Kc" }, |
468 | { MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0, | | 468 | { MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0, |
469 | MIPS64_FLAGS, 0, 0, "20Kc" }, | | 469 | MIPS64_FLAGS, 0, 0, "20Kc" }, |
470 | { MIPS_PRID_CID_MTI, MIPS_24K, -1, -1, -1, 0, | | 470 | { MIPS_PRID_CID_MTI, MIPS_24K, -1, -1, -1, 0, |
471 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, | | 471 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, |
472 | MIPS_CP0FL_USE | | | 472 | MIPS_CP0FL_USE | |
473 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | | | 473 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | |
474 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | | | 474 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | |
475 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, | | 475 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, |
476 | 0, "24K" }, | | 476 | 0, "24K" }, |
477 | { MIPS_PRID_CID_MTI, MIPS_24KE, -1, -1, -1, 0, | | 477 | { MIPS_PRID_CID_MTI, MIPS_24KE, -1, -1, -1, 0, |
478 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, | | 478 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, |
479 | MIPS_CP0FL_USE | | | 479 | MIPS_CP0FL_USE | |
480 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | | | 480 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | |
481 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | | | 481 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | |
482 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, | | 482 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, |
483 | 0, "24KE" }, | | 483 | 0, "24KE" }, |
484 | { MIPS_PRID_CID_MTI, MIPS_34K, -1, -1, -1, 0, | | 484 | { MIPS_PRID_CID_MTI, MIPS_34K, -1, -1, -1, 0, |
485 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, | | 485 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, |
486 | MIPS_CP0FL_USE | | | 486 | MIPS_CP0FL_USE | |
487 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | | | 487 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | |
488 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | | | 488 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | |
489 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, | | 489 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG7, |
490 | 0, "34K" }, | | 490 | 0, "34K" }, |
491 | { MIPS_PRID_CID_MTI, MIPS_74K, -1, -1, -1, 0, | | 491 | { MIPS_PRID_CID_MTI, MIPS_74K, -1, -1, -1, 0, |
492 | CPU_MIPS_HAVE_SPECIAL_CCA | (0 << CPU_MIPS_CACHED_CCA_SHIFT) | | | 492 | CPU_MIPS_HAVE_SPECIAL_CCA | (0 << CPU_MIPS_CACHED_CCA_SHIFT) | |
493 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, | | 493 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, |
494 | MIPS_CP0FL_USE | | | 494 | MIPS_CP0FL_USE | |
495 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | | | 495 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | |
496 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | | | 496 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | |
497 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7, | | 497 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7, |
498 | 0, "74K" }, | | 498 | 0, "74K" }, |
499 | { MIPS_PRID_CID_MTI, MIPS_1004K, -1, -1, -1, 0, | | 499 | { MIPS_PRID_CID_MTI, MIPS_1004K, -1, -1, -1, 0, |
500 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, | | 500 | MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, |
501 | MIPS_CP0FL_USE | | | 501 | MIPS_CP0FL_USE | |
502 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | | | 502 | MIPS_CP0FL_EBASE | MIPS_CP0FL_USERLOCAL | MIPS_CP0FL_HWRENA | |
503 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | | | 503 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG2 | |
504 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7, | | 504 | MIPS_CP0FL_CONFIG3 | MIPS_CP0FL_CONFIG6 | MIPS_CP0FL_CONFIG7, |
505 | 0, "1004K" }, | | 505 | 0, "1004K" }, |
506 | | | 506 | |
507 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0, | | 507 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0, |
508 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 508 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
509 | "Au1000 (Rev 1 core)" }, | | 509 | "Au1000 (Rev 1 core)" }, |
510 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0, | | 510 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0, |
511 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 511 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
512 | "Au1000 (Rev 2 core)" }, | | 512 | "Au1000 (Rev 2 core)" }, |
513 | | | 513 | |
514 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0, | | 514 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0, |
515 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 515 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
516 | "Au1100 (Rev 1 core)" }, | | 516 | "Au1100 (Rev 1 core)" }, |
517 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0, | | 517 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0, |
518 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 518 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
519 | "Au1100 (Rev 2 core)" }, | | 519 | "Au1100 (Rev 2 core)" }, |
520 | | | 520 | |
521 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0, | | 521 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0, |
522 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 522 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
523 | "Au1500 (Rev 1 core)" }, | | 523 | "Au1500 (Rev 1 core)" }, |
524 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0, | | 524 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0, |
525 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 525 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
526 | "Au1500 (Rev 2 core)" }, | | 526 | "Au1500 (Rev 2 core)" }, |
527 | | | 527 | |
528 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1550, -1, 0, | | 528 | { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1550, -1, 0, |
529 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, | | 529 | MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT, 0, 0, |
530 | "Au1550 (Rev 2 core)" }, | | 530 | "Au1550 (Rev 2 core)" }, |
531 | | | 531 | |
532 | /* The SB-1 CPU uses a CCA of 5 - "Cacheable Coherent Shareable" */ | | 532 | /* The SB-1 CPU uses a CCA of 5 - "Cacheable Coherent Shareable" */ |
533 | { MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0, | | 533 | { MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1, -1, -1, 0, |
534 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | | | 534 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | |
535 | CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), 0, 0, | | 535 | CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT), 0, 0, |
536 | "SB-1" }, | | 536 | "SB-1" }, |
537 | | | 537 | |
538 | { MIPS_PRID_CID_RMI, MIPS_XLR732B, -1, -1, -1, 0, | | 538 | { MIPS_PRID_CID_RMI, MIPS_XLR732B, -1, -1, -1, 0, |
539 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 539 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
540 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 540 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
541 | MIPS_CP0FL_USE | | | 541 | MIPS_CP0FL_USE | |
542 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 542 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
543 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 543 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
544 | CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB), | | 544 | CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB), |
545 | "XLR732B" }, | | 545 | "XLR732B" }, |
546 | | | 546 | |
547 | { MIPS_PRID_CID_RMI, MIPS_XLR732C, -1, -1, -1, 0, | | 547 | { MIPS_PRID_CID_RMI, MIPS_XLR732C, -1, -1, -1, 0, |
548 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 548 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
549 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 549 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
550 | MIPS_CP0FL_USE | | | 550 | MIPS_CP0FL_USE | |
551 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 551 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
552 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 552 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
553 | CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB), | | 553 | CIDFL_RMI_TYPE_XLR|MIPS_CIDFL_RMI_CPUS(8,4)|MIPS_CIDFL_RMI_L2(2MB), |
554 | "XLR732C" }, | | 554 | "XLR732C" }, |
555 | | | 555 | |
556 | { MIPS_PRID_CID_RMI, MIPS_XLS616, -1, -1, -1, 0, | | 556 | { MIPS_PRID_CID_RMI, MIPS_XLS616, -1, -1, -1, 0, |
557 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 557 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
558 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 558 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
559 | MIPS_CP0FL_USE | | | 559 | MIPS_CP0FL_USE | |
560 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 560 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
561 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 561 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
562 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB), | | 562 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB), |
563 | "XLS616" }, | | 563 | "XLS616" }, |
564 | | | 564 | |
565 | { MIPS_PRID_CID_RMI, MIPS_XLS416, -1, -1, -1, 0, | | 565 | { MIPS_PRID_CID_RMI, MIPS_XLS416, -1, -1, -1, 0, |
566 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 566 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
567 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 567 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
568 | MIPS_CP0FL_USE | | | 568 | MIPS_CP0FL_USE | |
569 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 569 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
570 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 570 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
571 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB), | | 571 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(4,4)|MIPS_CIDFL_RMI_L2(1MB), |
572 | "XLS416" }, | | 572 | "XLS416" }, |
573 | | | 573 | |
574 | { MIPS_PRID_CID_RMI, MIPS_XLS408, -1, -1, -1, 0, | | 574 | { MIPS_PRID_CID_RMI, MIPS_XLS408, -1, -1, -1, 0, |
575 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 575 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
576 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 576 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
577 | MIPS_CP0FL_USE | | | 577 | MIPS_CP0FL_USE | |
578 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 578 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
579 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 579 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
580 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB), | | 580 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB), |
581 | "XLS408" }, | | 581 | "XLS408" }, |
582 | | | 582 | |
583 | { MIPS_PRID_CID_RMI, MIPS_XLS408LITE, -1, -1, -1, 0, | | 583 | { MIPS_PRID_CID_RMI, MIPS_XLS408LITE, -1, -1, -1, 0, |
584 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 584 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
585 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 585 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
586 | MIPS_CP0FL_USE | | | 586 | MIPS_CP0FL_USE | |
587 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 587 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
588 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 588 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
589 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB), | | 589 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(1MB), |
590 | "XLS408lite" }, | | 590 | "XLS408lite" }, |
591 | | | 591 | |
592 | { MIPS_PRID_CID_RMI, MIPS_XLS404LITE, -1, -1, -1, 0, | | 592 | { MIPS_PRID_CID_RMI, MIPS_XLS404LITE, -1, -1, -1, 0, |
593 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 593 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
594 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 594 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
595 | MIPS_CP0FL_USE | | | 595 | MIPS_CP0FL_USE | |
596 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 596 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
597 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 597 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
598 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(512KB), | | 598 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(512KB), |
599 | "XLS404lite" }, | | 599 | "XLS404lite" }, |
600 | | | 600 | |
601 | { MIPS_PRID_CID_RMI, MIPS_XLS208, -1, -1, -1, 0, | | 601 | { MIPS_PRID_CID_RMI, MIPS_XLS208, -1, -1, -1, 0, |
602 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 602 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
603 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 603 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
604 | MIPS_CP0FL_USE | | | 604 | MIPS_CP0FL_USE | |
605 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 605 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
606 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 606 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
607 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB), | | 607 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB), |
608 | "XLS208" }, | | 608 | "XLS208" }, |
609 | | | 609 | |
610 | { MIPS_PRID_CID_RMI, MIPS_XLS204, -1, -1, -1, 0, | | 610 | { MIPS_PRID_CID_RMI, MIPS_XLS204, -1, -1, -1, 0, |
611 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 611 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
612 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 612 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
613 | MIPS_CP0FL_USE | | | 613 | MIPS_CP0FL_USE | |
614 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 614 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
615 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 615 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
616 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB), | | 616 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB), |
617 | "XLS204" }, | | 617 | "XLS204" }, |
618 | | | 618 | |
619 | { MIPS_PRID_CID_RMI, MIPS_XLS108, -1, -1, -1, 0, | | 619 | { MIPS_PRID_CID_RMI, MIPS_XLS108, -1, -1, -1, 0, |
620 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 620 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
621 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 621 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
622 | MIPS_CP0FL_USE | | | 622 | MIPS_CP0FL_USE | |
623 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 623 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
624 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 624 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
625 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB), | | 625 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(2,4)|MIPS_CIDFL_RMI_L2(512KB), |
626 | "XLS108" }, | | 626 | "XLS108" }, |
627 | | | 627 | |
628 | { MIPS_PRID_CID_RMI, MIPS_XLS104, -1, -1, -1, 0, | | 628 | { MIPS_PRID_CID_RMI, MIPS_XLS104, -1, -1, -1, 0, |
629 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | | | 629 | MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_NO_LLADDR | |
630 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, | | 630 | CPU_MIPS_I_D_CACHE_COHERENT | CPU_MIPS_HAVE_MxCR, |
631 | MIPS_CP0FL_USE | | | 631 | MIPS_CP0FL_USE | |
632 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | | | 632 | MIPS_CP0FL_EIRR | MIPS_CP0FL_EIMR | MIPS_CP0FL_EBASE | |
633 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, | | 633 | MIPS_CP0FL_CONFIG | MIPS_CP0FL_CONFIG1 | MIPS_CP0FL_CONFIG7, |
634 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB), | | 634 | CIDFL_RMI_TYPE_XLS|MIPS_CIDFL_RMI_CPUS(1,4)|MIPS_CIDFL_RMI_L2(256KB), |
635 | "XLS104" }, | | 635 | "XLS104" }, |
636 | | | 636 | |
637 | /* Microsoft Research' extensible MIPS */ | | 637 | /* Microsoft Research' extensible MIPS */ |
638 | { MIPS_PRID_CID_MICROSOFT, MIPS_eMIPS, 1, -1, CPU_ARCH_MIPS1, 64, | | 638 | { MIPS_PRID_CID_MICROSOFT, MIPS_eMIPS, 1, -1, CPU_ARCH_MIPS1, 64, |
639 | CPU_MIPS_NO_WAIT, 0, 0, "eMIPS CPU" }, | | 639 | CPU_MIPS_NO_WAIT, 0, 0, "eMIPS CPU" }, |
640 | | | 640 | |
641 | { 0, 0, 0, 0, 0, 0, | | 641 | { 0, 0, 0, 0, 0, 0, |
642 | 0, 0, 0, NULL } | | 642 | 0, 0, 0, NULL } |
643 | }; | | 643 | }; |
644 | | | 644 | |
645 | static const struct pridtab fputab[] = { | | 645 | static const struct pridtab fputab[] = { |
646 | { 0, MIPS_SOFT, -1, 0, 0, 0, 0, 0, 0, "software emulated floating point" }, | | 646 | { 0, MIPS_SOFT, -1, 0, 0, 0, 0, 0, 0, "software emulated floating point" }, |
647 | { 0, MIPS_R2360, -1, 0, 0, 0, 0, 0, 0, "MIPS R2360 Floating Point Board" }, | | 647 | { 0, MIPS_R2360, -1, 0, 0, 0, 0, 0, 0, "MIPS R2360 Floating Point Board" }, |
648 | { 0, MIPS_R2010, -1, 0, 0, 0, 0, 0, 0, "MIPS R2010 FPC" }, | | 648 | { 0, MIPS_R2010, -1, 0, 0, 0, 0, 0, 0, "MIPS R2010 FPC" }, |
649 | { 0, MIPS_R3010, -1, 0, 0, 0, 0, 0, 0, "MIPS R3010 FPC" }, | | 649 | { 0, MIPS_R3010, -1, 0, 0, 0, 0, 0, 0, "MIPS R3010 FPC" }, |
650 | { 0, MIPS_R6010, -1, 0, 0, 0, 0, 0, 0, "MIPS R6010 FPC" }, | | 650 | { 0, MIPS_R6010, -1, 0, 0, 0, 0, 0, 0, "MIPS R6010 FPC" }, |
651 | { 0, MIPS_R4010, -1, 0, 0, 0, 0, 0, 0, "MIPS R4010 FPC" }, | | 651 | { 0, MIPS_R4010, -1, 0, 0, 0, 0, 0, 0, "MIPS R4010 FPC" }, |
652 | }; | | 652 | }; |
653 | | | 653 | |
654 | /* | | 654 | /* |
655 | * Company ID's are not sparse (yet), this array is indexed directly | | 655 | * Company ID's are not sparse (yet), this array is indexed directly |
656 | * by pridtab->cpu_cid. | | 656 | * by pridtab->cpu_cid. |
657 | */ | | 657 | */ |
658 | static const char * const cidnames[] = { | | 658 | static const char * const cidnames[] = { |
659 | "Prehistoric", | | 659 | "Prehistoric", |
660 | "MIPS", /* or "MIPS Technologies, Inc. */ | | 660 | "MIPS", /* or "MIPS Technologies, Inc. */ |
661 | "Broadcom", /* or "Broadcom Corp." */ | | 661 | "Broadcom", /* or "Broadcom Corp." */ |
662 | "Alchemy", /* or "Alchemy Semiconductor" */ | | 662 | "Alchemy", /* or "Alchemy Semiconductor" */ |
663 | "SiByte", /* or "Broadcom Corp. (SiByte)" */ | | 663 | "SiByte", /* or "Broadcom Corp. (SiByte)" */ |
664 | "SandCraft", | | 664 | "SandCraft", |
665 | "Phillips", | | 665 | "Phillips", |
666 | "Toshiba or Microsoft", | | 666 | "Toshiba or Microsoft", |
667 | "LSI", | | 667 | "LSI", |
668 | "(unannounced)", | | 668 | "(unannounced)", |
669 | "(unannounced)", | | 669 | "(unannounced)", |
670 | "Lexra", | | 670 | "Lexra", |
671 | "RMI", | | 671 | "RMI", |
672 | }; | | 672 | }; |
673 | #define ncidnames __arraycount(cidnames) | | 673 | #define ncidnames __arraycount(cidnames) |
674 | | | 674 | |
675 | #if defined(MIPS1) | | 675 | #if defined(MIPS1) |
676 | /* | | 676 | /* |
677 | * MIPS-I locore function vector | | 677 | * MIPS-I locore function vector |
678 | */ | | 678 | */ |
679 | | | 679 | |
680 | static void | | 680 | static void |
681 | mips1_vector_init(const struct splsw *splsw) | | 681 | mips1_vector_init(const struct splsw *splsw) |
682 | { | | 682 | { |
683 | extern char mips1_utlb_miss[], mips1_utlb_miss_end[]; | | 683 | extern char mips1_utlb_miss[], mips1_utlb_miss_end[]; |
684 | extern char mips1_exception[], mips1_exception_end[]; | | 684 | extern char mips1_exception[], mips1_exception_end[]; |
685 | | | 685 | |
686 | /* | | 686 | /* |
687 | * Copy down exception vector code. | | 687 | * Copy down exception vector code. |
688 | */ | | 688 | */ |
689 | if (mips1_utlb_miss_end - mips1_utlb_miss > 0x80) | | 689 | if (mips1_utlb_miss_end - mips1_utlb_miss > 0x80) |
690 | panic("startup: UTLB vector code too large"); | | 690 | panic("startup: UTLB vector code too large"); |
691 | if (mips1_exception_end - mips1_exception > 0x80) | | 691 | if (mips1_exception_end - mips1_exception > 0x80) |
692 | panic("startup: general exception vector code too large"); | | 692 | panic("startup: general exception vector code too large"); |
693 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips1_utlb_miss, | | 693 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips1_utlb_miss, |
694 | mips1_exception_end - mips1_utlb_miss); | | 694 | mips1_exception_end - mips1_utlb_miss); |
695 | | | 695 | |
696 | /* | | 696 | /* |
697 | * Copy locore-function vector. | | 697 | * Copy locore-function vector. |
698 | */ | | 698 | */ |
699 | mips_locore_jumpvec = mips1_locore_vec; | | 699 | mips_locore_jumpvec = mips1_locore_vec; |
700 | | | 700 | |
701 | /* | | 701 | /* |
702 | * Clear out the I and D caches. | | 702 | * Clear out the I and D caches. |
703 | */ | | 703 | */ |
704 | mips_icache_sync_all(); | | 704 | mips_icache_sync_all(); |
705 | mips_dcache_wbinv_all(); | | 705 | mips_dcache_wbinv_all(); |
706 | } | | 706 | } |
707 | #endif /* MIPS1 */ | | 707 | #endif /* MIPS1 */ |
708 | | | 708 | |
709 | #if defined(MIPS3) | | 709 | #if defined(MIPS3) |
710 | static void | | 710 | static void |
711 | mips3_vector_init(const struct splsw *splsw) | | 711 | mips3_vector_init(const struct splsw *splsw) |
712 | { | | 712 | { |
713 | /* r4000 exception handler address and end */ | | 713 | /* r4000 exception handler address and end */ |
714 | extern char mips3_exception[], mips3_exception_end[]; | | 714 | extern char mips3_exception[], mips3_exception_end[]; |
715 | | | 715 | |
716 | /* TLB miss handler address and end */ | | 716 | /* TLB miss handler address and end */ |
717 | extern char mips3_tlb_miss[]; | | 717 | extern char mips3_tlb_miss[]; |
718 | extern char mips3_xtlb_miss[]; | | 718 | extern char mips3_xtlb_miss[]; |
719 | | | 719 | |
720 | /* Cache error handler */ | | 720 | /* Cache error handler */ |
721 | extern char mips3_cache[]; | | 721 | extern char mips3_cache[]; |
722 | | | 722 | |
723 | /* | | 723 | /* |
724 | * Copy down exception vector code. | | 724 | * Copy down exception vector code. |
725 | */ | | 725 | */ |
726 | | | 726 | |
727 | if (mips3_xtlb_miss - mips3_tlb_miss != 0x80) | | 727 | if (mips3_xtlb_miss - mips3_tlb_miss != 0x80) |
728 | panic("startup: %s vector code not 128 bytes in length", | | 728 | panic("startup: %s vector code not 128 bytes in length", |
729 | "UTLB"); | | 729 | "UTLB"); |
730 | if (mips3_cache - mips3_xtlb_miss != 0x80) | | 730 | if (mips3_cache - mips3_xtlb_miss != 0x80) |
731 | panic("startup: %s vector code not 128 bytes in length", | | 731 | panic("startup: %s vector code not 128 bytes in length", |
732 | "XTLB"); | | 732 | "XTLB"); |
733 | if (mips3_exception - mips3_cache != 0x80) | | 733 | if (mips3_exception - mips3_cache != 0x80) |
734 | panic("startup: %s vector code not 128 bytes in length", | | 734 | panic("startup: %s vector code not 128 bytes in length", |
735 | "Cache error"); | | 735 | "Cache error"); |
736 | if (mips3_exception_end - mips3_exception > 0x80) | | 736 | if (mips3_exception_end - mips3_exception > 0x80) |
737 | panic("startup: %s vector code too large", | | 737 | panic("startup: %s vector code too large", |
738 | "General exception"); | | 738 | "General exception"); |
739 | | | 739 | |
740 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips3_tlb_miss, | | 740 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips3_tlb_miss, |
741 | mips3_exception_end - mips3_tlb_miss); | | 741 | mips3_exception_end - mips3_tlb_miss); |
742 | | | 742 | |
743 | /* | | 743 | /* |
744 | * Copy locore-function vector. | | 744 | * Copy locore-function vector. |
745 | */ | | 745 | */ |
746 | mips_locore_jumpvec = mips3_locore_vec; | | 746 | mips_locore_jumpvec = mips3_locore_vec; |
747 | | | 747 | |
748 | mips_icache_sync_all(); | | 748 | mips_icache_sync_all(); |
749 | mips_dcache_wbinv_all(); | | 749 | mips_dcache_wbinv_all(); |
750 | | | 750 | |
751 | /* Clear BEV in SR so we start handling our own exceptions */ | | 751 | /* Clear BEV in SR so we start handling our own exceptions */ |
752 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 752 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
753 | } | | 753 | } |
754 | #endif /* MIPS3 */ | | 754 | #endif /* MIPS3 */ |
755 | | | 755 | |
756 | #if defined(MIPS3_LOONGSON2) | | 756 | #if defined(MIPS3_LOONGSON2) |
757 | static void | | 757 | static void |
758 | loongson2_vector_init(const struct splsw *splsw) | | 758 | loongson2_vector_init(const struct splsw *splsw) |
759 | { | | 759 | { |
760 | /* r4000 exception handler address and end */ | | 760 | /* r4000 exception handler address and end */ |
761 | extern char loongson2_exception[], loongson2_exception_end[]; | | 761 | extern char loongson2_exception[], loongson2_exception_end[]; |
762 | | | 762 | |
763 | /* TLB miss handler address and end */ | | 763 | /* TLB miss handler address and end */ |
764 | extern char loongson2_tlb_miss[]; | | 764 | extern char loongson2_tlb_miss[]; |
765 | extern char loongson2_xtlb_miss[]; | | 765 | extern char loongson2_xtlb_miss[]; |
766 | | | 766 | |
767 | /* Cache error handler */ | | 767 | /* Cache error handler */ |
768 | extern char loongson2_cache[]; | | 768 | extern char loongson2_cache[]; |
769 | | | 769 | |
770 | /* | | 770 | /* |
771 | * Copy down exception vector code. | | 771 | * Copy down exception vector code. |
772 | */ | | 772 | */ |
773 | | | 773 | |
774 | if (loongson2_xtlb_miss - loongson2_tlb_miss != 0x80) | | 774 | if (loongson2_xtlb_miss - loongson2_tlb_miss != 0x80) |
775 | panic("startup: %s vector code not 128 bytes in length", | | 775 | panic("startup: %s vector code not 128 bytes in length", |
776 | "UTLB"); | | 776 | "UTLB"); |
777 | if (loongson2_cache - loongson2_xtlb_miss != 0x80) | | 777 | if (loongson2_cache - loongson2_xtlb_miss != 0x80) |
778 | panic("startup: %s vector code not 128 bytes in length", | | 778 | panic("startup: %s vector code not 128 bytes in length", |
779 | "XTLB"); | | 779 | "XTLB"); |
780 | if (loongson2_exception - loongson2_cache != 0x80) | | 780 | if (loongson2_exception - loongson2_cache != 0x80) |
781 | panic("startup: %s vector code not 128 bytes in length", | | 781 | panic("startup: %s vector code not 128 bytes in length", |
782 | "Cache error"); | | 782 | "Cache error"); |
783 | if (loongson2_exception_end - loongson2_exception > 0x80) | | 783 | if (loongson2_exception_end - loongson2_exception > 0x80) |
784 | panic("startup: %s vector code too large", | | 784 | panic("startup: %s vector code too large", |
785 | "General exception"); | | 785 | "General exception"); |
786 | | | 786 | |
787 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, loongson2_tlb_miss, | | 787 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, loongson2_tlb_miss, |
788 | loongson2_exception_end - loongson2_tlb_miss); | | 788 | loongson2_exception_end - loongson2_tlb_miss); |
789 | | | 789 | |
790 | /* | | 790 | /* |
791 | * Copy locore-function vector. | | 791 | * Copy locore-function vector. |
792 | */ | | 792 | */ |
793 | mips_locore_jumpvec = loongson2_locore_vec; | | 793 | mips_locore_jumpvec = loongson2_locore_vec; |
794 | | | 794 | |
795 | mips_icache_sync_all(); | | 795 | mips_icache_sync_all(); |
796 | mips_dcache_wbinv_all(); | | 796 | mips_dcache_wbinv_all(); |
797 | | | 797 | |
798 | /* Clear BEV in SR so we start handling our own exceptions */ | | 798 | /* Clear BEV in SR so we start handling our own exceptions */ |
799 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 799 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
800 | } | | 800 | } |
801 | #endif /* MIPS3_LOONGSON2 */ | | 801 | #endif /* MIPS3_LOONGSON2 */ |
802 | | | 802 | |
803 | #if defined(MIPS32) | | 803 | #if defined(MIPS32) |
804 | static void | | 804 | static void |
805 | mips32_vector_init(const struct splsw *splsw) | | 805 | mips32_vector_init(const struct splsw *splsw) |
806 | { | | 806 | { |
807 | /* r4000 exception handler address */ | | 807 | /* r4000 exception handler address */ |
808 | extern char mips32_exception[]; | | 808 | extern char mips32_exception[]; |
809 | | | 809 | |
810 | /* TLB miss handler addresses */ | | 810 | /* TLB miss handler addresses */ |
811 | extern char mips32_tlb_miss[]; | | 811 | extern char mips32_tlb_miss[]; |
812 | | | 812 | |
813 | /* Cache error handler */ | | 813 | /* Cache error handler */ |
814 | extern char mips32_cache[]; | | 814 | extern char mips32_cache[]; |
815 | | | 815 | |
816 | /* MIPS32 interrupt exception handler */ | | 816 | /* MIPS32 interrupt exception handler */ |
817 | extern char mips32_intr[], mips32_intr_end[]; | | 817 | extern char mips32_intr[], mips32_intr_end[]; |
818 | | | 818 | |
819 | /* | | 819 | /* |
820 | * Copy down exception vector code. | | 820 | * Copy down exception vector code. |
821 | */ | | 821 | */ |
822 | | | 822 | |
823 | if (mips32_cache - mips32_tlb_miss != 0x100) | | 823 | if (mips32_cache - mips32_tlb_miss != 0x100) |
824 | panic("startup: %s vector code not 128 bytes in length", | | 824 | panic("startup: %s vector code not 128 bytes in length", |
825 | "UTLB"); | | 825 | "UTLB"); |
826 | if (mips32_exception - mips32_cache != 0x80) | | 826 | if (mips32_exception - mips32_cache != 0x80) |
827 | panic("startup: %s vector code not 128 bytes in length", | | 827 | panic("startup: %s vector code not 128 bytes in length", |
828 | "Cache error"); | | 828 | "Cache error"); |
829 | if (mips32_intr - mips32_exception != 0x80) | | 829 | if (mips32_intr - mips32_exception != 0x80) |
830 | panic("startup: %s vector code not 128 bytes in length", | | 830 | panic("startup: %s vector code not 128 bytes in length", |
831 | "General exception"); | | 831 | "General exception"); |
832 | if (mips32_intr_end - mips32_intr > 0x80) | | 832 | if (mips32_intr_end - mips32_intr > 0x80) |
833 | panic("startup: %s vector code too large", | | 833 | panic("startup: %s vector code too large", |
834 | "interrupt exception"); | | 834 | "interrupt exception"); |
835 | | | 835 | |
836 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32_tlb_miss, | | 836 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32_tlb_miss, |
837 | mips32_intr_end - mips32_tlb_miss); | | 837 | mips32_intr_end - mips32_tlb_miss); |
838 | | | 838 | |
839 | /* | | 839 | /* |
840 | * Copy locore-function vector. | | 840 | * Copy locore-function vector. |
841 | */ | | 841 | */ |
842 | mips_locore_jumpvec = mips32_locore_vec; | | 842 | mips_locore_jumpvec = mips32_locore_vec; |
843 | | | 843 | |
844 | mips_icache_sync_all(); | | 844 | mips_icache_sync_all(); |
845 | mips_dcache_wbinv_all(); | | 845 | mips_dcache_wbinv_all(); |
846 | | | 846 | |
847 | /* Clear BEV in SR so we start handling our own exceptions */ | | 847 | /* Clear BEV in SR so we start handling our own exceptions */ |
848 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 848 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
849 | | | 849 | |
850 | mips_watchpoint_init(); | | 850 | mips_watchpoint_init(); |
851 | } | | 851 | } |
852 | #endif /* MIPS32 */ | | 852 | #endif /* MIPS32 */ |
853 | | | 853 | |
854 | #if defined(MIPS32R2) | | 854 | #if defined(MIPS32R2) |
855 | static void | | 855 | static void |
856 | mips32r2_vector_init(const struct splsw *splsw) | | 856 | mips32r2_vector_init(const struct splsw *splsw) |
857 | { | | 857 | { |
858 | /* r4000 exception handler address */ | | 858 | /* r4000 exception handler address */ |
859 | extern char mips32r2_exception[]; | | 859 | extern char mips32r2_exception[]; |
860 | | | 860 | |
861 | /* TLB miss handler addresses */ | | 861 | /* TLB miss handler addresses */ |
862 | extern char mips32r2_tlb_miss[]; | | 862 | extern char mips32r2_tlb_miss[]; |
863 | | | 863 | |
864 | /* Cache error handler */ | | 864 | /* Cache error handler */ |
865 | extern char mips32r2_cache[]; | | 865 | extern char mips32r2_cache[]; |
866 | | | 866 | |
867 | /* MIPS32 interrupt exception handler */ | | 867 | /* MIPS32 interrupt exception handler */ |
868 | extern char mips32r2_intr[], mips32r2_intr_end[]; | | 868 | extern char mips32r2_intr[], mips32r2_intr_end[]; |
869 | | | 869 | |
870 | /* | | 870 | /* |
871 | * Copy down exception vector code. | | 871 | * Copy down exception vector code. |
872 | */ | | 872 | */ |
873 | if (mips32r2_cache - mips32r2_tlb_miss != 0x100) | | 873 | if (mips32r2_cache - mips32r2_tlb_miss != 0x100) |
874 | panic("startup: %s vector code not 128 bytes in length", | | 874 | panic("startup: %s vector code not 128 bytes in length", |
875 | "UTLB"); | | 875 | "UTLB"); |
876 | if (mips32r2_exception - mips32r2_cache != 0x80) | | 876 | if (mips32r2_exception - mips32r2_cache != 0x80) |
877 | panic("startup: %s vector code not 128 bytes in length", | | 877 | panic("startup: %s vector code not 128 bytes in length", |
878 | "Cache error"); | | 878 | "Cache error"); |
879 | if (mips32r2_intr - mips32r2_exception != 0x80) | | 879 | if (mips32r2_intr - mips32r2_exception != 0x80) |
880 | panic("startup: %s vector code not 128 bytes in length", | | 880 | panic("startup: %s vector code not 128 bytes in length", |
881 | "General exception"); | | 881 | "General exception"); |
882 | if (mips32r2_intr_end - mips32r2_intr > 0x80) | | 882 | if (mips32r2_intr_end - mips32r2_intr > 0x80) |
883 | panic("startup: %s vector code too large", | | 883 | panic("startup: %s vector code too large", |
884 | "interrupt exception"); | | 884 | "interrupt exception"); |
885 | | | 885 | |
886 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32r2_tlb_miss, | | 886 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips32r2_tlb_miss, |
887 | mips32r2_intr_end - mips32r2_tlb_miss); | | 887 | mips32r2_intr_end - mips32r2_tlb_miss); |
888 | | | 888 | |
889 | /* | | 889 | /* |
890 | * Let see if this cpu has DSP V2 ASE... | | 890 | * Let see if this cpu has DSP V2 ASE... |
891 | */ | | 891 | */ |
892 | uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags; | | 892 | uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags; |
893 | if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) { | | 893 | if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) { |
894 | const uint32_t cfg3 = mipsNN_cp0_config3_read(); | | 894 | const uint32_t cfg3 = mipsNN_cp0_config3_read(); |
895 | if (cfg3 & MIPSNN_CFG3_ULRP) { | | 895 | if (cfg3 & MIPSNN_CFG3_ULRP) { |
896 | cp0flags |= MIPS_CP0FL_USERLOCAL; | | 896 | cp0flags |= MIPS_CP0FL_USERLOCAL; |
897 | } | | 897 | } |
898 | if (cfg3 & MIPSNN_CFG3_DSP2P) { | | 898 | if (cfg3 & MIPSNN_CFG3_DSP2P) { |
899 | mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP; | | 899 | mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP; |
900 | } | | 900 | } |
901 | } | | 901 | } |
902 | /* | | 902 | /* |
903 | * If this CPU doesn't have a COP0 USERLOCAL register, at the end | | 903 | * If this CPU doesn't have a COP0 USERLOCAL register, at the end |
904 | * of cpu_switch resume overwrite the instructions which update it. | | 904 | * of cpu_switch resume overwrite the instructions which update it. |
905 | */ | | 905 | */ |
906 | if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) { | | 906 | if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) { |
907 | extern uint32_t mips32r2_cpu_switch_resume[]; | | 907 | extern uint32_t mips32r2_cpu_switch_resume[]; |
908 | for (uint32_t *insnp = mips32r2_cpu_switch_resume;; insnp++) { | | 908 | for (uint32_t *insnp = mips32r2_cpu_switch_resume;; insnp++) { |
909 | KASSERT(insnp[0] != JR_RA); | | 909 | KASSERT(insnp[0] != JR_RA); |
910 | if (insnp[0] == _LOAD_V0_L_PRIVATE_A0 | | 910 | if (insnp[0] == _LOAD_V0_L_PRIVATE_A0 |
911 | && insnp[1] == _MTC0_V0_USERLOCAL) { | | 911 | && insnp[1] == _MTC0_V0_USERLOCAL) { |
912 | insnp[0] = JR_RA; | | 912 | insnp[0] = JR_RA; |
913 | insnp[1] = 0; /* NOP */ | | 913 | insnp[1] = 0; /* NOP */ |
914 | break; | | 914 | break; |
915 | } | | 915 | } |
916 | } | | 916 | } |
917 | } | | 917 | } |
918 | | | 918 | |
919 | /* | | 919 | /* |
920 | * Copy locore-function vector. | | 920 | * Copy locore-function vector. |
921 | */ | | 921 | */ |
922 | mips_locore_jumpvec = mips32r2_locore_vec; | | 922 | mips_locore_jumpvec = mips32r2_locore_vec; |
923 | | | 923 | |
924 | mips_icache_sync_all(); | | 924 | mips_icache_sync_all(); |
925 | mips_dcache_wbinv_all(); | | 925 | mips_dcache_wbinv_all(); |
926 | | | 926 | |
927 | /* Clear BEV in SR so we start handling our own exceptions */ | | 927 | /* Clear BEV in SR so we start handling our own exceptions */ |
928 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 928 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
929 | | | 929 | |
930 | mips_watchpoint_init(); | | 930 | mips_watchpoint_init(); |
931 | } | | 931 | } |
932 | #endif /* MIPS32R2 */ | | 932 | #endif /* MIPS32R2 */ |
933 | | | 933 | |
934 | #if defined(MIPS64) | | 934 | #if defined(MIPS64) |
935 | static void | | 935 | static void |
936 | mips64_vector_init(const struct splsw *splsw) | | 936 | mips64_vector_init(const struct splsw *splsw) |
937 | { | | 937 | { |
938 | /* r4000 exception handler address */ | | 938 | /* r4000 exception handler address */ |
939 | extern char mips64_exception[]; | | 939 | extern char mips64_exception[]; |
940 | | | 940 | |
941 | /* TLB miss handler addresses */ | | 941 | /* TLB miss handler addresses */ |
942 | extern char mips64_tlb_miss[]; | | 942 | extern char mips64_tlb_miss[]; |
943 | extern char mips64_xtlb_miss[]; | | 943 | extern char mips64_xtlb_miss[]; |
944 | | | 944 | |
945 | /* Cache error handler */ | | 945 | /* Cache error handler */ |
946 | extern char mips64_cache[]; | | 946 | extern char mips64_cache[]; |
947 | | | 947 | |
948 | /* MIPS64 interrupt exception handler */ | | 948 | /* MIPS64 interrupt exception handler */ |
949 | extern char mips64_intr[], mips64_intr_end[]; | | 949 | extern char mips64_intr[], mips64_intr_end[]; |
950 | | | 950 | |
951 | /* | | 951 | /* |
952 | * Copy down exception vector code. | | 952 | * Copy down exception vector code. |
953 | */ | | 953 | */ |
954 | | | 954 | |
955 | if (mips64_xtlb_miss - mips64_tlb_miss != 0x80) | | 955 | if (mips64_xtlb_miss - mips64_tlb_miss != 0x80) |
956 | panic("startup: %s vector code not 128 bytes in length", | | 956 | panic("startup: %s vector code not 128 bytes in length", |
957 | "UTLB"); | | 957 | "UTLB"); |
958 | if (mips64_cache - mips64_xtlb_miss != 0x80) | | 958 | if (mips64_cache - mips64_xtlb_miss != 0x80) |
959 | panic("startup: %s vector code not 128 bytes in length", | | 959 | panic("startup: %s vector code not 128 bytes in length", |
960 | "XTLB"); | | 960 | "XTLB"); |
961 | if (mips64_exception - mips64_cache != 0x80) | | 961 | if (mips64_exception - mips64_cache != 0x80) |
962 | panic("startup: %s vector code not 128 bytes in length", | | 962 | panic("startup: %s vector code not 128 bytes in length", |
963 | "Cache error"); | | 963 | "Cache error"); |
964 | if (mips64_intr - mips64_exception != 0x80) | | 964 | if (mips64_intr - mips64_exception != 0x80) |
965 | panic("startup: %s vector code not 128 bytes in length", | | 965 | panic("startup: %s vector code not 128 bytes in length", |
966 | "General exception"); | | 966 | "General exception"); |
967 | if (mips64_intr_end - mips64_intr > 0x80) | | 967 | if (mips64_intr_end - mips64_intr > 0x80) |
968 | panic("startup: %s vector code too large", | | 968 | panic("startup: %s vector code too large", |
969 | "interrupt exception"); | | 969 | "interrupt exception"); |
970 | | | 970 | |
971 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64_tlb_miss, | | 971 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64_tlb_miss, |
972 | mips64_intr_end - mips64_tlb_miss); | | 972 | mips64_intr_end - mips64_tlb_miss); |
973 | | | 973 | |
974 | /* | | 974 | /* |
975 | * Copy locore-function vector. | | 975 | * Copy locore-function vector. |
976 | */ | | 976 | */ |
977 | mips_locore_jumpvec = mips64_locore_vec; | | 977 | mips_locore_jumpvec = mips64_locore_vec; |
978 | | | 978 | |
979 | mips_icache_sync_all(); | | 979 | mips_icache_sync_all(); |
980 | mips_dcache_wbinv_all(); | | 980 | mips_dcache_wbinv_all(); |
981 | | | 981 | |
982 | /* Clear BEV in SR so we start handling our own exceptions */ | | 982 | /* Clear BEV in SR so we start handling our own exceptions */ |
983 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 983 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
984 | | | 984 | |
985 | mips_watchpoint_init(); | | 985 | mips_watchpoint_init(); |
986 | } | | 986 | } |
987 | #endif /* MIPS64 */ | | 987 | #endif /* MIPS64 */ |
988 | | | 988 | |
989 | #if defined(MIPS64R2) | | 989 | #if defined(MIPS64R2) |
990 | static void | | 990 | static void |
991 | mips64r2_vector_init(const struct splsw *splsw) | | 991 | mips64r2_vector_init(const struct splsw *splsw) |
992 | { | | 992 | { |
993 | /* r4000 exception handler address */ | | 993 | /* r4000 exception handler address */ |
994 | extern char mips64r2_exception[]; | | 994 | extern char mips64r2_exception[]; |
995 | | | 995 | |
996 | /* TLB miss handler addresses */ | | 996 | /* TLB miss handler addresses */ |
997 | extern char mips64r2_tlb_miss[]; | | 997 | extern char mips64r2_tlb_miss[]; |
998 | extern char mips64r2_xtlb_miss[]; | | 998 | extern char mips64r2_xtlb_miss[]; |
999 | | | 999 | |
1000 | /* Cache error handler */ | | 1000 | /* Cache error handler */ |
1001 | extern char mips64r2_cache[]; | | 1001 | extern char mips64r2_cache[]; |
1002 | | | 1002 | |
1003 | /* MIPS64 interrupt exception handler */ | | 1003 | /* MIPS64 interrupt exception handler */ |
1004 | extern char mips64r2_intr[], mips64r2_intr_end[]; | | 1004 | extern char mips64r2_intr[], mips64r2_intr_end[]; |
1005 | | | 1005 | |
1006 | /* | | 1006 | /* |
1007 | * Copy down exception vector code. | | 1007 | * Copy down exception vector code. |
1008 | */ | | 1008 | */ |
1009 | | | 1009 | |
1010 | if (mips64r2_xtlb_miss - mips64r2_tlb_miss != 0x80) | | 1010 | if (mips64r2_xtlb_miss - mips64r2_tlb_miss != 0x80) |
1011 | panic("startup: %s vector code not 128 bytes in length", | | 1011 | panic("startup: %s vector code not 128 bytes in length", |
1012 | "UTLB"); | | 1012 | "UTLB"); |
1013 | if (mips64r2_cache - mips64r2_xtlb_miss != 0x80) | | 1013 | if (mips64r2_cache - mips64r2_xtlb_miss != 0x80) |
1014 | panic("startup: %s vector code not 128 bytes in length", | | 1014 | panic("startup: %s vector code not 128 bytes in length", |
1015 | "XTLB"); | | 1015 | "XTLB"); |
1016 | if (mips64r2_exception - mips64r2_cache != 0x80) | | 1016 | if (mips64r2_exception - mips64r2_cache != 0x80) |
1017 | panic("startup: %s vector code not 128 bytes in length", | | 1017 | panic("startup: %s vector code not 128 bytes in length", |
1018 | "Cache error"); | | 1018 | "Cache error"); |
1019 | if (mips64r2_intr - mips64r2_exception != 0x80) | | 1019 | if (mips64r2_intr - mips64r2_exception != 0x80) |
1020 | panic("startup: %s vector code not 128 bytes in length", | | 1020 | panic("startup: %s vector code not 128 bytes in length", |
1021 | "General exception"); | | 1021 | "General exception"); |
1022 | if (mips64r2_intr_end - mips64r2_intr > 0x80) | | 1022 | if (mips64r2_intr_end - mips64r2_intr > 0x80) |
1023 | panic("startup: %s vector code too large", | | 1023 | panic("startup: %s vector code too large", |
1024 | "interrupt exception"); | | 1024 | "interrupt exception"); |
1025 | | | 1025 | |
1026 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64r2_tlb_miss, | | 1026 | memcpy((void *)MIPS_UTLB_MISS_EXC_VEC, mips64r2_tlb_miss, |
1027 | mips64r2_intr_end - mips64r2_tlb_miss); | | 1027 | mips64r2_intr_end - mips64r2_tlb_miss); |
1028 | | | 1028 | |
1029 | /* | | 1029 | /* |
1030 | * Let see if this cpu has DSP V2 ASE... | | 1030 | * Let see if this cpu has DSP V2 ASE... |
1031 | */ | | 1031 | */ |
1032 | uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags; | | 1032 | uint32_t cp0flags = mips_options.mips_cpu->cpu_cp0flags; |
1033 | if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) { | | 1033 | if (mipsNN_cp0_config2_read() & MIPSNN_CFG2_M) { |
1034 | const uint32_t cfg3 = mipsNN_cp0_config3_read(); | | 1034 | const uint32_t cfg3 = mipsNN_cp0_config3_read(); |
1035 | if (cfg3 & MIPSNN_CFG3_ULRP) { | | 1035 | if (cfg3 & MIPSNN_CFG3_ULRP) { |
1036 | cp0flags |= MIPS_CP0FL_USERLOCAL; | | 1036 | cp0flags |= MIPS_CP0FL_USERLOCAL; |
1037 | } | | 1037 | } |
1038 | if (cfg3 & MIPSNN_CFG3_DSP2P) { | | 1038 | if (cfg3 & MIPSNN_CFG3_DSP2P) { |
1039 | mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP; | | 1039 | mips_options.mips_cpu_flags |= CPU_MIPS_HAVE_DSP; |
1040 | } | | 1040 | } |
1041 | } | | 1041 | } |
1042 | | | 1042 | |
1043 | /* | | 1043 | /* |
1044 | * If this CPU doesn't have a COP0 USERLOCAL register, at the end | | 1044 | * If this CPU doesn't have a COP0 USERLOCAL register, at the end |
1045 | * of cpu_switch resume overwrite the instructions which update it. | | 1045 | * of cpu_switch resume overwrite the instructions which update it. |
1046 | */ | | 1046 | */ |
1047 | if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) { | | 1047 | if (!(cp0flags & MIPS_CP0FL_USERLOCAL)) { |
1048 | extern uint32_t mips64r2_cpu_switch_resume[]; | | 1048 | extern uint32_t mips64r2_cpu_switch_resume[]; |
1049 | for (uint32_t *insnp = mips64r2_cpu_switch_resume;; insnp++) { | | 1049 | for (uint32_t *insnp = mips64r2_cpu_switch_resume;; insnp++) { |
1050 | KASSERT(insnp[0] != JR_RA); | | 1050 | KASSERT(insnp[0] != JR_RA); |
1051 | if (insnp[0] == _LOAD_V0_L_PRIVATE_A0 | | 1051 | if (insnp[0] == _LOAD_V0_L_PRIVATE_A0 |
1052 | && insnp[1] == _MTC0_V0_USERLOCAL) { | | 1052 | && insnp[1] == _MTC0_V0_USERLOCAL) { |
1053 | insnp[0] = JR_RA; | | 1053 | insnp[0] = JR_RA; |
1054 | insnp[1] = 0; /* NOP */ | | 1054 | insnp[1] = 0; /* NOP */ |
1055 | break; | | 1055 | break; |
1056 | } | | 1056 | } |
1057 | } | | 1057 | } |
1058 | } | | 1058 | } |
1059 | | | 1059 | |
1060 | /* | | 1060 | /* |
1061 | * Copy locore-function vector. | | 1061 | * Copy locore-function vector. |
1062 | */ | | 1062 | */ |
1063 | mips_locore_jumpvec = mips64r2_locore_vec; | | 1063 | mips_locore_jumpvec = mips64r2_locore_vec; |
1064 | | | 1064 | |
1065 | mips_icache_sync_all(); | | 1065 | mips_icache_sync_all(); |
1066 | mips_dcache_wbinv_all(); | | 1066 | mips_dcache_wbinv_all(); |
1067 | | | 1067 | |
1068 | /* Clear BEV in SR so we start handling our own exceptions */ | | 1068 | /* Clear BEV in SR so we start handling our own exceptions */ |
1069 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); | | 1069 | mips_cp0_status_write(mips_cp0_status_read() & ~MIPS_SR_BEV); |
1070 | | | 1070 | |
1071 | mips_watchpoint_init(); | | 1071 | mips_watchpoint_init(); |
1072 | } | | 1072 | } |
1073 | #endif /* MIPS64R2 */ | | 1073 | #endif /* MIPS64R2 */ |
1074 | | | 1074 | |
1075 | /* | | 1075 | /* |
1076 | * Do all the stuff that locore normally does before calling main(), | | 1076 | * Do all the stuff that locore normally does before calling main(), |
1077 | * that is common to all mips-CPU NetBSD ports. | | 1077 | * that is common to all mips-CPU NetBSD ports. |
1078 | * | | 1078 | * |
1079 | * The principal purpose of this function is to examine the | | 1079 | * The principal purpose of this function is to examine the |
1080 | * variable cpu_id, into which the kernel locore start code | | 1080 | * variable cpu_id, into which the kernel locore start code |
1081 | * writes the CPU ID register, and to then copy appropriate | | 1081 | * writes the CPU ID register, and to then copy appropriate |
1082 | * code into the CPU exception-vector entries and the jump tables | | 1082 | * code into the CPU exception-vector entries and the jump tables |
1083 | * used to hide the differences in cache and TLB handling in | | 1083 | * used to hide the differences in cache and TLB handling in |
1084 | * different MIPS CPUs. | | 1084 | * different MIPS CPUs. |
1085 | * | | 1085 | * |
1086 | * This should be the very first thing called by each port's | | 1086 | * This should be the very first thing called by each port's |
1087 | * init_main() function. | | 1087 | * init_main() function. |
1088 | */ | | 1088 | */ |
1089 | | | 1089 | |
1090 | /* | | 1090 | /* |
1091 | * Initialize the hardware exception vectors, and the jump table used to | | 1091 | * Initialize the hardware exception vectors, and the jump table used to |
1092 | * call locore cache and TLB management functions, based on the kind | | 1092 | * call locore cache and TLB management functions, based on the kind |
1093 | * of CPU the kernel is running on. | | 1093 | * of CPU the kernel is running on. |
1094 | */ | | 1094 | */ |
1095 | void | | 1095 | void |
1096 | mips_vector_init(const struct splsw *splsw, bool multicpu_p) | | 1096 | mips_vector_init(const struct splsw *splsw, bool multicpu_p) |
1097 | { | | 1097 | { |
1098 | struct mips_options * const opts = &mips_options; | | 1098 | struct mips_options * const opts = &mips_options; |
1099 | const struct pridtab *ct; | | 1099 | const struct pridtab *ct; |
1100 | const mips_prid_t cpu_id = opts->mips_cpu_id; | | 1100 | const mips_prid_t cpu_id = opts->mips_cpu_id; |
1101 | | | 1101 | |
1102 | for (ct = cputab; ct->cpu_name != NULL; ct++) { | | 1102 | for (ct = cputab; ct->cpu_name != NULL; ct++) { |
1103 | if (MIPS_PRID_CID(cpu_id) != ct->cpu_cid || | | 1103 | if (MIPS_PRID_CID(cpu_id) != ct->cpu_cid || |
1104 | MIPS_PRID_IMPL(cpu_id) != ct->cpu_pid) | | 1104 | MIPS_PRID_IMPL(cpu_id) != ct->cpu_pid) |
1105 | continue; | | 1105 | continue; |
1106 | if (ct->cpu_rev >= 0 && | | 1106 | if (ct->cpu_rev >= 0 && |
1107 | MIPS_PRID_REV(cpu_id) != ct->cpu_rev) | | 1107 | MIPS_PRID_REV(cpu_id) != ct->cpu_rev) |
1108 | continue; | | 1108 | continue; |
1109 | if (ct->cpu_copts >= 0 && | | 1109 | if (ct->cpu_copts >= 0 && |
1110 | MIPS_PRID_COPTS(cpu_id) != ct->cpu_copts) | | 1110 | MIPS_PRID_COPTS(cpu_id) != ct->cpu_copts) |
1111 | continue; | | 1111 | continue; |
1112 | | | 1112 | |
1113 | opts->mips_cpu = ct; | | 1113 | opts->mips_cpu = ct; |
1114 | opts->mips_cpu_arch = ct->cpu_isa; | | 1114 | opts->mips_cpu_arch = ct->cpu_isa; |
1115 | opts->mips_num_tlb_entries = ct->cpu_ntlb; | | 1115 | opts->mips_num_tlb_entries = ct->cpu_ntlb; |
1116 | break; | | 1116 | break; |
1117 | } | | 1117 | } |
1118 | | | 1118 | |
1119 | if (opts->mips_cpu == NULL) | | 1119 | if (opts->mips_cpu == NULL) |
1120 | panic("CPU type (0x%x) not supported", cpu_id); | | 1120 | panic("CPU type (0x%x) not supported", cpu_id); |
1121 | | | 1121 | |
1122 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 | | 1122 | #if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 |
1123 | if (MIPS_PRID_CID(cpu_id) != 0) { | | 1123 | if (MIPS_PRID_CID(cpu_id) != 0) { |
1124 | /* MIPS32/MIPS64, use coprocessor 0 config registers */ | | 1124 | /* MIPS32/MIPS64, use coprocessor 0 config registers */ |
1125 | uint32_t cfg, cfg1; | | 1125 | uint32_t cfg, cfg1; |
1126 | | | 1126 | |
1127 | cfg = mips3_cp0_config_read(); | | 1127 | cfg = mips3_cp0_config_read(); |
1128 | cfg1 = mipsNN_cp0_config1_read(); | | 1128 | cfg1 = mipsNN_cp0_config1_read(); |
1129 | | | 1129 | |
1130 | /* pick CPU type */ | | 1130 | /* pick CPU type */ |
1131 | switch (MIPSNN_GET(CFG_AT, cfg)) { | | 1131 | switch (MIPSNN_GET(CFG_AT, cfg)) { |
1132 | case MIPSNN_CFG_AT_MIPS32: | | 1132 | case MIPSNN_CFG_AT_MIPS32: |
1133 | opts->mips_cpu_arch = CPU_ARCH_MIPS32; | | 1133 | opts->mips_cpu_arch = CPU_ARCH_MIPS32; |
1134 | break; | | 1134 | break; |
1135 | case MIPSNN_CFG_AT_MIPS64: | | 1135 | case MIPSNN_CFG_AT_MIPS64: |
1136 | opts->mips_cpu_arch = CPU_ARCH_MIPS64; | | 1136 | opts->mips_cpu_arch = CPU_ARCH_MIPS64; |
1137 | break; | | 1137 | break; |
1138 | case MIPSNN_CFG_AT_MIPS64S: | | 1138 | case MIPSNN_CFG_AT_MIPS64S: |
1139 | default: | | 1139 | default: |
1140 | panic("MIPS32/64 architecture type %d not supported", | | 1140 | panic("MIPS32/64 architecture type %d not supported", |
1141 | MIPSNN_GET(CFG_AT, cfg)); | | 1141 | MIPSNN_GET(CFG_AT, cfg)); |
1142 | } | | 1142 | } |
1143 | | | 1143 | |
1144 | switch (MIPSNN_GET(CFG_AR, cfg)) { | | 1144 | switch (MIPSNN_GET(CFG_AR, cfg)) { |
1145 | case MIPSNN_CFG_AR_REV1: | | 1145 | case MIPSNN_CFG_AR_REV1: |
1146 | break; | | 1146 | break; |
1147 | case MIPSNN_CFG_AR_REV2: | | 1147 | case MIPSNN_CFG_AR_REV2: |
1148 | opts->mips_cpu_arch += CPU_ARCH_MIPS32R2 - CPU_ARCH_MIPS32; | | 1148 | opts->mips_cpu_arch += CPU_ARCH_MIPS32R2 - CPU_ARCH_MIPS32; |
1149 | break; | | 1149 | break; |
1150 | default: | | 1150 | default: |
1151 | printf("WARNING: MIPS32/64 arch revision %d " | | 1151 | printf("WARNING: MIPS32/64 arch revision %d " |
1152 | "unknown!\n", MIPSNN_GET(CFG_AR, cfg)); | | 1152 | "unknown!\n", MIPSNN_GET(CFG_AR, cfg)); |
1153 | break; | | 1153 | break; |
1154 | } | | 1154 | } |
1155 | | | 1155 | |
1156 | /* figure out MMU type (and number of TLB entries) */ | | 1156 | /* figure out MMU type (and number of TLB entries) */ |
1157 | switch (MIPSNN_GET(CFG_MT, cfg)) { | | 1157 | switch (MIPSNN_GET(CFG_MT, cfg)) { |
1158 | case MIPSNN_CFG_MT_TLB: | | 1158 | case MIPSNN_CFG_MT_TLB: |
1159 | opts->mips_num_tlb_entries = MIPSNN_CFG1_MS(cfg1); | | 1159 | opts->mips_num_tlb_entries = MIPSNN_CFG1_MS(cfg1); |
1160 | break; | | 1160 | break; |
1161 | case MIPSNN_CFG_MT_NONE: | | 1161 | case MIPSNN_CFG_MT_NONE: |
1162 | case MIPSNN_CFG_MT_BAT: | | 1162 | case MIPSNN_CFG_MT_BAT: |
1163 | case MIPSNN_CFG_MT_FIXED: | | 1163 | case MIPSNN_CFG_MT_FIXED: |
1164 | default: | | 1164 | default: |
1165 | panic("MIPS32/64 MMU type %d not supported", | | 1165 | panic("MIPS32/64 MMU type %d not supported", |
1166 | MIPSNN_GET(CFG_MT, cfg)); | | 1166 | MIPSNN_GET(CFG_MT, cfg)); |
1167 | } | | 1167 | } |
1168 | } | | 1168 | } |
1169 | #endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ | | 1169 | #endif /* (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ |
1170 | | | 1170 | |
1171 | if (opts->mips_cpu_arch < 1) | | 1171 | if (opts->mips_cpu_arch < 1) |
1172 | panic("Unknown CPU ISA for CPU type 0x%x", cpu_id); | | 1172 | panic("Unknown CPU ISA for CPU type 0x%x", cpu_id); |
1173 | if (opts->mips_num_tlb_entries < 1) | | 1173 | if (opts->mips_num_tlb_entries < 1) |
1174 | panic("Unknown number of TLBs for CPU type 0x%x", cpu_id); | | 1174 | panic("Unknown number of TLBs for CPU type 0x%x", cpu_id); |
1175 | | | 1175 | |
1176 | /* | | 1176 | /* |
1177 | * Check CPU-specific flags. | | 1177 | * Check CPU-specific flags. |
1178 | */ | | 1178 | */ |
1179 | opts->mips_cpu_flags = opts->mips_cpu->cpu_flags; | | 1179 | opts->mips_cpu_flags = opts->mips_cpu->cpu_flags; |
1180 | opts->mips_has_r4k_mmu = (opts->mips_cpu_flags & CPU_MIPS_R4K_MMU) != 0; | | 1180 | opts->mips_has_r4k_mmu = (opts->mips_cpu_flags & CPU_MIPS_R4K_MMU) != 0; |
1181 | opts->mips_has_llsc = (opts->mips_cpu_flags & CPU_MIPS_NO_LLSC) == 0; | | 1181 | opts->mips_has_llsc = (opts->mips_cpu_flags & CPU_MIPS_NO_LLSC) == 0; |
1182 | #if defined(MIPS3_4100) | | 1182 | #if defined(MIPS3_4100) |
1183 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100) | | 1183 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100) |
1184 | opts->mips3_pg_shift = MIPS3_4100_PG_SHIFT; | | 1184 | opts->mips3_pg_shift = MIPS3_4100_PG_SHIFT; |
1185 | else | | 1185 | else |
1186 | #endif | | 1186 | #endif |
1187 | opts->mips3_pg_shift = MIPS3_DEFAULT_PG_SHIFT; | | 1187 | opts->mips3_pg_shift = MIPS3_DEFAULT_PG_SHIFT; |
1188 | | | 1188 | |
1189 | if (opts->mips_cpu_flags & CPU_MIPS_HAVE_SPECIAL_CCA) { | | 1189 | if (opts->mips_cpu_flags & CPU_MIPS_HAVE_SPECIAL_CCA) { |
1190 | uint32_t cca; | | 1190 | uint32_t cca; |
1191 | | | 1191 | |
1192 | cca = (opts->mips_cpu_flags & CPU_MIPS_CACHED_CCA_MASK) >> | | 1192 | cca = (opts->mips_cpu_flags & CPU_MIPS_CACHED_CCA_MASK) >> |
1193 | CPU_MIPS_CACHED_CCA_SHIFT; | | 1193 | CPU_MIPS_CACHED_CCA_SHIFT; |
1194 | opts->mips3_pg_cached = MIPS3_CCA_TO_PG(cca); | | 1194 | opts->mips3_pg_cached = MIPS3_CCA_TO_PG(cca); |
1195 | #ifdef _LP64 | | 1195 | #ifdef _LP64 |
1196 | opts->mips3_xkphys_cached = MIPS_PHYS_TO_XKPHYS(cca, 0); | | 1196 | opts->mips3_xkphys_cached = MIPS_PHYS_TO_XKPHYS(cca, 0); |
1197 | #endif | | 1197 | #endif |
1198 | } else { | | 1198 | } else { |
1199 | opts->mips3_pg_cached = MIPS3_DEFAULT_PG_CACHED; | | 1199 | opts->mips3_pg_cached = MIPS3_DEFAULT_PG_CACHED; |
1200 | #ifdef _LP64 | | 1200 | #ifdef _LP64 |
1201 | opts->mips3_xkphys_cached = MIPS3_DEFAULT_XKPHYS_CACHED; | | 1201 | opts->mips3_xkphys_cached = MIPS3_DEFAULT_XKPHYS_CACHED; |
1202 | #endif | | 1202 | #endif |
1203 | } | | 1203 | } |
1204 | | | 1204 | |
1205 | #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG | | 1205 | #ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG |
1206 | mips_machdep_cache_config(); | | 1206 | mips_machdep_cache_config(); |
1207 | #endif | | 1207 | #endif |
1208 | | | 1208 | |
1209 | /* | | 1209 | /* |
1210 | * if 'splsw' is NULL, use standard SPL with COP0 status/cause | | 1210 | * if 'splsw' is NULL, use standard SPL with COP0 status/cause |
1211 | * otherwise use chip-specific splsw | | 1211 | * otherwise use chip-specific splsw |
1212 | */ | | 1212 | */ |
1213 | if (splsw == NULL) { | | 1213 | if (splsw == NULL) { |
1214 | mips_splsw = std_splsw; | | 1214 | mips_splsw = std_splsw; |
1215 | #ifdef PARANOIA | | 1215 | #ifdef PARANOIA |
1216 | std_splsw_test(); /* only works with std_splsw */ | | 1216 | std_splsw_test(); /* only works with std_splsw */ |
1217 | #endif | | 1217 | #endif |
1218 | } else { | | 1218 | } else { |
1219 | mips_splsw = *splsw; | | 1219 | mips_splsw = *splsw; |
1220 | } | | 1220 | } |
1221 | | | 1221 | |
1222 | /* | | 1222 | /* |
1223 | * Determine cache configuration and initialize our cache | | 1223 | * Determine cache configuration and initialize our cache |
1224 | * frobbing routine function pointers. | | 1224 | * frobbing routine function pointers. |
1225 | */ | | 1225 | */ |
1226 | mips_config_cache(); | | 1226 | mips_config_cache(); |
1227 | | | 1227 | |
1228 | /* | | 1228 | /* |
1229 | * We default to RAS atomic ops since they are the lowest overhead. | | 1229 | * We default to RAS atomic ops since they are the lowest overhead. |
1230 | */ | | 1230 | */ |
1231 | #ifdef MULTIPROCESSOR | | 1231 | #ifdef MULTIPROCESSOR |
1232 | if (multicpu_p) { | | 1232 | if (multicpu_p) { |
1233 | /* | | 1233 | /* |
1234 | * If we could have multiple CPUs active, | | 1234 | * If we could have multiple CPUs active, |
1235 | * use the ll/sc variants. | | 1235 | * use the ll/sc variants. |
1236 | */ | | 1236 | */ |
1237 | mips_locore_atomicvec = mips_llsc_locore_atomicvec; | | 1237 | mips_locore_atomicvec = mips_llsc_locore_atomicvec; |
1238 | } | | 1238 | } |
1239 | #endif | | 1239 | #endif |
1240 | /* | | 1240 | /* |
1241 | * Now initialize our ISA-dependent function vector. | | 1241 | * Now initialize our ISA-dependent function vector. |
1242 | */ | | 1242 | */ |
1243 | switch (opts->mips_cpu_arch) { | | 1243 | switch (opts->mips_cpu_arch) { |
1244 | #if defined(MIPS1) | | 1244 | #if defined(MIPS1) |
1245 | case CPU_ARCH_MIPS1: | | 1245 | case CPU_ARCH_MIPS1: |
1246 | (*mips1_locore_vec.ljv_tlb_invalidate_all)(); | | 1246 | (*mips1_locore_vec.ljv_tlb_invalidate_all)(); |
1247 | mips1_vector_init(splsw); | | 1247 | mips1_vector_init(splsw); |
1248 | mips_locoresw = mips1_locoresw; | | 1248 | mips_locoresw = mips1_locoresw; |
1249 | break; | | 1249 | break; |
1250 | #endif | | 1250 | #endif |
1251 | #if defined(MIPS3) | | 1251 | #if defined(MIPS3) |
1252 | case CPU_ARCH_MIPS3: | | 1252 | case CPU_ARCH_MIPS3: |
1253 | case CPU_ARCH_MIPS4: | | 1253 | case CPU_ARCH_MIPS4: |
1254 | mips3_tlb_probe(); | | 1254 | mips3_tlb_probe(); |
1255 | #if defined(MIPS3_4100) | | 1255 | #if defined(MIPS3_4100) |
1256 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100) | | 1256 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100) |
1257 | mips3_cp0_pg_mask_write(MIPS4100_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1257 | mips3_cp0_pg_mask_write(MIPS4100_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1258 | else | | 1258 | else |
1259 | #endif | | 1259 | #endif |
1260 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1260 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1261 | mips3_cp0_wired_write(0); | | 1261 | mips3_cp0_wired_write(0); |
1262 | #if defined(MIPS3_LOONGSON2) | | 1262 | #if defined(MIPS3_LOONGSON2) |
1263 | if (opts->mips_cpu_flags & CPU_MIPS_LOONGSON2) { | | 1263 | if (opts->mips_cpu_flags & CPU_MIPS_LOONGSON2) { |
1264 | (*loongson2_locore_vec.ljv_tlb_invalidate_all)(); | | 1264 | (*loongson2_locore_vec.ljv_tlb_invalidate_all)(); |
1265 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1265 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1266 | loongson2_vector_init(splsw); | | 1266 | loongson2_vector_init(splsw); |
1267 | mips_locoresw = loongson2_locoresw; | | 1267 | mips_locoresw = loongson2_locoresw; |
1268 | break; | | 1268 | break; |
1269 | } | | 1269 | } |
1270 | #endif /* MIPS3_LOONGSON2 */ | | 1270 | #endif /* MIPS3_LOONGSON2 */ |
1271 | (*mips3_locore_vec.ljv_tlb_invalidate_all)(); | | 1271 | (*mips3_locore_vec.ljv_tlb_invalidate_all)(); |
1272 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1272 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1273 | mips3_vector_init(splsw); | | 1273 | mips3_vector_init(splsw); |
1274 | mips_locoresw = mips3_locoresw; | | 1274 | mips_locoresw = mips3_locoresw; |
1275 | break; | | 1275 | break; |
1276 | #endif /* MIPS3 */ | | 1276 | #endif /* MIPS3 */ |
1277 | #if defined(MIPS32) | | 1277 | #if defined(MIPS32) |
1278 | case CPU_ARCH_MIPS32: | | 1278 | case CPU_ARCH_MIPS32: |
1279 | mips3_tlb_probe(); | | 1279 | mips3_tlb_probe(); |
1280 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1280 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1281 | mips3_cp0_wired_write(0); | | 1281 | mips3_cp0_wired_write(0); |
1282 | (*mips32_locore_vec.ljv_tlb_invalidate_all)(); | | 1282 | (*mips32_locore_vec.ljv_tlb_invalidate_all)(); |
1283 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1283 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1284 | mips32_vector_init(splsw); | | 1284 | mips32_vector_init(splsw); |
1285 | mips_locoresw = mips32_locoresw; | | 1285 | mips_locoresw = mips32_locoresw; |
1286 | break; | | 1286 | break; |
1287 | #endif | | 1287 | #endif |
1288 | #if defined(MIPS32R2) | | 1288 | #if defined(MIPS32R2) |
1289 | case CPU_ARCH_MIPS32R2: | | 1289 | case CPU_ARCH_MIPS32R2: |
1290 | mips3_tlb_probe(); | | 1290 | mips3_tlb_probe(); |
1291 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1291 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1292 | mips3_cp0_wired_write(0); | | 1292 | mips3_cp0_wired_write(0); |
1293 | (*mips32r2_locore_vec.ljv_tlb_invalidate_all)(); | | 1293 | (*mips32r2_locore_vec.ljv_tlb_invalidate_all)(); |
1294 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1294 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1295 | mips32r2_vector_init(splsw); | | 1295 | mips32r2_vector_init(splsw); |
1296 | mips_locoresw = mips32r2_locoresw; | | 1296 | mips_locoresw = mips32r2_locoresw; |
1297 | break; | | 1297 | break; |
1298 | #endif | | 1298 | #endif |
1299 | #if defined(MIPS64) | | 1299 | #if defined(MIPS64) |
1300 | case CPU_ARCH_MIPS64: { | | 1300 | case CPU_ARCH_MIPS64: { |
1301 | mips3_tlb_probe(); | | 1301 | mips3_tlb_probe(); |
1302 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1302 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1303 | mips3_cp0_wired_write(0); | | 1303 | mips3_cp0_wired_write(0); |
1304 | (*mips64_locore_vec.ljv_tlb_invalidate_all)(); | | 1304 | (*mips64_locore_vec.ljv_tlb_invalidate_all)(); |
1305 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1305 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1306 | mips64_vector_init(splsw); | | 1306 | mips64_vector_init(splsw); |
1307 | mips_locoresw = mips64_locoresw; | | 1307 | mips_locoresw = mips64_locoresw; |
1308 | break; | | 1308 | break; |
1309 | } | | 1309 | } |
1310 | #endif | | 1310 | #endif |
1311 | #if defined(MIPS64R2) | | 1311 | #if defined(MIPS64R2) |
1312 | case CPU_ARCH_MIPS64R2: { | | 1312 | case CPU_ARCH_MIPS64R2: { |
1313 | mips3_tlb_probe(); | | 1313 | mips3_tlb_probe(); |
1314 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); | | 1314 | mips3_cp0_pg_mask_write(MIPS3_PG_SIZE_TO_MASK(PAGE_SIZE)); |
1315 | mips3_cp0_wired_write(0); | | 1315 | mips3_cp0_wired_write(0); |
1316 | (*mips64r2_locore_vec.ljv_tlb_invalidate_all)(); | | 1316 | (*mips64r2_locore_vec.ljv_tlb_invalidate_all)(); |
1317 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); | | 1317 | mips3_cp0_wired_write(pmap_tlb0_info.ti_wired); |
1318 | mips64r2_vector_init(splsw); | | 1318 | mips64r2_vector_init(splsw); |
1319 | mips_locoresw = mips64r2_locoresw; | | 1319 | mips_locoresw = mips64r2_locoresw; |
1320 | break; | | 1320 | break; |
1321 | } | | 1321 | } |
1322 | #endif | | 1322 | #endif |
1323 | default: | | 1323 | default: |
1324 | printf("cpu_arch 0x%x: not supported\n", opts->mips_cpu_arch); | | 1324 | printf("cpu_arch 0x%x: not supported\n", opts->mips_cpu_arch); |
1325 | cpu_reboot(RB_HALT, NULL); | | 1325 | cpu_reboot(RB_HALT, NULL); |
1326 | } | | 1326 | } |
1327 | | | 1327 | |
1328 | /* | | 1328 | /* |
1329 | * Now that the splsw and locoresw have been filled in, fixup the | | 1329 | * Now that the splsw and locoresw have been filled in, fixup the |
1330 | * jumps to any stubs to actually jump to the real routines. | | 1330 | * jumps to any stubs to actually jump to the real routines. |
1331 | */ | | 1331 | */ |
1332 | extern uint32_t _ftext[]; | | 1332 | extern uint32_t _ftext[]; |
1333 | extern uint32_t _etext[]; | | 1333 | extern uint32_t _etext[]; |
1334 | mips_fixup_stubs(_ftext, _etext); | | 1334 | mips_fixup_stubs(_ftext, _etext); |
1335 | | | 1335 | |
1336 | #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 | | 1336 | #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 |
1337 | /* | | 1337 | /* |
1338 | * Install power-saving idle routines. | | 1338 | * Install power-saving idle routines. |
1339 | */ | | 1339 | */ |
1340 | if ((opts->mips_cpu_flags & CPU_MIPS_USE_WAIT) && | | 1340 | if ((opts->mips_cpu_flags & CPU_MIPS_USE_WAIT) && |
1341 | !(opts->mips_cpu_flags & CPU_MIPS_NO_WAIT)) | | 1341 | !(opts->mips_cpu_flags & CPU_MIPS_NO_WAIT)) |
1342 | mips_locoresw.lsw_cpu_idle = mips_wait_idle; | | 1342 | mips_locoresw.lsw_cpu_idle = mips_wait_idle; |
1343 | #endif /* (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ | | 1343 | #endif /* (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ |
1344 | } | | 1344 | } |
1345 | | | 1345 | |
1346 | void | | 1346 | void |
1347 | mips_set_wbflush(void (*flush_fn)(void)) | | 1347 | mips_set_wbflush(void (*flush_fn)(void)) |
1348 | { | | 1348 | { |
1349 | mips_locoresw.lsw_wbflush = flush_fn; | | 1349 | mips_locoresw.lsw_wbflush = flush_fn; |
1350 | (*flush_fn)(); | | 1350 | (*flush_fn)(); |
1351 | } | | 1351 | } |
1352 | | | 1352 | |
1353 | #if defined(MIPS3_PLUS) | | 1353 | #if defined(MIPS3_PLUS) |
1354 | static void | | 1354 | static void |
1355 | mips3_tlb_probe(void) | | 1355 | mips3_tlb_probe(void) |
1356 | { | | 1356 | { |
1357 | struct mips_options * const opts = &mips_options; | | 1357 | struct mips_options * const opts = &mips_options; |
1358 | opts->mips3_tlb_pg_mask = mips3_cp0_tlb_page_mask_probe(); | | 1358 | opts->mips3_tlb_pg_mask = mips3_cp0_tlb_page_mask_probe(); |
1359 | if (CPUIS64BITS) { | | 1359 | if (CPUIS64BITS) { |
1360 | opts->mips3_tlb_vpn_mask = mips3_cp0_tlb_entry_hi_probe(); | | 1360 | opts->mips3_tlb_vpn_mask = mips3_cp0_tlb_entry_hi_probe(); |
| | | 1361 | opts->mips3_tlb_vpn_mask |= PAGE_MASK; |
1361 | opts->mips3_tlb_vpn_mask <<= 2; | | 1362 | opts->mips3_tlb_vpn_mask <<= 2; |
1362 | opts->mips3_tlb_vpn_mask >>= 2; | | 1363 | opts->mips3_tlb_vpn_mask >>= 2; |
1363 | opts->mips3_tlb_pfn_mask = mips3_cp0_tlb_entry_lo_probe(); | | 1364 | opts->mips3_tlb_pfn_mask = mips3_cp0_tlb_entry_lo_probe(); |
1364 | #if defined(_LP64) && defined(ENABLE_MIPS_16KB_PAGE) | | 1365 | #if defined(_LP64) && defined(ENABLE_MIPS_16KB_PAGE) |
1365 | /* | | 1366 | /* |
1366 | * 16KB pages could cause our page table being able to address | | 1367 | * 16KB pages could cause our page table being able to address |
1367 | * a larger address space than the actual chip supports. So | | 1368 | * a larger address space than the actual chip supports. So |
1368 | * we need to limit the address space to what it can really | | 1369 | * we need to limit the address space to what it can really |
1369 | * address. | | 1370 | * address. |
1370 | */ | | 1371 | */ |
1371 | if (mips_vm_maxuser_address > opts->mips3_tlb_vpn_mask + 1) | | 1372 | if (mips_vm_maxuser_address > opts->mips3_tlb_vpn_mask + 1) |
1372 | mips_vm_maxuser_address = opts->mips3_tlb_vpn_mask + 1; | | 1373 | mips_vm_maxuser_address = opts->mips3_tlb_vpn_mask + 1; |
1373 | #endif | | 1374 | #endif |
1374 | } | | 1375 | } |
1375 | } | | 1376 | } |
1376 | #endif | | 1377 | #endif |
1377 | | | 1378 | |
1378 | /* | | 1379 | /* |
1379 | * Identify product revision IDs of CPU and FPU. | | 1380 | * Identify product revision IDs of CPU and FPU. |
1380 | */ | | 1381 | */ |
1381 | void | | 1382 | void |
1382 | cpu_identify(device_t dev) | | 1383 | cpu_identify(device_t dev) |
1383 | { | | 1384 | { |
1384 | const struct mips_options * const opts = &mips_options; | | 1385 | const struct mips_options * const opts = &mips_options; |
1385 | const struct mips_cache_info * const mci = &mips_cache_info; | | 1386 | const struct mips_cache_info * const mci = &mips_cache_info; |
1386 | const mips_prid_t cpu_id = opts->mips_cpu_id; | | 1387 | const mips_prid_t cpu_id = opts->mips_cpu_id; |
1387 | const mips_prid_t fpu_id = opts->mips_fpu_id; | | 1388 | const mips_prid_t fpu_id = opts->mips_fpu_id; |
1388 | static const char * const waynames[] = { | | 1389 | static const char * const waynames[] = { |
1389 | "fully set-associative", /* 0 */ | | 1390 | "fully set-associative", /* 0 */ |
1390 | "direct-mapped", /* 1 */ | | 1391 | "direct-mapped", /* 1 */ |
1391 | "2-way set-associative", /* 2 */ | | 1392 | "2-way set-associative", /* 2 */ |
1392 | NULL, /* 3 */ | | 1393 | NULL, /* 3 */ |
1393 | "4-way set-associative", /* 4 */ | | 1394 | "4-way set-associative", /* 4 */ |
1394 | "5-way set-associative", /* 5 */ | | 1395 | "5-way set-associative", /* 5 */ |
1395 | "6-way set-associative", /* 6 */ | | 1396 | "6-way set-associative", /* 6 */ |
1396 | "7-way set-associative", /* 7 */ | | 1397 | "7-way set-associative", /* 7 */ |
1397 | "8-way set-associative", /* 8 */ | | 1398 | "8-way set-associative", /* 8 */ |
1398 | }; | | 1399 | }; |
1399 | #define nwaynames (sizeof(waynames) / sizeof(waynames[0])) | | 1400 | #define nwaynames (sizeof(waynames) / sizeof(waynames[0])) |
1400 | static const char * const wtnames[] = { | | 1401 | static const char * const wtnames[] = { |
1401 | "write-back", | | 1402 | "write-back", |
1402 | "write-through", | | 1403 | "write-through", |
1403 | }; | | 1404 | }; |
1404 | const char *cpuname, *fpuname; | | 1405 | const char *cpuname, *fpuname; |
1405 | int i; | | 1406 | int i; |
1406 | | | 1407 | |
1407 | cpuname = opts->mips_cpu->cpu_name; | | 1408 | cpuname = opts->mips_cpu->cpu_name; |
1408 | | | 1409 | |
1409 | fpuname = NULL; | | 1410 | fpuname = NULL; |
1410 | for (i = 0; i < sizeof(fputab)/sizeof(fputab[0]); i++) { | | 1411 | for (i = 0; i < sizeof(fputab)/sizeof(fputab[0]); i++) { |
1411 | if (MIPS_PRID_CID(fpu_id) == fputab[i].cpu_cid && | | 1412 | if (MIPS_PRID_CID(fpu_id) == fputab[i].cpu_cid && |
1412 | MIPS_PRID_IMPL(fpu_id) == fputab[i].cpu_pid) { | | 1413 | MIPS_PRID_IMPL(fpu_id) == fputab[i].cpu_pid) { |
1413 | fpuname = fputab[i].cpu_name; | | 1414 | fpuname = fputab[i].cpu_name; |
1414 | break; | | 1415 | break; |
1415 | } | | 1416 | } |
1416 | } | | 1417 | } |
1417 | if (fpuname == NULL && MIPS_PRID_IMPL(fpu_id) == MIPS_PRID_IMPL(cpu_id)) | | 1418 | if (fpuname == NULL && MIPS_PRID_IMPL(fpu_id) == MIPS_PRID_IMPL(cpu_id)) |
1418 | fpuname = "built-in FPU"; | | 1419 | fpuname = "built-in FPU"; |
1419 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4700) /* FPU PRid is 0x20 */ | | 1420 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4700) /* FPU PRid is 0x20 */ |
1420 | fpuname = "built-in FPU"; | | 1421 | fpuname = "built-in FPU"; |
1421 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_RC64470) /* FPU PRid is 0x21 */ | | 1422 | if (MIPS_PRID_IMPL(cpu_id) == MIPS_RC64470) /* FPU PRid is 0x21 */ |
1422 | fpuname = "built-in FPU"; | | 1423 | fpuname = "built-in FPU"; |
1423 | | | 1424 | |
1424 | if (opts->mips_cpu->cpu_cid != 0) { | | 1425 | if (opts->mips_cpu->cpu_cid != 0) { |
1425 | if (opts->mips_cpu->cpu_cid <= ncidnames) | | 1426 | if (opts->mips_cpu->cpu_cid <= ncidnames) |
1426 | aprint_normal("%s ", cidnames[opts->mips_cpu->cpu_cid]); | | 1427 | aprint_normal("%s ", cidnames[opts->mips_cpu->cpu_cid]); |
1427 | else { | | 1428 | else { |
1428 | aprint_normal("Unknown Company ID - 0x%x", opts->mips_cpu->cpu_cid); | | 1429 | aprint_normal("Unknown Company ID - 0x%x", opts->mips_cpu->cpu_cid); |
1429 | aprint_normal_dev(dev, ""); | | 1430 | aprint_normal_dev(dev, ""); |
1430 | } | | 1431 | } |
1431 | } | | 1432 | } |
1432 | if (cpuname != NULL) | | 1433 | if (cpuname != NULL) |
1433 | aprint_normal("%s (0x%x)", cpuname, cpu_id); | | 1434 | aprint_normal("%s (0x%x)", cpuname, cpu_id); |
1434 | else | | 1435 | else |
1435 | aprint_normal("unknown CPU type (0x%x)", cpu_id); | | 1436 | aprint_normal("unknown CPU type (0x%x)", cpu_id); |
1436 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC) | | 1437 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC) |
1437 | aprint_normal(" Rev. %d.%d", MIPS_PRID_REV_MAJ(cpu_id), | | 1438 | aprint_normal(" Rev. %d.%d", MIPS_PRID_REV_MAJ(cpu_id), |
1438 | MIPS_PRID_REV_MIN(cpu_id)); | | 1439 | MIPS_PRID_REV_MIN(cpu_id)); |
1439 | else | | 1440 | else |
1440 | aprint_normal(" Rev. %d", MIPS_PRID_REV(cpu_id)); | | 1441 | aprint_normal(" Rev. %d", MIPS_PRID_REV(cpu_id)); |
1441 | | | 1442 | |
1442 | if (fpuname != NULL) | | 1443 | if (fpuname != NULL) |
1443 | aprint_normal(" with %s", fpuname); | | 1444 | aprint_normal(" with %s", fpuname); |
1444 | else | | 1445 | else |
1445 | aprint_normal(" with unknown FPC type (0x%x)", fpu_id); | | 1446 | aprint_normal(" with unknown FPC type (0x%x)", fpu_id); |
1446 | if (opts->mips_fpu_id != 0) { | | 1447 | if (opts->mips_fpu_id != 0) { |
1447 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC) | | 1448 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC) |
1448 | aprint_normal(" Rev. %d.%d", MIPS_PRID_REV_MAJ(fpu_id), | | 1449 | aprint_normal(" Rev. %d.%d", MIPS_PRID_REV_MAJ(fpu_id), |
1449 | MIPS_PRID_REV_MIN(fpu_id)); | | 1450 | MIPS_PRID_REV_MIN(fpu_id)); |
1450 | else | | 1451 | else |
1451 | aprint_normal(" Rev. %d", MIPS_PRID_REV(fpu_id)); | | 1452 | aprint_normal(" Rev. %d", MIPS_PRID_REV(fpu_id)); |
1452 | } | | 1453 | } |
1453 | if (opts->mips_cpu_flags & MIPS_HAS_DSP) { | | 1454 | if (opts->mips_cpu_flags & MIPS_HAS_DSP) { |
1454 | aprint_normal(" and DSPv2"); | | 1455 | aprint_normal(" and DSPv2"); |
1455 | } | | 1456 | } |
1456 | aprint_normal("\n"); | | 1457 | aprint_normal("\n"); |
1457 | | | 1458 | |
1458 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC && | | 1459 | if (MIPS_PRID_CID(cpu_id) == MIPS_PRID_CID_PREHISTORIC && |
1459 | MIPS_PRID_RSVD(cpu_id) != 0) { | | 1460 | MIPS_PRID_RSVD(cpu_id) != 0) { |
1460 | aprint_normal_dev(dev, "NOTE: top 8 bits of prehistoric PRID not 0!\n"); | | 1461 | aprint_normal_dev(dev, "NOTE: top 8 bits of prehistoric PRID not 0!\n"); |
1461 | aprint_normal_dev(dev, "Please mail port-mips@NetBSD.org with %s " | | 1462 | aprint_normal_dev(dev, "Please mail port-mips@NetBSD.org with %s " |
1462 | "dmesg lines.\n", device_xname(dev)); | | 1463 | "dmesg lines.\n", device_xname(dev)); |
1463 | } | | 1464 | } |
1464 | | | 1465 | |
1465 | KASSERT(mci->mci_picache_ways < nwaynames); | | 1466 | KASSERT(mci->mci_picache_ways < nwaynames); |
1466 | KASSERT(mci->mci_pdcache_ways < nwaynames); | | 1467 | KASSERT(mci->mci_pdcache_ways < nwaynames); |
1467 | KASSERT(mci->mci_sicache_ways < nwaynames); | | 1468 | KASSERT(mci->mci_sicache_ways < nwaynames); |
1468 | KASSERT(mci->mci_sdcache_ways < nwaynames); | | 1469 | KASSERT(mci->mci_sdcache_ways < nwaynames); |
1469 | | | 1470 | |
1470 | switch (opts->mips_cpu_arch) { | | 1471 | switch (opts->mips_cpu_arch) { |
1471 | #if defined(MIPS1) | | 1472 | #if defined(MIPS1) |
1472 | case CPU_ARCH_MIPS1: | | 1473 | case CPU_ARCH_MIPS1: |
1473 | if (mci->mci_picache_size) | | 1474 | if (mci->mci_picache_size) |
1474 | aprint_normal_dev(dev, "%dKB/%dB %s Instruction cache, " | | 1475 | aprint_normal_dev(dev, "%dKB/%dB %s Instruction cache, " |
1475 | "%d TLB entries\n", mci->mci_picache_size / 1024, | | 1476 | "%d TLB entries\n", mci->mci_picache_size / 1024, |
1476 | mci->mci_picache_line_size, waynames[mci->mci_picache_ways], | | 1477 | mci->mci_picache_line_size, waynames[mci->mci_picache_ways], |
1477 | opts->mips_num_tlb_entries); | | 1478 | opts->mips_num_tlb_entries); |
1478 | else | | 1479 | else |
1479 | aprint_normal_dev(dev, "%d TLB entries\n", | | 1480 | aprint_normal_dev(dev, "%d TLB entries\n", |
1480 | opts->mips_num_tlb_entries); | | 1481 | opts->mips_num_tlb_entries); |
1481 | if (mci->mci_pdcache_size) | | 1482 | if (mci->mci_pdcache_size) |
1482 | aprint_normal_dev(dev, "%dKB/%dB %s %s Data cache\n", | | 1483 | aprint_normal_dev(dev, "%dKB/%dB %s %s Data cache\n", |
1483 | mci->mci_pdcache_size / 1024, mci->mci_pdcache_line_size, | | 1484 | mci->mci_pdcache_size / 1024, mci->mci_pdcache_line_size, |
1484 | waynames[mci->mci_pdcache_ways], | | 1485 | waynames[mci->mci_pdcache_ways], |
1485 | wtnames[mci->mci_pdcache_write_through]); | | 1486 | wtnames[mci->mci_pdcache_write_through]); |
1486 | break; | | 1487 | break; |
1487 | #endif /* MIPS1 */ | | 1488 | #endif /* MIPS1 */ |
1488 | #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 | | 1489 | #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 |
1489 | case CPU_ARCH_MIPS3: | | 1490 | case CPU_ARCH_MIPS3: |
1490 | case CPU_ARCH_MIPS4: | | 1491 | case CPU_ARCH_MIPS4: |
1491 | case CPU_ARCH_MIPS32: | | 1492 | case CPU_ARCH_MIPS32: |
1492 | case CPU_ARCH_MIPS32R2: | | 1493 | case CPU_ARCH_MIPS32R2: |
1493 | case CPU_ARCH_MIPS64: | | 1494 | case CPU_ARCH_MIPS64: |
1494 | case CPU_ARCH_MIPS64R2: { | | 1495 | case CPU_ARCH_MIPS64R2: { |
1495 | const char *sufx = "KMGTPE"; | | 1496 | const char *sufx = "KMGTPE"; |
1496 | uint32_t pg_mask; | | 1497 | uint32_t pg_mask; |
1497 | aprint_normal_dev(dev, "%d TLB entries", opts->mips_num_tlb_entries); | | 1498 | aprint_normal_dev(dev, "%d TLB entries", opts->mips_num_tlb_entries); |
1498 | #if !defined(__mips_o32) | | 1499 | #if !defined(__mips_o32) |
1499 | if (CPUIS64BITS) { | | 1500 | if (CPUIS64BITS) { |
1500 | int64_t pfn_mask; | | 1501 | int64_t pfn_mask; |
1501 | i = ffs(~(opts->mips3_tlb_vpn_mask >> 31)) + 30; | | 1502 | i = ffs(~(opts->mips3_tlb_vpn_mask >> 31)) + 30; |
1502 | aprint_normal(", %d%cB (%d-bit) VAs", | | 1503 | aprint_normal(", %d%cB (%d-bit) VAs", |
1503 | 1 << (i % 10), sufx[(i / 10) - 1], i); | | 1504 | 1 << (i % 10), sufx[(i / 10) - 1], i); |
1504 | for (i = 64, pfn_mask = opts->mips3_tlb_pfn_mask << 6; | | 1505 | for (i = 64, pfn_mask = opts->mips3_tlb_pfn_mask << 6; |
1505 | pfn_mask > 0; i--, pfn_mask <<= 1) | | 1506 | pfn_mask > 0; i--, pfn_mask <<= 1) |
1506 | ; | | 1507 | ; |
1507 | aprint_normal(", %d%cB (%d-bit) PAs", | | 1508 | aprint_normal(", %d%cB (%d-bit) PAs", |
1508 | 1 << (i % 10), sufx[(i / 10) - 1], i); | | 1509 | 1 << (i % 10), sufx[(i / 10) - 1], i); |
1509 | } | | 1510 | } |
1510 | #endif | | 1511 | #endif |
1511 | for (i = 4, pg_mask = opts->mips3_tlb_pg_mask >> 13; | | 1512 | for (i = 4, pg_mask = opts->mips3_tlb_pg_mask >> 13; |
1512 | pg_mask != 0; ) { | | 1513 | pg_mask != 0; ) { |
1513 | if ((pg_mask & 3) != 3) | | 1514 | if ((pg_mask & 3) != 3) |
1514 | break; | | 1515 | break; |
1515 | pg_mask >>= 2; | | 1516 | pg_mask >>= 2; |
1516 | i *= 4; | | 1517 | i *= 4; |
1517 | if (i == 1024) { | | 1518 | if (i == 1024) { |
1518 | i = 1; | | 1519 | i = 1; |
1519 | sufx++; | | 1520 | sufx++; |
1520 | } | | 1521 | } |
1521 | } | | 1522 | } |
1522 | aprint_normal(", %d%cB max page size\n", i, sufx[0]); | | 1523 | aprint_normal(", %d%cB max page size\n", i, sufx[0]); |
1523 | if (mci->mci_picache_size) | | 1524 | if (mci->mci_picache_size) |
1524 | aprint_normal_dev(dev, | | 1525 | aprint_normal_dev(dev, |
1525 | "%dKB/%dB %s L1 instruction cache\n", | | 1526 | "%dKB/%dB %s L1 instruction cache\n", |
1526 | mci->mci_picache_size / 1024, | | 1527 | mci->mci_picache_size / 1024, |
1527 | mci->mci_picache_line_size, waynames[mci->mci_picache_ways]); | | 1528 | mci->mci_picache_line_size, waynames[mci->mci_picache_ways]); |
1528 | if (mci->mci_pdcache_size) | | 1529 | if (mci->mci_pdcache_size) |
1529 | aprint_normal_dev(dev, | | 1530 | aprint_normal_dev(dev, |
1530 | "%dKB/%dB %s %s %sL1 data cache\n", | | 1531 | "%dKB/%dB %s %s %sL1 data cache\n", |
1531 | mci->mci_pdcache_size / 1024, mci->mci_pdcache_line_size, | | 1532 | mci->mci_pdcache_size / 1024, mci->mci_pdcache_line_size, |
1532 | waynames[mci->mci_pdcache_ways], | | 1533 | waynames[mci->mci_pdcache_ways], |
1533 | wtnames[mci->mci_pdcache_write_through], | | 1534 | wtnames[mci->mci_pdcache_write_through], |
1534 | ((opts->mips_cpu_flags & CPU_MIPS_D_CACHE_COHERENT) | | 1535 | ((opts->mips_cpu_flags & CPU_MIPS_D_CACHE_COHERENT) |
1535 | ? "coherent " : "")); | | 1536 | ? "coherent " : "")); |
1536 | if (mci->mci_sdcache_line_size) | | 1537 | if (mci->mci_sdcache_line_size) |
1537 | aprint_normal_dev(dev, | | 1538 | aprint_normal_dev(dev, |
1538 | "%dKB/%dB %s %s L2 %s cache\n", | | 1539 | "%dKB/%dB %s %s L2 %s cache\n", |
1539 | mci->mci_sdcache_size / 1024, mci->mci_sdcache_line_size, | | 1540 | mci->mci_sdcache_size / 1024, mci->mci_sdcache_line_size, |
1540 | waynames[mci->mci_sdcache_ways], | | 1541 | waynames[mci->mci_sdcache_ways], |
1541 | wtnames[mci->mci_sdcache_write_through], | | 1542 | wtnames[mci->mci_sdcache_write_through], |
1542 | mci->mci_scache_unified ? "unified" : "data"); | | 1543 | mci->mci_scache_unified ? "unified" : "data"); |
1543 | break; | | 1544 | break; |
1544 | } | | 1545 | } |
1545 | #endif /* (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ | | 1546 | #endif /* (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */ |
1546 | default: | | 1547 | default: |
1547 | panic("cpu_identify: impossible"); | | 1548 | panic("cpu_identify: impossible"); |
1548 | } | | 1549 | } |
1549 | } | | 1550 | } |
1550 | | | 1551 | |
1551 | /* | | 1552 | /* |
1552 | * Set registers on exec. | | 1553 | * Set registers on exec. |
1553 | * Clear all registers except sp, pc, and t9. | | 1554 | * Clear all registers except sp, pc, and t9. |
1554 | * $sp is set to the stack pointer passed in. $pc is set to the entry | | 1555 | * $sp is set to the stack pointer passed in. $pc is set to the entry |
1555 | * point given by the exec_package passed in, as is $t9 (used for PIC | | 1556 | * point given by the exec_package passed in, as is $t9 (used for PIC |
1556 | * code by the MIPS elf abi). | | 1557 | * code by the MIPS elf abi). |
1557 | */ | | 1558 | */ |
1558 | void | | 1559 | void |
1559 | setregs(struct lwp *l, struct exec_package *pack, vaddr_t stack) | | 1560 | setregs(struct lwp *l, struct exec_package *pack, vaddr_t stack) |
1560 | { | | 1561 | { |
1561 | struct trapframe * const tf = l->l_md.md_utf; | | 1562 | struct trapframe * const tf = l->l_md.md_utf; |
1562 | struct proc * const p = l->l_proc; | | 1563 | struct proc * const p = l->l_proc; |
1563 | | | 1564 | |
1564 | memset(tf, 0, sizeof(struct trapframe)); | | 1565 | memset(tf, 0, sizeof(struct trapframe)); |
1565 | tf->tf_regs[_R_SP] = (intptr_t)stack; | | 1566 | tf->tf_regs[_R_SP] = (intptr_t)stack; |
1566 | tf->tf_regs[_R_PC] = (intptr_t)pack->ep_entry & ~3; | | 1567 | tf->tf_regs[_R_PC] = (intptr_t)pack->ep_entry & ~3; |
1567 | tf->tf_regs[_R_T9] = (intptr_t)pack->ep_entry & ~3; /* abicall requirement */ | | 1568 | tf->tf_regs[_R_T9] = (intptr_t)pack->ep_entry & ~3; /* abicall requirement */ |
1568 | tf->tf_regs[_R_SR] = PSL_USERSET; | | 1569 | tf->tf_regs[_R_SR] = PSL_USERSET; |
1569 | #if !defined(__mips_o32) | | 1570 | #if !defined(__mips_o32) |
1570 | /* | | 1571 | /* |
1571 | * allow 64bit ops in userland for non-O32 ABIs | | 1572 | * allow 64bit ops in userland for non-O32 ABIs |
1572 | */ | | 1573 | */ |
1573 | if (p->p_md.md_abi == _MIPS_BSD_API_N32 | | 1574 | if (p->p_md.md_abi == _MIPS_BSD_API_N32 |
1574 | && (CPUISMIPS64 || CPUISMIPS64R2)) { | | 1575 | && (CPUISMIPS64 || CPUISMIPS64R2)) { |
1575 | tf->tf_regs[_R_SR] |= MIPS_SR_PX; | | 1576 | tf->tf_regs[_R_SR] |= MIPS_SR_PX; |
1576 | } else if (p->p_md.md_abi != _MIPS_BSD_API_O32) { | | 1577 | } else if (p->p_md.md_abi != _MIPS_BSD_API_O32) { |
1577 | tf->tf_regs[_R_SR] |= MIPS_SR_UX; | | 1578 | tf->tf_regs[_R_SR] |= MIPS_SR_UX; |
1578 | } | | 1579 | } |
1579 | if (_MIPS_SIM_NEWABI_P(p->p_md.md_abi)) | | 1580 | if (_MIPS_SIM_NEWABI_P(p->p_md.md_abi)) |
1580 | tf->tf_regs[_R_SR] |= MIPS3_SR_FR; | | 1581 | tf->tf_regs[_R_SR] |= MIPS3_SR_FR; |
1581 | #endif | | 1582 | #endif |
1582 | #ifdef _LP64 | | 1583 | #ifdef _LP64 |
1583 | /* | | 1584 | /* |
1584 | * If we are using a 32-bit ABI on a 64-bit kernel, mark the process | | 1585 | * If we are using a 32-bit ABI on a 64-bit kernel, mark the process |
1585 | * that way. If we aren't, clear it. | | 1586 | * that way. If we aren't, clear it. |
1586 | */ | | 1587 | */ |
1587 | if (p->p_md.md_abi == _MIPS_BSD_API_N32 | | 1588 | if (p->p_md.md_abi == _MIPS_BSD_API_N32 |
1588 | || p->p_md.md_abi == _MIPS_BSD_API_O32) { | | 1589 | || p->p_md.md_abi == _MIPS_BSD_API_O32) { |
1589 | p->p_flag |= PK_32; | | 1590 | p->p_flag |= PK_32; |
1590 | } else { | | 1591 | } else { |
1591 | p->p_flag &= ~PK_32; | | 1592 | p->p_flag &= ~PK_32; |
1592 | } | | 1593 | } |
1593 | #endif | | 1594 | #endif |
1594 | /* | | 1595 | /* |
1595 | * Set up arguments for _start(): | | 1596 | * Set up arguments for _start(): |
1596 | * _start(stack, obj, cleanup, ps_strings); | | 1597 | * _start(stack, obj, cleanup, ps_strings); |
1597 | * | | 1598 | * |
1598 | * Notes: | | 1599 | * Notes: |
1599 | * - obj and cleanup are the auxiliary and termination | | 1600 | * - obj and cleanup are the auxiliary and termination |
1600 | * vectors. They are fixed up by ld.elf_so. | | 1601 | * vectors. They are fixed up by ld.elf_so. |
1601 | * - ps_strings is a NetBSD extension. | | 1602 | * - ps_strings is a NetBSD extension. |
1602 | */ | | 1603 | */ |
1603 | tf->tf_regs[_R_A0] = (intptr_t)stack; | | 1604 | tf->tf_regs[_R_A0] = (intptr_t)stack; |
1604 | tf->tf_regs[_R_A1] = 0; | | 1605 | tf->tf_regs[_R_A1] = 0; |
1605 | tf->tf_regs[_R_A2] = 0; | | 1606 | tf->tf_regs[_R_A2] = 0; |
1606 | tf->tf_regs[_R_A3] = p->p_psstrp; | | 1607 | tf->tf_regs[_R_A3] = p->p_psstrp; |
1607 | | | 1608 | |
1608 | l->l_md.md_ss_addr = 0; | | 1609 | l->l_md.md_ss_addr = 0; |
1609 | } | | 1610 | } |
1610 | | | 1611 | |
1611 | #ifdef __HAVE_BOOTINFO_H | | 1612 | #ifdef __HAVE_BOOTINFO_H |
1612 | /* | | 1613 | /* |
1613 | * Machine dependent system variables. | | 1614 | * Machine dependent system variables. |
1614 | */ | | 1615 | */ |
1615 | static int | | 1616 | static int |
1616 | sysctl_machdep_booted_kernel(SYSCTLFN_ARGS) | | 1617 | sysctl_machdep_booted_kernel(SYSCTLFN_ARGS) |
1617 | { | | 1618 | { |
1618 | struct btinfo_bootpath *bibp; | | 1619 | struct btinfo_bootpath *bibp; |
1619 | struct sysctlnode node; | | 1620 | struct sysctlnode node; |
1620 | | | 1621 | |
1621 | bibp = lookup_bootinfo(BTINFO_BOOTPATH); | | 1622 | bibp = lookup_bootinfo(BTINFO_BOOTPATH); |
1622 | if(!bibp) | | 1623 | if(!bibp) |
1623 | return(ENOENT); /* ??? */ | | 1624 | return(ENOENT); /* ??? */ |
1624 | | | 1625 | |
1625 | node = *rnode; | | 1626 | node = *rnode; |
1626 | node.sysctl_data = bibp->bootpath; | | 1627 | node.sysctl_data = bibp->bootpath; |
1627 | node.sysctl_size = sizeof(bibp->bootpath); | | 1628 | node.sysctl_size = sizeof(bibp->bootpath); |
1628 | return (sysctl_lookup(SYSCTLFN_CALL(&node))); | | 1629 | return (sysctl_lookup(SYSCTLFN_CALL(&node))); |
1629 | } | | 1630 | } |
1630 | #endif | | 1631 | #endif |
1631 | | | 1632 | |
1632 | SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") | | 1633 | SYSCTL_SETUP(sysctl_machdep_setup, "sysctl machdep subtree setup") |
1633 | { | | 1634 | { |
1634 | | | 1635 | |
1635 | sysctl_createv(clog, 0, NULL, NULL, | | 1636 | sysctl_createv(clog, 0, NULL, NULL, |
1636 | CTLFLAG_PERMANENT, | | 1637 | CTLFLAG_PERMANENT, |
1637 | CTLTYPE_NODE, "machdep", NULL, | | 1638 | CTLTYPE_NODE, "machdep", NULL, |
1638 | NULL, 0, NULL, 0, | | 1639 | NULL, 0, NULL, 0, |
1639 | CTL_MACHDEP, CTL_EOL); | | 1640 | CTL_MACHDEP, CTL_EOL); |
1640 | | | 1641 | |
1641 | sysctl_createv(clog, 0, NULL, NULL, | | 1642 | sysctl_createv(clog, 0, NULL, NULL, |
1642 | CTLFLAG_PERMANENT, | | 1643 | CTLFLAG_PERMANENT, |
1643 | CTLTYPE_STRUCT, "console_device", NULL, | | 1644 | CTLTYPE_STRUCT, "console_device", NULL, |
1644 | sysctl_consdev, 0, NULL, sizeof(dev_t), | | 1645 | sysctl_consdev, 0, NULL, sizeof(dev_t), |
1645 | CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); | | 1646 | CTL_MACHDEP, CPU_CONSDEV, CTL_EOL); |
1646 | #ifdef __HAVE_BOOTINFO_H | | 1647 | #ifdef __HAVE_BOOTINFO_H |
1647 | sysctl_createv(clog, 0, NULL, NULL, | | 1648 | sysctl_createv(clog, 0, NULL, NULL, |
1648 | CTLFLAG_PERMANENT, | | 1649 | CTLFLAG_PERMANENT, |
1649 | CTLTYPE_STRING, "booted_kernel", NULL, | | 1650 | CTLTYPE_STRING, "booted_kernel", NULL, |
1650 | sysctl_machdep_booted_kernel, 0, NULL, 0, | | 1651 | sysctl_machdep_booted_kernel, 0, NULL, 0, |
1651 | CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); | | 1652 | CTL_MACHDEP, CPU_BOOTED_KERNEL, CTL_EOL); |
1652 | #endif | | 1653 | #endif |
1653 | sysctl_createv(clog, 0, NULL, NULL, | | 1654 | sysctl_createv(clog, 0, NULL, NULL, |
1654 | CTLFLAG_PERMANENT, | | 1655 | CTLFLAG_PERMANENT, |
1655 | CTLTYPE_STRING, "root_device", NULL, | | 1656 | CTLTYPE_STRING, "root_device", NULL, |
1656 | sysctl_root_device, 0, NULL, 0, | | 1657 | sysctl_root_device, 0, NULL, 0, |
1657 | CTL_MACHDEP, CPU_ROOT_DEVICE, CTL_EOL); | | 1658 | CTL_MACHDEP, CPU_ROOT_DEVICE, CTL_EOL); |
1658 | sysctl_createv(clog, 0, NULL, NULL, | | 1659 | sysctl_createv(clog, 0, NULL, NULL, |
1659 | CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, | | 1660 | CTLFLAG_PERMANENT|CTLFLAG_IMMEDIATE, |
1660 | CTLTYPE_INT, "llsc", NULL, | | 1661 | CTLTYPE_INT, "llsc", NULL, |
1661 | NULL, MIPS_HAS_LLSC, NULL, 0, | | 1662 | NULL, MIPS_HAS_LLSC, NULL, 0, |
1662 | CTL_MACHDEP, CPU_LLSC, CTL_EOL); | | 1663 | CTL_MACHDEP, CPU_LLSC, CTL_EOL); |
1663 | } | | 1664 | } |
1664 | | | 1665 | |
1665 | /* | | 1666 | /* |
1666 | * These are imported from platform-specific code. | | 1667 | * These are imported from platform-specific code. |
1667 | * XXX Should be declared in a header file. | | 1668 | * XXX Should be declared in a header file. |
1668 | */ | | 1669 | */ |
1669 | extern phys_ram_seg_t mem_clusters[]; | | 1670 | extern phys_ram_seg_t mem_clusters[]; |
1670 | extern int mem_cluster_cnt; | | 1671 | extern int mem_cluster_cnt; |
1671 | | | 1672 | |
1672 | /* | | 1673 | /* |
1673 | * These variables are needed by /sbin/savecore. | | 1674 | * These variables are needed by /sbin/savecore. |
1674 | */ | | 1675 | */ |
1675 | u_int32_t dumpmag = 0x8fca0101; /* magic number */ | | 1676 | u_int32_t dumpmag = 0x8fca0101; /* magic number */ |
1676 | int dumpsize = 0; /* pages */ | | 1677 | int dumpsize = 0; /* pages */ |
1677 | long dumplo = 0; /* blocks */ | | 1678 | long dumplo = 0; /* blocks */ |
1678 | | | 1679 | |
1679 | #if 0 | | 1680 | #if 0 |
1680 | struct pcb dumppcb; | | 1681 | struct pcb dumppcb; |
1681 | #endif | | 1682 | #endif |
1682 | | | 1683 | |
1683 | /* | | 1684 | /* |
1684 | * cpu_dumpsize: calculate size of machine-dependent kernel core dump headers. | | 1685 | * cpu_dumpsize: calculate size of machine-dependent kernel core dump headers. |
1685 | */ | | 1686 | */ |
1686 | int | | 1687 | int |
1687 | cpu_dumpsize(void) | | 1688 | cpu_dumpsize(void) |
1688 | { | | 1689 | { |
1689 | int size; | | 1690 | int size; |
1690 | | | 1691 | |
1691 | size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)) + | | 1692 | size = ALIGN(sizeof(kcore_seg_t)) + ALIGN(sizeof(cpu_kcore_hdr_t)) + |
1692 | ALIGN(mem_cluster_cnt * sizeof(phys_ram_seg_t)); | | 1693 | ALIGN(mem_cluster_cnt * sizeof(phys_ram_seg_t)); |
1693 | if (roundup(size, dbtob(1)) != dbtob(1)) | | 1694 | if (roundup(size, dbtob(1)) != dbtob(1)) |
1694 | return (-1); | | 1695 | return (-1); |
1695 | | | 1696 | |
1696 | return (1); | | 1697 | return (1); |
1697 | } | | 1698 | } |
1698 | | | 1699 | |
1699 | /* | | 1700 | /* |
1700 | * cpu_dump_mempagecnt: calculate size of RAM (in pages) to be dumped. | | 1701 | * cpu_dump_mempagecnt: calculate size of RAM (in pages) to be dumped. |
1701 | */ | | 1702 | */ |
1702 | u_long | | 1703 | u_long |
1703 | cpu_dump_mempagecnt(void) | | 1704 | cpu_dump_mempagecnt(void) |
1704 | { | | 1705 | { |
1705 | u_long i, n; | | 1706 | u_long i, n; |
1706 | | | 1707 | |
1707 | n = 0; | | 1708 | n = 0; |
1708 | for (i = 0; i < mem_cluster_cnt; i++) | | 1709 | for (i = 0; i < mem_cluster_cnt; i++) |
1709 | n += atop(mem_clusters[i].size); | | 1710 | n += atop(mem_clusters[i].size); |
1710 | return (n); | | 1711 | return (n); |
1711 | } | | 1712 | } |
1712 | | | 1713 | |
1713 | /* | | 1714 | /* |
1714 | * cpu_dump: dump machine-dependent kernel core dump headers. | | 1715 | * cpu_dump: dump machine-dependent kernel core dump headers. |
1715 | */ | | 1716 | */ |
1716 | int | | 1717 | int |
1717 | cpu_dump(void) | | 1718 | cpu_dump(void) |
1718 | { | | 1719 | { |
1719 | int (*dump)(dev_t, daddr_t, void *, size_t); | | 1720 | int (*dump)(dev_t, daddr_t, void *, size_t); |
1720 | char buf[dbtob(1)]; | | 1721 | char buf[dbtob(1)]; |
1721 | kcore_seg_t *segp; | | 1722 | kcore_seg_t *segp; |
1722 | cpu_kcore_hdr_t *cpuhdrp; | | 1723 | cpu_kcore_hdr_t *cpuhdrp; |
1723 | phys_ram_seg_t *memsegp; | | 1724 | phys_ram_seg_t *memsegp; |
1724 | const struct bdevsw *bdev; | | 1725 | const struct bdevsw *bdev; |
1725 | int i; | | 1726 | int i; |
1726 | | | 1727 | |
1727 | bdev = bdevsw_lookup(dumpdev); | | 1728 | bdev = bdevsw_lookup(dumpdev); |
1728 | if (bdev == NULL) | | 1729 | if (bdev == NULL) |
1729 | return (ENXIO); | | 1730 | return (ENXIO); |
1730 | | | 1731 | |
1731 | dump = bdev->d_dump; | | 1732 | dump = bdev->d_dump; |
1732 | | | 1733 | |
1733 | memset(buf, 0, sizeof buf); | | 1734 | memset(buf, 0, sizeof buf); |
1734 | segp = (kcore_seg_t *)buf; | | 1735 | segp = (kcore_seg_t *)buf; |
1735 | cpuhdrp = (cpu_kcore_hdr_t *)&buf[ALIGN(sizeof(*segp))]; | | 1736 | cpuhdrp = (cpu_kcore_hdr_t *)&buf[ALIGN(sizeof(*segp))]; |
1736 | memsegp = (phys_ram_seg_t *)&buf[ ALIGN(sizeof(*segp)) + | | 1737 | memsegp = (phys_ram_seg_t *)&buf[ ALIGN(sizeof(*segp)) + |
1737 | ALIGN(sizeof(*cpuhdrp))]; | | 1738 | ALIGN(sizeof(*cpuhdrp))]; |
1738 | | | 1739 | |
1739 | /* | | 1740 | /* |
1740 | * Generate a segment header. | | 1741 | * Generate a segment header. |
1741 | */ | | 1742 | */ |
1742 | CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); | | 1743 | CORE_SETMAGIC(*segp, KCORE_MAGIC, MID_MACHINE, CORE_CPU); |
1743 | segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); | | 1744 | segp->c_size = dbtob(1) - ALIGN(sizeof(*segp)); |
1744 | | | 1745 | |
1745 | /* | | 1746 | /* |
1746 | * Add the machine-dependent header info. | | 1747 | * Add the machine-dependent header info. |
1747 | */ | | 1748 | */ |
1748 | if (MIPS_HAS_R4K_MMU) { | | 1749 | if (MIPS_HAS_R4K_MMU) { |
1749 | cpuhdrp->archlevel = 3; | | 1750 | cpuhdrp->archlevel = 3; |
1750 | cpuhdrp->pg_shift = MIPS3_PG_SHIFT; | | 1751 | cpuhdrp->pg_shift = MIPS3_PG_SHIFT; |
1751 | cpuhdrp->pg_frame = MIPS3_PG_FRAME; | | 1752 | cpuhdrp->pg_frame = MIPS3_PG_FRAME; |
1752 | cpuhdrp->pg_v = MIPS3_PG_V; | | 1753 | cpuhdrp->pg_v = MIPS3_PG_V; |
1753 | } else { | | 1754 | } else { |
1754 | cpuhdrp->archlevel = 1; | | 1755 | cpuhdrp->archlevel = 1; |
1755 | cpuhdrp->pg_shift = MIPS1_PG_SHIFT; | | 1756 | cpuhdrp->pg_shift = MIPS1_PG_SHIFT; |
1756 | cpuhdrp->pg_frame = MIPS1_PG_FRAME; | | 1757 | cpuhdrp->pg_frame = MIPS1_PG_FRAME; |
1757 | cpuhdrp->pg_v = MIPS1_PG_V; | | 1758 | cpuhdrp->pg_v = MIPS1_PG_V; |
1758 | } | | 1759 | } |
1759 | cpuhdrp->sysmappa = MIPS_KSEG0_TO_PHYS(Sysmap); | | 1760 | cpuhdrp->sysmappa = MIPS_KSEG0_TO_PHYS(Sysmap); |
1760 | cpuhdrp->sysmapsize = Sysmapsize; | | 1761 | cpuhdrp->sysmapsize = Sysmapsize; |
1761 | cpuhdrp->nmemsegs = mem_cluster_cnt; | | 1762 | cpuhdrp->nmemsegs = mem_cluster_cnt; |
1762 | | | 1763 | |
1763 | /* | | 1764 | /* |
1764 | * Fill in the memory segment descriptors. | | 1765 | * Fill in the memory segment descriptors. |
1765 | */ | | 1766 | */ |
1766 | for (i = 0; i < mem_cluster_cnt; i++) { | | 1767 | for (i = 0; i < mem_cluster_cnt; i++) { |
1767 | memsegp[i].start = mem_clusters[i].start; | | 1768 | memsegp[i].start = mem_clusters[i].start; |
1768 | memsegp[i].size = mem_clusters[i].size; | | 1769 | memsegp[i].size = mem_clusters[i].size; |
1769 | } | | 1770 | } |
1770 | | | 1771 | |
1771 | return (dump(dumpdev, dumplo, (void *)buf, dbtob(1))); | | 1772 | return (dump(dumpdev, dumplo, (void *)buf, dbtob(1))); |
1772 | } | | 1773 | } |
1773 | | | 1774 | |
1774 | /* | | 1775 | /* |
1775 | * This is called by main to set dumplo and dumpsize. | | 1776 | * This is called by main to set dumplo and dumpsize. |
1776 | * Dumps always skip the first CLBYTES of disk space | | 1777 | * Dumps always skip the first CLBYTES of disk space |
1777 | * in case there might be a disk label stored there. | | 1778 | * in case there might be a disk label stored there. |
1778 | * If there is extra space, put dump at the end to | | 1779 | * If there is extra space, put dump at the end to |
1779 | * reduce the chance that swapping trashes it. | | 1780 | * reduce the chance that swapping trashes it. |
1780 | */ | | 1781 | */ |
1781 | void | | 1782 | void |
1782 | cpu_dumpconf(void) | | 1783 | cpu_dumpconf(void) |
1783 | { | | 1784 | { |
1784 | const struct bdevsw *bdev; | | 1785 | const struct bdevsw *bdev; |
1785 | int nblks, dumpblks; /* size of dump area */ | | 1786 | int nblks, dumpblks; /* size of dump area */ |
1786 | | | 1787 | |
1787 | if (dumpdev == NODEV) | | 1788 | if (dumpdev == NODEV) |
1788 | goto bad; | | 1789 | goto bad; |
1789 | bdev = bdevsw_lookup(dumpdev); | | 1790 | bdev = bdevsw_lookup(dumpdev); |
1790 | if (bdev == NULL) { | | 1791 | if (bdev == NULL) { |
1791 | dumpdev = NODEV; | | 1792 | dumpdev = NODEV; |
1792 | goto bad; | | 1793 | goto bad; |
1793 | } | | 1794 | } |
1794 | if (bdev->d_psize == NULL) | | 1795 | if (bdev->d_psize == NULL) |
1795 | goto bad; | | 1796 | goto bad; |
1796 | nblks = (*bdev->d_psize)(dumpdev); | | 1797 | nblks = (*bdev->d_psize)(dumpdev); |
1797 | if (nblks <= ctod(1)) | | 1798 | if (nblks <= ctod(1)) |
1798 | goto bad; | | 1799 | goto bad; |
1799 | | | 1800 | |
1800 | dumpblks = cpu_dumpsize(); | | 1801 | dumpblks = cpu_dumpsize(); |
1801 | if (dumpblks < 0) | | 1802 | if (dumpblks < 0) |
1802 | goto bad; | | 1803 | goto bad; |
1803 | dumpblks += ctod(cpu_dump_mempagecnt()); | | 1804 | dumpblks += ctod(cpu_dump_mempagecnt()); |
1804 | | | 1805 | |
1805 | /* If dump won't fit (incl. room for possible label), punt. */ | | 1806 | /* If dump won't fit (incl. room for possible label), punt. */ |
1806 | if (dumpblks > (nblks - ctod(1))) | | 1807 | if (dumpblks > (nblks - ctod(1))) |
1807 | goto bad; | | 1808 | goto bad; |
1808 | | | 1809 | |
1809 | /* Put dump at end of partition */ | | 1810 | /* Put dump at end of partition */ |
1810 | dumplo = nblks - dumpblks; | | 1811 | dumplo = nblks - dumpblks; |
1811 | | | 1812 | |
1812 | /* dumpsize is in page units, and doesn't include headers. */ | | 1813 | /* dumpsize is in page units, and doesn't include headers. */ |
1813 | dumpsize = cpu_dump_mempagecnt(); | | 1814 | dumpsize = cpu_dump_mempagecnt(); |
1814 | return; | | 1815 | return; |
1815 | | | 1816 | |
1816 | bad: | | 1817 | bad: |
1817 | dumpsize = 0; | | 1818 | dumpsize = 0; |
1818 | } | | 1819 | } |
1819 | | | 1820 | |
1820 | /* | | 1821 | /* |
1821 | * Dump the kernel's image to the swap partition. | | 1822 | * Dump the kernel's image to the swap partition. |
1822 | */ | | 1823 | */ |
1823 | #define BYTES_PER_DUMP PAGE_SIZE | | 1824 | #define BYTES_PER_DUMP PAGE_SIZE |
1824 | | | 1825 | |
1825 | void | | 1826 | void |
1826 | dumpsys(void) | | 1827 | dumpsys(void) |
1827 | { | | 1828 | { |
1828 | u_long totalbytesleft, bytes, i, n, memcl; | | 1829 | u_long totalbytesleft, bytes, i, n, memcl; |
1829 | u_long maddr; | | 1830 | u_long maddr; |
1830 | int psize; | | 1831 | int psize; |
1831 | daddr_t blkno; | | 1832 | daddr_t blkno; |
1832 | const struct bdevsw *bdev; | | 1833 | const struct bdevsw *bdev; |
1833 | int (*dump)(dev_t, daddr_t, void *, size_t); | | 1834 | int (*dump)(dev_t, daddr_t, void *, size_t); |
1834 | int error; | | 1835 | int error; |
1835 | | | 1836 | |
1836 | #if 0 | | 1837 | #if 0 |
1837 | /* Save registers. */ | | 1838 | /* Save registers. */ |
1838 | savectx(&dumppcb); | | 1839 | savectx(&dumppcb); |
1839 | #endif | | 1840 | #endif |
1840 | | | 1841 | |
1841 | if (dumpdev == NODEV) | | 1842 | if (dumpdev == NODEV) |
1842 | return; | | 1843 | return; |
1843 | bdev = bdevsw_lookup(dumpdev); | | 1844 | bdev = bdevsw_lookup(dumpdev); |
1844 | if (bdev == NULL || bdev->d_psize == NULL) | | 1845 | if (bdev == NULL || bdev->d_psize == NULL) |
1845 | return; | | 1846 | return; |
1846 | | | 1847 | |
1847 | /* | | 1848 | /* |
1848 | * For dumps during autoconfiguration, | | 1849 | * For dumps during autoconfiguration, |
1849 | * if dump device has already configured... | | 1850 | * if dump device has already configured... |
1850 | */ | | 1851 | */ |
1851 | if (dumpsize == 0) | | 1852 | if (dumpsize == 0) |
1852 | cpu_dumpconf(); | | 1853 | cpu_dumpconf(); |
1853 | if (dumplo <= 0) { | | 1854 | if (dumplo <= 0) { |
1854 | printf("\ndump to dev %u,%u not possible\n", major(dumpdev), | | 1855 | printf("\ndump to dev %u,%u not possible\n", major(dumpdev), |
1855 | minor(dumpdev)); | | 1856 | minor(dumpdev)); |
1856 | return; | | 1857 | return; |
1857 | } | | 1858 | } |
1858 | printf("\ndumping to dev %u,%u offset %ld\n", major(dumpdev), | | 1859 | printf("\ndumping to dev %u,%u offset %ld\n", major(dumpdev), |
1859 | minor(dumpdev), dumplo); | | 1860 | minor(dumpdev), dumplo); |
1860 | | | 1861 | |
1861 | psize = (*bdev->d_psize)(dumpdev); | | 1862 | psize = (*bdev->d_psize)(dumpdev); |
1862 | printf("dump "); | | 1863 | printf("dump "); |
1863 | if (psize == -1) { | | 1864 | if (psize == -1) { |
1864 | printf("area unavailable\n"); | | 1865 | printf("area unavailable\n"); |
1865 | return; | | 1866 | return; |
1866 | } | | 1867 | } |
1867 | | | 1868 | |
1868 | /* XXX should purge all outstanding keystrokes. */ | | 1869 | /* XXX should purge all outstanding keystrokes. */ |
1869 | | | 1870 | |
1870 | if ((error = cpu_dump()) != 0) | | 1871 | if ((error = cpu_dump()) != 0) |
1871 | goto err; | | 1872 | goto err; |
1872 | | | 1873 | |
1873 | totalbytesleft = ptoa(cpu_dump_mempagecnt()); | | 1874 | totalbytesleft = ptoa(cpu_dump_mempagecnt()); |
1874 | blkno = dumplo + cpu_dumpsize(); | | 1875 | blkno = dumplo + cpu_dumpsize(); |
1875 | dump = bdev->d_dump; | | 1876 | dump = bdev->d_dump; |
1876 | error = 0; | | 1877 | error = 0; |
1877 | | | 1878 | |
1878 | for (memcl = 0; memcl < mem_cluster_cnt; memcl++) { | | 1879 | for (memcl = 0; memcl < mem_cluster_cnt; memcl++) { |
1879 | maddr = mem_clusters[memcl].start; | | 1880 | maddr = mem_clusters[memcl].start; |
1880 | bytes = mem_clusters[memcl].size; | | 1881 | bytes = mem_clusters[memcl].size; |
1881 | | | 1882 | |
1882 | for (i = 0; i < bytes; i += n, totalbytesleft -= n) { | | 1883 | for (i = 0; i < bytes; i += n, totalbytesleft -= n) { |
1883 | void *maddr_va; | | 1884 | void *maddr_va; |
1884 | | | 1885 | |
1885 | /* Print out how many MBs we have left to go. */ | | 1886 | /* Print out how many MBs we have left to go. */ |
1886 | if ((totalbytesleft % (1024*1024)) == 0) | | 1887 | if ((totalbytesleft % (1024*1024)) == 0) |
1887 | printf_nolog("%ld ", | | 1888 | printf_nolog("%ld ", |
1888 | totalbytesleft / (1024 * 1024)); | | 1889 | totalbytesleft / (1024 * 1024)); |
1889 | | | 1890 | |
1890 | /* Limit size for next transfer. */ | | 1891 | /* Limit size for next transfer. */ |
1891 | n = bytes - i; | | 1892 | n = bytes - i; |
1892 | if (n > BYTES_PER_DUMP) | | 1893 | if (n > BYTES_PER_DUMP) |
1893 | n = BYTES_PER_DUMP; | | 1894 | n = BYTES_PER_DUMP; |
1894 | | | 1895 | |
1895 | #ifdef _LP64 | | 1896 | #ifdef _LP64 |
1896 | maddr_va = (void *)MIPS_PHYS_TO_XKPHYS_CACHED(maddr); | | 1897 | maddr_va = (void *)MIPS_PHYS_TO_XKPHYS_CACHED(maddr); |
1897 | #else | | 1898 | #else |
1898 | maddr_va = (void *)MIPS_PHYS_TO_KSEG0(maddr); | | 1899 | maddr_va = (void *)MIPS_PHYS_TO_KSEG0(maddr); |
1899 | #endif | | 1900 | #endif |
1900 | error = (*dump)(dumpdev, blkno, maddr_va, n); | | 1901 | error = (*dump)(dumpdev, blkno, maddr_va, n); |
1901 | if (error) | | 1902 | if (error) |
1902 | goto err; | | 1903 | goto err; |
1903 | maddr += n; | | 1904 | maddr += n; |
1904 | blkno += btodb(n); /* XXX? */ | | 1905 | blkno += btodb(n); /* XXX? */ |
1905 | | | 1906 | |
1906 | /* XXX should look for keystrokes, to cancel. */ | | 1907 | /* XXX should look for keystrokes, to cancel. */ |
1907 | } | | 1908 | } |
1908 | } | | 1909 | } |
1909 | | | 1910 | |
1910 | err: | | 1911 | err: |
1911 | switch (error) { | | 1912 | switch (error) { |
1912 | | | 1913 | |
1913 | case ENXIO: | | 1914 | case ENXIO: |
1914 | printf("device bad\n"); | | 1915 | printf("device bad\n"); |
1915 | break; | | 1916 | break; |
1916 | | | 1917 | |
1917 | case EFAULT: | | 1918 | case EFAULT: |
1918 | printf("device not ready\n"); | | 1919 | printf("device not ready\n"); |
1919 | break; | | 1920 | break; |
1920 | | | 1921 | |
1921 | case EINVAL: | | 1922 | case EINVAL: |
1922 | printf("area improper\n"); | | 1923 | printf("area improper\n"); |
1923 | break; | | 1924 | break; |
1924 | | | 1925 | |
1925 | case EIO: | | 1926 | case EIO: |
1926 | printf("i/o error\n"); | | 1927 | printf("i/o error\n"); |
1927 | break; | | 1928 | break; |
1928 | | | 1929 | |
1929 | case EINTR: | | 1930 | case EINTR: |
1930 | printf("aborted from console\n"); | | 1931 | printf("aborted from console\n"); |
1931 | break; | | 1932 | break; |
1932 | | | 1933 | |
1933 | case 0: | | 1934 | case 0: |
1934 | printf("succeeded\n"); | | 1935 | printf("succeeded\n"); |
1935 | break; | | 1936 | break; |
1936 | | | 1937 | |
1937 | default: | | 1938 | default: |
1938 | printf("error %d\n", error); | | 1939 | printf("error %d\n", error); |
1939 | break; | | 1940 | break; |
1940 | } | | 1941 | } |
1941 | printf("\n\n"); | | 1942 | printf("\n\n"); |
1942 | delay(5000000); /* 5 seconds */ | | 1943 | delay(5000000); /* 5 seconds */ |
1943 | } | | 1944 | } |
1944 | | | 1945 | |
1945 | void | | 1946 | void |
1946 | mips_init_msgbuf(void) | | 1947 | mips_init_msgbuf(void) |
1947 | { | | 1948 | { |
1948 | vsize_t sz = (vsize_t)round_page(MSGBUFSIZE); | | 1949 | vsize_t sz = (vsize_t)round_page(MSGBUFSIZE); |
1949 | vsize_t reqsz = sz; | | 1950 | vsize_t reqsz = sz; |
1950 | u_int bank = vm_nphysseg - 1; | | 1951 | u_int bank = vm_nphysseg - 1; |
1951 | struct vm_physseg *vps = VM_PHYSMEM_PTR(bank); | | 1952 | struct vm_physseg *vps = VM_PHYSMEM_PTR(bank); |
1952 | #ifndef _LP64 | | 1953 | #ifndef _LP64 |
1953 | /* | | 1954 | /* |
1954 | * Fist the physical segment that can be mapped to KSEG0 | | 1955 | * Fist the physical segment that can be mapped to KSEG0 |
1955 | */ | | 1956 | */ |
1956 | for (; vps >= vm_physmem; vps--, bank--) { | | 1957 | for (; vps >= vm_physmem; vps--, bank--) { |
1957 | if (vps->avail_start + atop(sz) <= atop(MIPS_PHYS_MASK)) | | 1958 | if (vps->avail_start + atop(sz) <= atop(MIPS_PHYS_MASK)) |
1958 | break; | | 1959 | break; |
1959 | } | | 1960 | } |
1960 | #endif | | 1961 | #endif |
1961 | | | 1962 | |
1962 | /* shrink so that it'll fit in the last segment */ | | 1963 | /* shrink so that it'll fit in the last segment */ |
1963 | if ((vps->avail_end - vps->avail_start) < atop(sz)) | | 1964 | if ((vps->avail_end - vps->avail_start) < atop(sz)) |
1964 | sz = ptoa(vps->avail_end - vps->avail_start); | | 1965 | sz = ptoa(vps->avail_end - vps->avail_start); |
1965 | | | 1966 | |
1966 | vps->end -= atop(sz); | | 1967 | vps->end -= atop(sz); |
1967 | vps->avail_end -= atop(sz); | | 1968 | vps->avail_end -= atop(sz); |
1968 | #ifdef _LP64 | | 1969 | #ifdef _LP64 |
1969 | msgbufaddr = (void *) MIPS_PHYS_TO_XKPHYS_CACHED(ptoa(vps->end)); | | 1970 | msgbufaddr = (void *) MIPS_PHYS_TO_XKPHYS_CACHED(ptoa(vps->end)); |
1970 | #else | | 1971 | #else |
1971 | msgbufaddr = (void *) MIPS_PHYS_TO_KSEG0(ptoa(vps->end)); | | 1972 | msgbufaddr = (void *) MIPS_PHYS_TO_KSEG0(ptoa(vps->end)); |
1972 | #endif | | 1973 | #endif |
1973 | initmsgbuf(msgbufaddr, sz); | | 1974 | initmsgbuf(msgbufaddr, sz); |
1974 | | | 1975 | |
1975 | /* Remove the [last] segment if it now has no pages. */ | | 1976 | /* Remove the [last] segment if it now has no pages. */ |
1976 | if (vps->start == vps->end) { | | 1977 | if (vps->start == vps->end) { |
1977 | for (vm_nphysseg--; bank < vm_nphysseg - 1; bank++) { | | 1978 | for (vm_nphysseg--; bank < vm_nphysseg - 1; bank++) { |
1978 | VM_PHYSMEM_PTR_SWAP(bank, bank + 1); | | 1979 | VM_PHYSMEM_PTR_SWAP(bank, bank + 1); |
1979 | } | | 1980 | } |
1980 | } | | 1981 | } |
1981 | | | 1982 | |
1982 | /* warn if the message buffer had to be shrunk */ | | 1983 | /* warn if the message buffer had to be shrunk */ |
1983 | if (sz != reqsz) | | 1984 | if (sz != reqsz) |
1984 | printf("WARNING: %"PRIdVSIZE" bytes not available for msgbuf " | | 1985 | printf("WARNING: %"PRIdVSIZE" bytes not available for msgbuf " |
1985 | "in last cluster (%"PRIdVSIZE" used)\n", reqsz, sz); | | 1986 | "in last cluster (%"PRIdVSIZE" used)\n", reqsz, sz); |
1986 | } | | 1987 | } |
1987 | | | 1988 | |
1988 | void | | 1989 | void |
1989 | mips_init_lwp0_uarea(void) | | 1990 | mips_init_lwp0_uarea(void) |
1990 | { | | 1991 | { |
1991 | struct lwp * const l = &lwp0; | | 1992 | struct lwp * const l = &lwp0; |
1992 | vaddr_t v; | | 1993 | vaddr_t v; |
1993 | | | 1994 | |
1994 | if (l->l_addr == NULL) { | | 1995 | if (l->l_addr == NULL) { |
1995 | v = uvm_pageboot_alloc(USPACE); | | 1996 | v = uvm_pageboot_alloc(USPACE); |
1996 | uvm_lwp_setuarea(&lwp0, v); | | 1997 | uvm_lwp_setuarea(&lwp0, v); |
1997 | } else { | | 1998 | } else { |
1998 | v = (vaddr_t)l->l_addr; | | 1999 | v = (vaddr_t)l->l_addr; |
1999 | } | | 2000 | } |
2000 | | | 2001 | |
2001 | l->l_md.md_utf = (struct trapframe *)(v + USPACE) - 1; | | 2002 | l->l_md.md_utf = (struct trapframe *)(v + USPACE) - 1; |
2002 | struct pcb * const pcb = lwp_getpcb(l); | | 2003 | struct pcb * const pcb = lwp_getpcb(l); |
2003 | /* | | 2004 | /* |
2004 | * Now zero out the only two areas of the uarea that we care about. | | 2005 | * Now zero out the only two areas of the uarea that we care about. |
2005 | */ | | 2006 | */ |
2006 | memset(l->l_md.md_utf, 0, sizeof(*l->l_md.md_utf)); | | 2007 | memset(l->l_md.md_utf, 0, sizeof(*l->l_md.md_utf)); |
2007 | memset(pcb, 0, sizeof(*pcb)); | | 2008 | memset(pcb, 0, sizeof(*pcb)); |
2008 | | | 2009 | |
2009 | pcb->pcb_context.val[_L_SR] = MIPS_SR_INT_IE | | 2010 | pcb->pcb_context.val[_L_SR] = MIPS_SR_INT_IE |
2010 | | (ipl_sr_map.sr_bits[IPL_SCHED] ^ MIPS_INT_MASK); | | 2011 | | (ipl_sr_map.sr_bits[IPL_SCHED] ^ MIPS_INT_MASK); |
2011 | #ifdef _LP64 | | 2012 | #ifdef _LP64 |
2012 | pcb->pcb_context.val[_L_SR] |= MIPS_SR_KX | MIPS_SR_UX; | | 2013 | pcb->pcb_context.val[_L_SR] |= MIPS_SR_KX | MIPS_SR_UX; |
2013 | l->l_md.md_utf->tf_regs[_R_SR] = MIPS_SR_KX | MIPS_SR_UX; | | 2014 | l->l_md.md_utf->tf_regs[_R_SR] = MIPS_SR_KX | MIPS_SR_UX; |
2014 | #endif | | 2015 | #endif |
2015 | } | | 2016 | } |
2016 | | | 2017 | |
2017 | int mips_poolpage_vmfreelist = VM_FREELIST_DEFAULT; | | 2018 | int mips_poolpage_vmfreelist = VM_FREELIST_DEFAULT; |
2018 | | | 2019 | |
2019 | #define HALFGIG ((paddr_t)512 * 1024 * 1024) | | 2020 | #define HALFGIG ((paddr_t)512 * 1024 * 1024) |
2020 | #define FOURGIG ((paddr_t)4 * 1024 * 1024 * 1024) | | 2021 | #define FOURGIG ((paddr_t)4 * 1024 * 1024 * 1024) |
2021 | | | 2022 | |
2022 | void | | 2023 | void |
2023 | mips_page_physload(vaddr_t vkernstart, vaddr_t vkernend, | | 2024 | mips_page_physload(vaddr_t vkernstart, vaddr_t vkernend, |
2024 | const phys_ram_seg_t *segs, size_t nseg, | | 2025 | const phys_ram_seg_t *segs, size_t nseg, |
2025 | const struct mips_vmfreelist *flp, size_t nfl) | | 2026 | const struct mips_vmfreelist *flp, size_t nfl) |
2026 | { | | 2027 | { |
2027 | const paddr_t kernstart = MIPS_KSEG0_TO_PHYS(trunc_page(vkernstart)); | | 2028 | const paddr_t kernstart = MIPS_KSEG0_TO_PHYS(trunc_page(vkernstart)); |
2028 | const paddr_t kernend = MIPS_KSEG0_TO_PHYS(round_page(vkernend)); | | 2029 | const paddr_t kernend = MIPS_KSEG0_TO_PHYS(round_page(vkernend)); |
2029 | #if defined(VM_FREELIST_FIRST4G) || defined(VM_FREELIST_FIRST512M) | | 2030 | #if defined(VM_FREELIST_FIRST4G) || defined(VM_FREELIST_FIRST512M) |
2030 | #ifdef VM_FREELIST_FIRST512M | | 2031 | #ifdef VM_FREELIST_FIRST512M |
2031 | bool need512m = false; | | 2032 | bool need512m = false; |
2032 | #endif | | 2033 | #endif |
2033 | #ifdef VM_FREELIST_FIRST4G | | 2034 | #ifdef VM_FREELIST_FIRST4G |
2034 | bool need4g = false; | | 2035 | bool need4g = false; |
2035 | #endif | | 2036 | #endif |
2036 | | | 2037 | |
2037 | /* | | 2038 | /* |
2038 | * Do a first pass and see what ranges memory we have to deal with. | | 2039 | * Do a first pass and see what ranges memory we have to deal with. |
2039 | */ | | 2040 | */ |
2040 | for (size_t i = 0; i < nseg; i++) { | | 2041 | for (size_t i = 0; i < nseg; i++) { |
2041 | #ifdef VM_FREELIST_FIRST4G | | 2042 | #ifdef VM_FREELIST_FIRST4G |
2042 | if (round_page(segs[i].start + segs[i].size) > FOURGIG) { | | 2043 | if (round_page(segs[i].start + segs[i].size) > FOURGIG) { |
2043 | need4g = true; | | 2044 | need4g = true; |
2044 | mips_poolpage_vmfreelist = VM_FREELIST_FIRST4G; | | 2045 | mips_poolpage_vmfreelist = VM_FREELIST_FIRST4G; |
2045 | } | | 2046 | } |
2046 | #endif | | 2047 | #endif |
2047 | #ifdef VM_FREELIST_FIRST512M | | 2048 | #ifdef VM_FREELIST_FIRST512M |
2048 | if (round_page(segs[i].start + segs[i].size) > HALFGIG) { | | 2049 | if (round_page(segs[i].start + segs[i].size) > HALFGIG) { |
2049 | need512m = true; | | 2050 | need512m = true; |
2050 | mips_poolpage_vmfreelist = VM_FREELIST_FIRST512M; | | 2051 | mips_poolpage_vmfreelist = VM_FREELIST_FIRST512M; |
2051 | } | | 2052 | } |
2052 | #endif | | 2053 | #endif |
2053 | } | | 2054 | } |
2054 | #endif /* VM_FREELIST_FIRST512M || VM_FREELIST_FIRST4G */ | | 2055 | #endif /* VM_FREELIST_FIRST512M || VM_FREELIST_FIRST4G */ |
2055 | | | 2056 | |
2056 | for (; nseg-- > 0; segs++) { | | 2057 | for (; nseg-- > 0; segs++) { |
2057 | /* | | 2058 | /* |
2058 | * Make sure everything is in page units. | | 2059 | * Make sure everything is in page units. |
2059 | */ | | 2060 | */ |
2060 | paddr_t segstart = round_page(segs->start); | | 2061 | paddr_t segstart = round_page(segs->start); |
2061 | const paddr_t segfinish = trunc_page(segs->start + segs->size); | | 2062 | const paddr_t segfinish = trunc_page(segs->start + segs->size); |
2062 | | | 2063 | |
2063 | printf("phys segment: %#"PRIxPADDR" @ %#"PRIxPADDR"\n", | | 2064 | printf("phys segment: %#"PRIxPADDR" @ %#"PRIxPADDR"\n", |
2064 | segfinish - segstart, segstart); | | 2065 | segfinish - segstart, segstart); |
2065 | | | 2066 | |
2066 | /* | | 2067 | /* |
2067 | * Page 0 is reserved for exception vectors. | | 2068 | * Page 0 is reserved for exception vectors. |
2068 | */ | | 2069 | */ |
2069 | if (segstart == 0) { | | 2070 | if (segstart == 0) { |
2070 | segstart = PAGE_SIZE; | | 2071 | segstart = PAGE_SIZE; |
2071 | } | | 2072 | } |
2072 | while (segstart < segfinish) { | | 2073 | while (segstart < segfinish) { |
2073 | int freelist = -1; /* unknown freelist */ | | 2074 | int freelist = -1; /* unknown freelist */ |
2074 | paddr_t segend = segfinish; | | 2075 | paddr_t segend = segfinish; |
2075 | for (size_t i = 0; i < nfl; i++) { | | 2076 | for (size_t i = 0; i < nfl; i++) { |
2076 | /* | | 2077 | /* |
2077 | * If this segment doesn't overlap the freelist | | 2078 | * If this segment doesn't overlap the freelist |
2078 | * at all, skip it. | | 2079 | * at all, skip it. |
2079 | */ | | 2080 | */ |
2080 | if (segstart >= flp[i].fl_end | | 2081 | if (segstart >= flp[i].fl_end |
2081 | || segend <= flp[i].fl_start) | | 2082 | || segend <= flp[i].fl_start) |
2082 | continue; | | 2083 | continue; |
2083 | /* | | 2084 | /* |
2084 | * If the start of this segment starts before | | 2085 | * If the start of this segment starts before |
2085 | * the start of the freelist, then limit the | | 2086 | * the start of the freelist, then limit the |
2086 | * segment to loaded to the part that doesn't | | 2087 | * segment to loaded to the part that doesn't |
2087 | * match this freelist and fall back to normal | | 2088 | * match this freelist and fall back to normal |
2088 | * freelist matching. | | 2089 | * freelist matching. |
2089 | */ | | 2090 | */ |
2090 | if (segstart < flp[i].fl_start) { | | 2091 | if (segstart < flp[i].fl_start) { |
2091 | segstart = flp[i].fl_start; | | 2092 | segstart = flp[i].fl_start; |
2092 | break; | | 2093 | break; |
2093 | } | | 2094 | } |
2094 | | | 2095 | |
2095 | /* | | 2096 | /* |
2096 | * We've matched this freelist so remember it. | | 2097 | * We've matched this freelist so remember it. |
2097 | */ | | 2098 | */ |
2098 | freelist = flp->fl_freelist; | | 2099 | freelist = flp->fl_freelist; |
2099 | | | 2100 | |
2100 | /* | | 2101 | /* |
2101 | * If this segment extends past the end of this | | 2102 | * If this segment extends past the end of this |
2102 | * freelist, bound to segment to the freelist. | | 2103 | * freelist, bound to segment to the freelist. |
2103 | */ | | 2104 | */ |
2104 | if (segend > flp[i].fl_end) | | 2105 | if (segend > flp[i].fl_end) |
2105 | segend = flp[i].fl_end; | | 2106 | segend = flp[i].fl_end; |
2106 | break; | | 2107 | break; |
2107 | } | | 2108 | } |
2108 | /* | | 2109 | /* |
2109 | * If we didn't match one of the port dependent | | 2110 | * If we didn't match one of the port dependent |
2110 | * freelists, let's try the common ones. | | 2111 | * freelists, let's try the common ones. |
2111 | */ | | 2112 | */ |
2112 | if (freelist == -1) { | | 2113 | if (freelist == -1) { |
2113 | #ifdef VM_FREELIST_FIRST512M | | 2114 | #ifdef VM_FREELIST_FIRST512M |
2114 | if (need512m && segstart < HALFGIG) { | | 2115 | if (need512m && segstart < HALFGIG) { |
2115 | freelist = VM_FREELIST_FIRST512M; | | 2116 | freelist = VM_FREELIST_FIRST512M; |
2116 | if (segend > HALFGIG) | | 2117 | if (segend > HALFGIG) |
2117 | segend = HALFGIG; | | 2118 | segend = HALFGIG; |
2118 | } else | | 2119 | } else |
2119 | #endif | | 2120 | #endif |
2120 | #ifdef VM_FREELIST_FIRST4G | | 2121 | #ifdef VM_FREELIST_FIRST4G |
2121 | if (need4g && segstart < FOURGIG) { | | 2122 | if (need4g && segstart < FOURGIG) { |
2122 | freelist = VM_FREELIST_FIRST4G; | | 2123 | freelist = VM_FREELIST_FIRST4G; |
2123 | if (segend > FOURGIG) | | 2124 | if (segend > FOURGIG) |
2124 | segend = FOURGIG; | | 2125 | segend = FOURGIG; |
2125 | } else | | 2126 | } else |
2126 | #endif | | 2127 | #endif |
2127 | freelist = VM_FREELIST_DEFAULT; | | 2128 | freelist = VM_FREELIST_DEFAULT; |
2128 | } | | 2129 | } |
2129 | | | 2130 | |
2130 | /* | | 2131 | /* |
2131 | * Make sure the memory we provide to uvm doesn't | | 2132 | * Make sure the memory we provide to uvm doesn't |
2132 | * include the kernel. | | 2133 | * include the kernel. |
2133 | */ | | 2134 | */ |
2134 | if (segstart < kernend && segend > kernstart) { | | 2135 | if (segstart < kernend && segend > kernstart) { |
2135 | if (segstart < kernstart) { | | 2136 | if (segstart < kernstart) { |
2136 | /* | | 2137 | /* |
2137 | * Only add the memory before the | | 2138 | * Only add the memory before the |
2138 | * kernel. | | 2139 | * kernel. |
2139 | */ | | 2140 | */ |
2140 | segend = kernstart; | | 2141 | segend = kernstart; |
2141 | } else if (segend > kernend) { | | 2142 | } else if (segend > kernend) { |
2142 | /* | | 2143 | /* |
2143 | * Only add the memory after the | | 2144 | * Only add the memory after the |
2144 | * kernel. | | 2145 | * kernel. |
2145 | */ | | 2146 | */ |
2146 | segstart = kernend; | | 2147 | segstart = kernend; |
2147 | } else { | | 2148 | } else { |
2148 | /* | | 2149 | /* |
2149 | * Just skip the segment entirely since | | 2150 | * Just skip the segment entirely since |
2150 | * it's completely inside the kernel. | | 2151 | * it's completely inside the kernel. |
2151 | */ | | 2152 | */ |
2152 | printf("skipping %#"PRIxPADDR" @ %#"PRIxPADDR" (kernel)\n", | | 2153 | printf("skipping %#"PRIxPADDR" @ %#"PRIxPADDR" (kernel)\n", |
2153 | segend - segstart, segstart); | | 2154 | segend - segstart, segstart); |
2154 | break; | | 2155 | break; |
2155 | } | | 2156 | } |
2156 | } | | 2157 | } |
2157 | | | 2158 | |
2158 | /* | | 2159 | /* |
2159 | * Now we give this segment to uvm. | | 2160 | * Now we give this segment to uvm. |
2160 | */ | | 2161 | */ |
2161 | printf("adding %#"PRIxPADDR" @ %#"PRIxPADDR" to freelist %d\n", | | 2162 | printf("adding %#"PRIxPADDR" @ %#"PRIxPADDR" to freelist %d\n", |
2162 | | | 2163 | |
2163 | segend - segstart, segstart, freelist); | | 2164 | segend - segstart, segstart, freelist); |
2164 | paddr_t first = atop(segstart); | | 2165 | paddr_t first = atop(segstart); |
2165 | paddr_t last = atop(segend); | | 2166 | paddr_t last = atop(segend); |
2166 | uvm_page_physload(first, last, first, last, freelist); | | 2167 | uvm_page_physload(first, last, first, last, freelist); |
2167 | | | 2168 | |
2168 | /* | | 2169 | /* |
2169 | * Start where we finished. | | 2170 | * Start where we finished. |
2170 | */ | | 2171 | */ |
2171 | segstart = segend; | | 2172 | segstart = segend; |
2172 | } | | 2173 | } |
2173 | } | | 2174 | } |
2174 | } | | 2175 | } |
2175 | | | 2176 | |
2176 | /* | | 2177 | /* |
2177 | * Start a new LWP | | 2178 | * Start a new LWP |
2178 | */ | | 2179 | */ |
2179 | void | | 2180 | void |
2180 | startlwp(void *arg) | | 2181 | startlwp(void *arg) |
2181 | { | | 2182 | { |
2182 | ucontext_t * const uc = arg; | | 2183 | ucontext_t * const uc = arg; |
2183 | lwp_t * const l = curlwp; | | 2184 | lwp_t * const l = curlwp; |
2184 | int error; | | 2185 | int error; |
2185 | | | 2186 | |
2186 | error = cpu_setmcontext(l, &uc->uc_mcontext, uc->uc_flags); | | 2187 | error = cpu_setmcontext(l, &uc->uc_mcontext, uc->uc_flags); |
2187 | KASSERT(error == 0); | | 2188 | KASSERT(error == 0); |
2188 | | | 2189 | |
2189 | kmem_free(uc, sizeof(ucontext_t)); | | 2190 | kmem_free(uc, sizeof(ucontext_t)); |
2190 | userret(l); | | 2191 | userret(l); |
2191 | } | | 2192 | } |
2192 | | | 2193 | |
2193 | #ifdef COMPAT_NETBSD32 | | 2194 | #ifdef COMPAT_NETBSD32 |
2194 | /* | | 2195 | /* |
2195 | * Start a new LWP | | 2196 | * Start a new LWP |
2196 | */ | | 2197 | */ |
2197 | void | | 2198 | void |
2198 | startlwp32(void *arg) | | 2199 | startlwp32(void *arg) |
2199 | { | | 2200 | { |
2200 | ucontext32_t * const uc = arg; | | 2201 | ucontext32_t * const uc = arg; |
2201 | lwp_t * const l = curlwp; | | 2202 | lwp_t * const l = curlwp; |
2202 | int error; | | 2203 | int error; |
2203 | | | 2204 | |
2204 | error = cpu_setmcontext32(l, &uc->uc_mcontext, uc->uc_flags); | | 2205 | error = cpu_setmcontext32(l, &uc->uc_mcontext, uc->uc_flags); |
2205 | KASSERT(error == 0); | | 2206 | KASSERT(error == 0); |
2206 | | | 2207 | |
2207 | /* Note: we are freeing ucontext_t, not ucontext32_t. */ | | 2208 | /* Note: we are freeing ucontext_t, not ucontext32_t. */ |
2208 | kmem_free(uc, sizeof(ucontext_t)); | | 2209 | kmem_free(uc, sizeof(ucontext_t)); |
2209 | userret(l); | | 2210 | userret(l); |
2210 | } | | 2211 | } |
2211 | #endif /* COMPAT_NETBSD32 */ | | 2212 | #endif /* COMPAT_NETBSD32 */ |
2212 | | | 2213 | |
2213 | #ifdef PARANOIA | | 2214 | #ifdef PARANOIA |
2214 | void | | 2215 | void |
2215 | std_splsw_test(void) | | 2216 | std_splsw_test(void) |
2216 | { | | 2217 | { |
2217 | struct cpu_info * const ci = curcpu(); | | 2218 | struct cpu_info * const ci = curcpu(); |
2218 | const uint32_t * const sr_map = ipl_sr_map.sr_bits; | | 2219 | const uint32_t * const sr_map = ipl_sr_map.sr_bits; |
2219 | uint32_t status = mips_cp0_status_read(); | | 2220 | uint32_t status = mips_cp0_status_read(); |
2220 | uint32_t sr_bits; | | 2221 | uint32_t sr_bits; |
2221 | int s; | | 2222 | int s; |
2222 | | | 2223 | |
2223 | KASSERT((status & MIPS_SR_INT_IE) == 0); | | 2224 | KASSERT((status & MIPS_SR_INT_IE) == 0); |
2224 | | | 2225 | |
2225 | sr_bits = sr_map[IPL_NONE]; | | 2226 | sr_bits = sr_map[IPL_NONE]; |
2226 | | | 2227 | |
2227 | splx(IPL_NONE); | | 2228 | splx(IPL_NONE); |
2228 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2229 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2229 | KASSERT(status == MIPS_INT_MASK); | | 2230 | KASSERT(status == MIPS_INT_MASK); |
2230 | KASSERT(ci->ci_cpl == IPL_NONE); | | 2231 | KASSERT(ci->ci_cpl == IPL_NONE); |
2231 | | | 2232 | |
2232 | s = splsoftclock(); | | 2233 | s = splsoftclock(); |
2233 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2234 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2234 | KASSERT((status ^ sr_map[IPL_SOFTCLOCK]) == MIPS_INT_MASK); | | 2235 | KASSERT((status ^ sr_map[IPL_SOFTCLOCK]) == MIPS_INT_MASK); |
2235 | KASSERT(ci->ci_cpl == IPL_SOFTCLOCK); | | 2236 | KASSERT(ci->ci_cpl == IPL_SOFTCLOCK); |
2236 | KASSERT(s == IPL_NONE); | | 2237 | KASSERT(s == IPL_NONE); |
2237 | | | 2238 | |
2238 | s = splsoftbio(); | | 2239 | s = splsoftbio(); |
2239 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2240 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2240 | KASSERT((status ^ sr_map[IPL_SOFTBIO]) == MIPS_INT_MASK); | | 2241 | KASSERT((status ^ sr_map[IPL_SOFTBIO]) == MIPS_INT_MASK); |
2241 | KASSERT(ci->ci_cpl == IPL_SOFTBIO); | | 2242 | KASSERT(ci->ci_cpl == IPL_SOFTBIO); |
2242 | KASSERT(s == IPL_SOFTCLOCK); | | 2243 | KASSERT(s == IPL_SOFTCLOCK); |
2243 | | | 2244 | |
2244 | s = splsoftnet(); | | 2245 | s = splsoftnet(); |
2245 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2246 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2246 | KASSERT((status ^ sr_map[IPL_SOFTNET]) == MIPS_INT_MASK); | | 2247 | KASSERT((status ^ sr_map[IPL_SOFTNET]) == MIPS_INT_MASK); |
2247 | KASSERT(ci->ci_cpl == IPL_SOFTNET); | | 2248 | KASSERT(ci->ci_cpl == IPL_SOFTNET); |
2248 | KASSERT(s == IPL_SOFTBIO); | | 2249 | KASSERT(s == IPL_SOFTBIO); |
2249 | | | 2250 | |
2250 | s = splsoftserial(); | | 2251 | s = splsoftserial(); |
2251 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2252 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2252 | KASSERT((status ^ sr_map[IPL_SOFTSERIAL]) == MIPS_INT_MASK); | | 2253 | KASSERT((status ^ sr_map[IPL_SOFTSERIAL]) == MIPS_INT_MASK); |
2253 | KASSERT(ci->ci_cpl == IPL_SOFTSERIAL); | | 2254 | KASSERT(ci->ci_cpl == IPL_SOFTSERIAL); |
2254 | KASSERT(s == IPL_SOFTNET); | | 2255 | KASSERT(s == IPL_SOFTNET); |
2255 | | | 2256 | |
2256 | s = splvm(); | | 2257 | s = splvm(); |
2257 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2258 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2258 | KASSERT((status ^ sr_map[IPL_VM]) == MIPS_INT_MASK); | | 2259 | KASSERT((status ^ sr_map[IPL_VM]) == MIPS_INT_MASK); |
2259 | KASSERT(ci->ci_cpl == IPL_VM); | | 2260 | KASSERT(ci->ci_cpl == IPL_VM); |
2260 | KASSERT(s == IPL_SOFTSERIAL); | | 2261 | KASSERT(s == IPL_SOFTSERIAL); |
2261 | | | 2262 | |
2262 | s = splsched(); | | 2263 | s = splsched(); |
2263 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2264 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2264 | KASSERT((status ^ sr_map[IPL_SCHED]) == MIPS_INT_MASK); | | 2265 | KASSERT((status ^ sr_map[IPL_SCHED]) == MIPS_INT_MASK); |
2265 | KASSERT(ci->ci_cpl == IPL_SCHED); | | 2266 | KASSERT(ci->ci_cpl == IPL_SCHED); |
2266 | KASSERT(s == IPL_VM); | | 2267 | KASSERT(s == IPL_VM); |
2267 | | | 2268 | |
2268 | s = splhigh(); | | 2269 | s = splhigh(); |
2269 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2270 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2270 | KASSERT((status ^ sr_map[IPL_HIGH]) == MIPS_INT_MASK); | | 2271 | KASSERT((status ^ sr_map[IPL_HIGH]) == MIPS_INT_MASK); |
2271 | KASSERT(ci->ci_cpl == IPL_HIGH); | | 2272 | KASSERT(ci->ci_cpl == IPL_HIGH); |
2272 | KASSERT(s == IPL_SCHED); | | 2273 | KASSERT(s == IPL_SCHED); |
2273 | | | 2274 | |
2274 | splx(IPL_NONE); | | 2275 | splx(IPL_NONE); |
2275 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2276 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2276 | KASSERT(status == MIPS_INT_MASK); | | 2277 | KASSERT(status == MIPS_INT_MASK); |
2277 | KASSERT(ci->ci_cpl == IPL_NONE); | | 2278 | KASSERT(ci->ci_cpl == IPL_NONE); |
2278 | | | 2279 | |
2279 | for (int r = IPL_SOFTCLOCK; r <= IPL_HIGH; r++) { | | 2280 | for (int r = IPL_SOFTCLOCK; r <= IPL_HIGH; r++) { |
2280 | /* | | 2281 | /* |
2281 | * As IPL increases, more intrs may be masked but no intrs | | 2282 | * As IPL increases, more intrs may be masked but no intrs |
2282 | * may become unmasked. | | 2283 | * may become unmasked. |
2283 | */ | | 2284 | */ |
2284 | KASSERT((sr_map[r] & sr_bits) == sr_bits); | | 2285 | KASSERT((sr_map[r] & sr_bits) == sr_bits); |
2285 | sr_bits |= sr_map[r]; | | 2286 | sr_bits |= sr_map[r]; |
2286 | s = splraise(r); | | 2287 | s = splraise(r); |
2287 | KASSERT(s == IPL_NONE); | | 2288 | KASSERT(s == IPL_NONE); |
2288 | | | 2289 | |
2289 | for (int t = r; t <= IPL_HIGH; t++) { | | 2290 | for (int t = r; t <= IPL_HIGH; t++) { |
2290 | int o = splraise(t); | | 2291 | int o = splraise(t); |
2291 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2292 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2292 | KASSERT((status ^ sr_map[t]) == MIPS_INT_MASK); | | 2293 | KASSERT((status ^ sr_map[t]) == MIPS_INT_MASK); |
2293 | KASSERT(ci->ci_cpl == t); | | 2294 | KASSERT(ci->ci_cpl == t); |
2294 | KASSERT(o == r); | | 2295 | KASSERT(o == r); |
2295 | | | 2296 | |
2296 | splx(o); | | 2297 | splx(o); |
2297 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2298 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2298 | KASSERT((status ^ sr_map[r]) == MIPS_INT_MASK); | | 2299 | KASSERT((status ^ sr_map[r]) == MIPS_INT_MASK); |
2299 | KASSERT(ci->ci_cpl == r); | | 2300 | KASSERT(ci->ci_cpl == r); |
2300 | } | | 2301 | } |
2301 | | | 2302 | |
2302 | splx(s); | | 2303 | splx(s); |
2303 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2304 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2304 | KASSERT((status ^ sr_map[s]) == MIPS_INT_MASK); | | 2305 | KASSERT((status ^ sr_map[s]) == MIPS_INT_MASK); |
2305 | KASSERT(ci->ci_cpl == s); | | 2306 | KASSERT(ci->ci_cpl == s); |
2306 | } | | 2307 | } |
2307 | | | 2308 | |
2308 | status = mips_cp0_status_read() & MIPS_INT_MASK; | | 2309 | status = mips_cp0_status_read() & MIPS_INT_MASK; |
2309 | KASSERT(status == MIPS_INT_MASK); | | 2310 | KASSERT(status == MIPS_INT_MASK); |
2310 | KASSERT(ci->ci_cpl == IPL_NONE); | | 2311 | KASSERT(ci->ci_cpl == IPL_NONE); |
2311 | } | | 2312 | } |
2312 | | | 2313 | |
2313 | #endif /* PARANOIA */ | | 2314 | #endif /* PARANOIA */ |
2314 | | | 2315 | |
2315 | bool | | 2316 | bool |
2316 | mm_md_direct_mapped_phys(paddr_t pa, vaddr_t *vap) | | 2317 | mm_md_direct_mapped_phys(paddr_t pa, vaddr_t *vap) |
2317 | { | | 2318 | { |
2318 | #ifdef _LP64 | | 2319 | #ifdef _LP64 |
2319 | if (MIPS_XKSEG_P(pa)) { | | 2320 | if (MIPS_XKSEG_P(pa)) { |
2320 | *vap = MIPS_PHYS_TO_XKPHYS_CACHED(pa); | | 2321 | *vap = MIPS_PHYS_TO_XKPHYS_CACHED(pa); |
2321 | return true; | | 2322 | return true; |
2322 | } | | 2323 | } |
2323 | #endif | | 2324 | #endif |
2324 | if (MIPS_KSEG0_P(pa)) { | | 2325 | if (MIPS_KSEG0_P(pa)) { |
2325 | *vap = MIPS_PHYS_TO_KSEG0(pa); | | 2326 | *vap = MIPS_PHYS_TO_KSEG0(pa); |
2326 | return true; | | 2327 | return true; |
2327 | } | | 2328 | } |
2328 | return false; | | 2329 | return false; |
2329 | } | | 2330 | } |
2330 | | | 2331 | |
2331 | int | | 2332 | int |
2332 | mm_md_physacc(paddr_t pa, vm_prot_t prot) | | 2333 | mm_md_physacc(paddr_t pa, vm_prot_t prot) |
2333 | { | | 2334 | { |
2334 | | | 2335 | |
2335 | return (pa < ctob(physmem)) ? 0 : EFAULT; | | 2336 | return (pa < ctob(physmem)) ? 0 : EFAULT; |
2336 | } | | 2337 | } |
2337 | | | 2338 | |
2338 | int | | 2339 | int |
2339 | mm_md_kernacc(void *ptr, vm_prot_t prot, bool *handled) | | 2340 | mm_md_kernacc(void *ptr, vm_prot_t prot, bool *handled) |
2340 | { | | 2341 | { |
2341 | const vaddr_t v = (vaddr_t)ptr; | | 2342 | const vaddr_t v = (vaddr_t)ptr; |
2342 | | | 2343 | |
2343 | #ifdef _LP64 | | 2344 | #ifdef _LP64 |
2344 | if (v < MIPS_XKPHYS_START) { | | 2345 | if (v < MIPS_XKPHYS_START) { |
2345 | return EFAULT; | | 2346 | return EFAULT; |
2346 | } | | 2347 | } |
2347 | if (MIPS_XKPHYS_P(v) && v > MIPS_PHYS_TO_XKPHYS_CACHED(mips_avail_end + | | 2348 | if (MIPS_XKPHYS_P(v) && v > MIPS_PHYS_TO_XKPHYS_CACHED(mips_avail_end + |
2348 | mips_round_page(MSGBUFSIZE))) { | | 2349 | mips_round_page(MSGBUFSIZE))) { |
2349 | return EFAULT; | | 2350 | return EFAULT; |
2350 | } | | 2351 | } |
2351 | if (MIPS_XKSEG_P(v) && v < MIPS_KSEG0_START) { | | 2352 | if (MIPS_XKSEG_P(v) && v < MIPS_KSEG0_START) { |
2352 | *handled = true; | | 2353 | *handled = true; |
2353 | return 0; | | 2354 | return 0; |
2354 | } | | 2355 | } |
2355 | if (MIPS_KSEG1_P(v) || MIPS_KSEG2_P(v)) { | | 2356 | if (MIPS_KSEG1_P(v) || MIPS_KSEG2_P(v)) { |
2356 | return EFAULT; | | 2357 | return EFAULT; |
2357 | } | | 2358 | } |
2358 | #else | | 2359 | #else |
2359 | if (v < MIPS_KSEG0_START) { | | 2360 | if (v < MIPS_KSEG0_START) { |