| @@ -1,1998 +1,1996 @@ | | | @@ -1,1998 +1,1996 @@ |
1 | /* $NetBSD: wdc.c,v 1.264 2011/08/28 09:32:21 christos Exp $ */ | | 1 | /* $NetBSD: wdc.c,v 1.265 2011/08/28 10:21:41 bouyer Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. | | 4 | * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. |
5 | * | | 5 | * |
6 | * Redistribution and use in source and binary forms, with or without | | 6 | * Redistribution and use in source and binary forms, with or without |
7 | * modification, are permitted provided that the following conditions | | 7 | * modification, are permitted provided that the following conditions |
8 | * are met: | | 8 | * are met: |
9 | * 1. Redistributions of source code must retain the above copyright | | 9 | * 1. Redistributions of source code must retain the above copyright |
10 | * notice, this list of conditions and the following disclaimer. | | 10 | * notice, this list of conditions and the following disclaimer. |
11 | * 2. Redistributions in binary form must reproduce the above copyright | | 11 | * 2. Redistributions in binary form must reproduce the above copyright |
12 | * notice, this list of conditions and the following disclaimer in the | | 12 | * notice, this list of conditions and the following disclaimer in the |
13 | * documentation and/or other materials provided with the distribution. | | 13 | * documentation and/or other materials provided with the distribution. |
14 | * | | 14 | * |
15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | | 15 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | | 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | | 17 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | | 18 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | | 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | | 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | | 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | | 22 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | | 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | | 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
25 | */ | | 25 | */ |
26 | | | 26 | |
27 | /*- | | 27 | /*- |
28 | * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. | | 28 | * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. |
29 | * All rights reserved. | | 29 | * All rights reserved. |
30 | * | | 30 | * |
31 | * This code is derived from software contributed to The NetBSD Foundation | | 31 | * This code is derived from software contributed to The NetBSD Foundation |
32 | * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. | | 32 | * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. |
33 | * | | 33 | * |
34 | * Redistribution and use in source and binary forms, with or without | | 34 | * Redistribution and use in source and binary forms, with or without |
35 | * modification, are permitted provided that the following conditions | | 35 | * modification, are permitted provided that the following conditions |
36 | * are met: | | 36 | * are met: |
37 | * 1. Redistributions of source code must retain the above copyright | | 37 | * 1. Redistributions of source code must retain the above copyright |
38 | * notice, this list of conditions and the following disclaimer. | | 38 | * notice, this list of conditions and the following disclaimer. |
39 | * 2. Redistributions in binary form must reproduce the above copyright | | 39 | * 2. Redistributions in binary form must reproduce the above copyright |
40 | * notice, this list of conditions and the following disclaimer in the | | 40 | * notice, this list of conditions and the following disclaimer in the |
41 | * documentation and/or other materials provided with the distribution. | | 41 | * documentation and/or other materials provided with the distribution. |
42 | * | | 42 | * |
43 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS | | 43 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
44 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 44 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
45 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 45 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
46 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 46 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
47 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 47 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
48 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 48 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
49 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 49 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
50 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 50 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
51 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 51 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
52 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 52 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
53 | * POSSIBILITY OF SUCH DAMAGE. | | 53 | * POSSIBILITY OF SUCH DAMAGE. |
54 | */ | | 54 | */ |
55 | | | 55 | |
56 | /* | | 56 | /* |
57 | * CODE UNTESTED IN THE CURRENT REVISION: | | 57 | * CODE UNTESTED IN THE CURRENT REVISION: |
58 | */ | | 58 | */ |
59 | | | 59 | |
60 | #include <sys/cdefs.h> | | 60 | #include <sys/cdefs.h> |
61 | __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.264 2011/08/28 09:32:21 christos Exp $"); | | 61 | __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.265 2011/08/28 10:21:41 bouyer Exp $"); |
62 | | | 62 | |
63 | #include "opt_ata.h" | | 63 | #include "opt_ata.h" |
64 | #include "opt_wdc.h" | | 64 | #include "opt_wdc.h" |
65 | | | 65 | |
66 | #include <sys/param.h> | | 66 | #include <sys/param.h> |
67 | #include <sys/systm.h> | | 67 | #include <sys/systm.h> |
68 | #include <sys/kernel.h> | | 68 | #include <sys/kernel.h> |
69 | #include <sys/conf.h> | | 69 | #include <sys/conf.h> |
70 | #include <sys/buf.h> | | 70 | #include <sys/buf.h> |
71 | #include <sys/device.h> | | 71 | #include <sys/device.h> |
72 | #include <sys/malloc.h> | | 72 | #include <sys/malloc.h> |
73 | #include <sys/syslog.h> | | 73 | #include <sys/syslog.h> |
74 | #include <sys/proc.h> | | 74 | #include <sys/proc.h> |
75 | | | 75 | |
76 | #include <sys/intr.h> | | 76 | #include <sys/intr.h> |
77 | #include <sys/bus.h> | | 77 | #include <sys/bus.h> |
78 | | | 78 | |
79 | #ifndef __BUS_SPACE_HAS_STREAM_METHODS | | 79 | #ifndef __BUS_SPACE_HAS_STREAM_METHODS |
80 | #define bus_space_write_multi_stream_2 bus_space_write_multi_2 | | 80 | #define bus_space_write_multi_stream_2 bus_space_write_multi_2 |
81 | #define bus_space_write_multi_stream_4 bus_space_write_multi_4 | | 81 | #define bus_space_write_multi_stream_4 bus_space_write_multi_4 |
82 | #define bus_space_read_multi_stream_2 bus_space_read_multi_2 | | 82 | #define bus_space_read_multi_stream_2 bus_space_read_multi_2 |
83 | #define bus_space_read_multi_stream_4 bus_space_read_multi_4 | | 83 | #define bus_space_read_multi_stream_4 bus_space_read_multi_4 |
84 | #define bus_space_read_stream_2 bus_space_read_2 | | 84 | #define bus_space_read_stream_2 bus_space_read_2 |
85 | #define bus_space_read_stream_4 bus_space_read_4 | | 85 | #define bus_space_read_stream_4 bus_space_read_4 |
86 | #define bus_space_write_stream_2 bus_space_write_2 | | 86 | #define bus_space_write_stream_2 bus_space_write_2 |
87 | #define bus_space_write_stream_4 bus_space_write_4 | | 87 | #define bus_space_write_stream_4 bus_space_write_4 |
88 | #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ | | 88 | #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ |
89 | | | 89 | |
90 | #include <dev/ata/atavar.h> | | 90 | #include <dev/ata/atavar.h> |
91 | #include <dev/ata/atareg.h> | | 91 | #include <dev/ata/atareg.h> |
92 | #include <dev/ata/satareg.h> | | 92 | #include <dev/ata/satareg.h> |
93 | #include <dev/ata/satavar.h> | | 93 | #include <dev/ata/satavar.h> |
94 | #include <dev/ic/wdcreg.h> | | 94 | #include <dev/ic/wdcreg.h> |
95 | #include <dev/ic/wdcvar.h> | | 95 | #include <dev/ic/wdcvar.h> |
96 | | | 96 | |
97 | #include "locators.h" | | 97 | #include "locators.h" |
98 | | | 98 | |
99 | #include "atapibus.h" | | 99 | #include "atapibus.h" |
100 | #include "wd.h" | | 100 | #include "wd.h" |
101 | #include "sata.h" | | 101 | #include "sata.h" |
102 | | | 102 | |
103 | #define WDCDELAY 100 /* 100 microseconds */ | | 103 | #define WDCDELAY 100 /* 100 microseconds */ |
104 | #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) | | 104 | #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) |
105 | #if 0 | | 105 | #if 0 |
106 | /* If you enable this, it will report any delays more than WDCDELAY * N long. */ | | 106 | /* If you enable this, it will report any delays more than WDCDELAY * N long. */ |
107 | #define WDCNDELAY_DEBUG 50 | | 107 | #define WDCNDELAY_DEBUG 50 |
108 | #endif | | 108 | #endif |
109 | | | 109 | |
110 | /* When polling wait that much and then tsleep for 1/hz seconds */ | | 110 | /* When polling wait that much and then tsleep for 1/hz seconds */ |
111 | #define WDCDELAY_POLL 1 /* ms */ | | 111 | #define WDCDELAY_POLL 1 /* ms */ |
112 | | | 112 | |
113 | /* timeout for the control commands */ | | 113 | /* timeout for the control commands */ |
114 | #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ | | 114 | #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ |
115 | | | 115 | |
116 | /* | | 116 | /* |
117 | * timeout when waiting for BSY to deassert when probing. | | 117 | * timeout when waiting for BSY to deassert when probing. |
118 | * set to 5s. From the standards this could be up to 31, but we can't | | 118 | * set to 5s. From the standards this could be up to 31, but we can't |
119 | * wait that much at boot time, and 5s seems to be enough. | | 119 | * wait that much at boot time, and 5s seems to be enough. |
120 | */ | | 120 | */ |
121 | #define WDC_PROBE_WAIT 5 | | 121 | #define WDC_PROBE_WAIT 5 |
122 | | | 122 | |
123 | | | 123 | |
124 | #if NWD > 0 | | 124 | #if NWD > 0 |
125 | extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ | | 125 | extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ |
126 | #else | | 126 | #else |
127 | /* A fake one, the autoconfig will print "wd at foo ... not configured */ | | 127 | /* A fake one, the autoconfig will print "wd at foo ... not configured */ |
128 | const struct ata_bustype wdc_ata_bustype = { | | 128 | const struct ata_bustype wdc_ata_bustype = { |
129 | SCSIPI_BUSTYPE_ATA, | | 129 | SCSIPI_BUSTYPE_ATA, |
130 | NULL, /* wdc_ata_bio */ | | 130 | NULL, /* wdc_ata_bio */ |
131 | NULL, /* wdc_reset_drive */ | | 131 | NULL, /* wdc_reset_drive */ |
132 | wdc_reset_channel, | | 132 | wdc_reset_channel, |
133 | wdc_exec_command, | | 133 | wdc_exec_command, |
134 | NULL, /* ata_get_params */ | | 134 | NULL, /* ata_get_params */ |
135 | NULL, /* wdc_ata_addref */ | | 135 | NULL, /* wdc_ata_addref */ |
136 | NULL, /* wdc_ata_delref */ | | 136 | NULL, /* wdc_ata_delref */ |
137 | NULL /* ata_kill_pending */ | | 137 | NULL /* ata_kill_pending */ |
138 | }; | | 138 | }; |
139 | #endif | | 139 | #endif |
140 | | | 140 | |
141 | /* Flags to wdcreset(). */ | | 141 | /* Flags to wdcreset(). */ |
142 | #define RESET_POLL 1 | | 142 | #define RESET_POLL 1 |
143 | #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ | | 143 | #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ |
144 | | | 144 | |
145 | static int wdcprobe1(struct ata_channel *, int); | | 145 | static int wdcprobe1(struct ata_channel *, int); |
146 | static int wdcreset(struct ata_channel *, int); | | 146 | static int wdcreset(struct ata_channel *, int); |
147 | static void __wdcerror(struct ata_channel *, const char *); | | 147 | static void __wdcerror(struct ata_channel *, const char *); |
148 | static int __wdcwait_reset(struct ata_channel *, int, int); | | 148 | static int __wdcwait_reset(struct ata_channel *, int, int); |
149 | static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); | | 149 | static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); |
150 | static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); | | 150 | static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); |
151 | static void __wdccommand_kill_xfer(struct ata_channel *, | | 151 | static void __wdccommand_kill_xfer(struct ata_channel *, |
152 | struct ata_xfer *, int); | | 152 | struct ata_xfer *, int); |
153 | static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); | | 153 | static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); |
154 | static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); | | 154 | static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); |
155 | static int __wdcwait(struct ata_channel *, int, int, int); | | 155 | static int __wdcwait(struct ata_channel *, int, int, int); |
156 | | | 156 | |
157 | static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); | | 157 | static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); |
158 | static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); | | 158 | static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); |
159 | | | 159 | |
160 | #define DEBUG_INTR 0x01 | | 160 | #define DEBUG_INTR 0x01 |
161 | #define DEBUG_XFERS 0x02 | | 161 | #define DEBUG_XFERS 0x02 |
162 | #define DEBUG_STATUS 0x04 | | 162 | #define DEBUG_STATUS 0x04 |
163 | #define DEBUG_FUNCS 0x08 | | 163 | #define DEBUG_FUNCS 0x08 |
164 | #define DEBUG_PROBE 0x10 | | 164 | #define DEBUG_PROBE 0x10 |
165 | #define DEBUG_DETACH 0x20 | | 165 | #define DEBUG_DETACH 0x20 |
166 | #define DEBUG_DELAY 0x40 | | 166 | #define DEBUG_DELAY 0x40 |
167 | #ifdef ATADEBUG | | 167 | #ifdef ATADEBUG |
168 | extern int atadebug_mask; /* init'ed in ata.c */ | | 168 | extern int atadebug_mask; /* init'ed in ata.c */ |
169 | int wdc_nxfer = 0; | | 169 | int wdc_nxfer = 0; |
170 | #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args | | 170 | #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args |
171 | #else | | 171 | #else |
172 | #define ATADEBUG_PRINT(args, level) | | 172 | #define ATADEBUG_PRINT(args, level) |
173 | #endif | | 173 | #endif |
174 | | | 174 | |
175 | /* | | 175 | /* |
176 | * Initialize the "shadow register" handles for a standard wdc controller. | | 176 | * Initialize the "shadow register" handles for a standard wdc controller. |
177 | */ | | 177 | */ |
178 | void | | 178 | void |
179 | wdc_init_shadow_regs(struct ata_channel *chp) | | 179 | wdc_init_shadow_regs(struct ata_channel *chp) |
180 | { | | 180 | { |
181 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); | | 181 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
182 | | | 182 | |
183 | wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; | | 183 | wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; |
184 | wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; | | 184 | wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; |
185 | } | | 185 | } |
186 | | | 186 | |
187 | /* | | 187 | /* |
188 | * Allocate a wdc_regs array, based on the number of channels. | | 188 | * Allocate a wdc_regs array, based on the number of channels. |
189 | */ | | 189 | */ |
190 | void | | 190 | void |
191 | wdc_allocate_regs(struct wdc_softc *wdc) | | 191 | wdc_allocate_regs(struct wdc_softc *wdc) |
192 | { | | 192 | { |
193 | | | 193 | |
194 | wdc->regs = malloc(wdc->sc_atac.atac_nchannels * | | 194 | wdc->regs = malloc(wdc->sc_atac.atac_nchannels * |
195 | sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); | | 195 | sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); |
196 | } | | 196 | } |
197 | | | 197 | |
198 | #if NSATA > 0 | | 198 | #if NSATA > 0 |
199 | /* | | 199 | /* |
200 | * probe drives on SATA controllers with standard SATA registers: | | 200 | * probe drives on SATA controllers with standard SATA registers: |
201 | * bring the PHYs online, read the drive signature and set drive flags | | 201 | * bring the PHYs online, read the drive signature and set drive flags |
202 | * appropriately. | | 202 | * appropriately. |
203 | */ | | 203 | */ |
204 | void | | 204 | void |
205 | wdc_sataprobe(struct ata_channel *chp) | | 205 | wdc_sataprobe(struct ata_channel *chp) |
206 | { | | 206 | { |
207 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); | | 207 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
208 | uint8_t st = 0, sc, sn, cl, ch; | | 208 | uint8_t st = 0, sc, sn, cl, ch; |
209 | int i, s; | | 209 | int i, s; |
210 | | | 210 | |
211 | /* XXX This should be done by other code. */ | | 211 | /* XXX This should be done by other code. */ |
212 | for (i = 0; i < chp->ch_ndrive; i++) { | | 212 | for (i = 0; i < chp->ch_ndrive; i++) { |
213 | chp->ch_drive[i].chnl_softc = chp; | | 213 | chp->ch_drive[i].chnl_softc = chp; |
214 | chp->ch_drive[i].drive = i; | | 214 | chp->ch_drive[i].drive = i; |
215 | } | | 215 | } |
216 | | | 216 | |
217 | /* reset the PHY and bring online */ | | 217 | /* reset the PHY and bring online */ |
218 | switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, | | 218 | switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, |
219 | wdr->sata_status)) { | | 219 | wdr->sata_status)) { |
220 | case SStatus_DET_DEV: | | 220 | case SStatus_DET_DEV: |
221 | /* wait 5s for BSY to clear */ | | 221 | /* wait 5s for BSY to clear */ |
222 | for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { | | 222 | for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { |
223 | bus_space_write_1(wdr->cmd_iot, | | 223 | bus_space_write_1(wdr->cmd_iot, |
224 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); | | 224 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); |
225 | delay(10); /* 400ns delay */ | | 225 | delay(10); /* 400ns delay */ |
226 | st = bus_space_read_1(wdr->cmd_iot, | | 226 | st = bus_space_read_1(wdr->cmd_iot, |
227 | wdr->cmd_iohs[wd_status], 0); | | 227 | wdr->cmd_iohs[wd_status], 0); |
228 | if ((st & WDCS_BSY) == 0) | | 228 | if ((st & WDCS_BSY) == 0) |
229 | break; | | 229 | break; |
230 | tsleep(&chp, PRIBIO, "sataprb", 1); | | 230 | tsleep(&chp, PRIBIO, "sataprb", 1); |
231 | } | | 231 | } |
232 | if (i == WDC_PROBE_WAIT * hz) | | 232 | if (i == WDC_PROBE_WAIT * hz) |
233 | aprint_error_dev(chp->ch_atac->atac_dev, | | 233 | aprint_error_dev(chp->ch_atac->atac_dev, |
234 | "BSY never cleared, status 0x%02x\n", st); | | 234 | "BSY never cleared, status 0x%02x\n", st); |
235 | sc = bus_space_read_1(wdr->cmd_iot, | | 235 | sc = bus_space_read_1(wdr->cmd_iot, |
236 | wdr->cmd_iohs[wd_seccnt], 0); | | 236 | wdr->cmd_iohs[wd_seccnt], 0); |
237 | sn = bus_space_read_1(wdr->cmd_iot, | | 237 | sn = bus_space_read_1(wdr->cmd_iot, |
238 | wdr->cmd_iohs[wd_sector], 0); | | 238 | wdr->cmd_iohs[wd_sector], 0); |
239 | cl = bus_space_read_1(wdr->cmd_iot, | | 239 | cl = bus_space_read_1(wdr->cmd_iot, |
240 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 240 | wdr->cmd_iohs[wd_cyl_lo], 0); |
241 | ch = bus_space_read_1(wdr->cmd_iot, | | 241 | ch = bus_space_read_1(wdr->cmd_iot, |
242 | wdr->cmd_iohs[wd_cyl_hi], 0); | | 242 | wdr->cmd_iohs[wd_cyl_hi], 0); |
243 | ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " | | 243 | ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " |
244 | "cl=0x%x ch=0x%x\n", | | 244 | "cl=0x%x ch=0x%x\n", |
245 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 245 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
246 | sc, sn, cl, ch), DEBUG_PROBE); | | 246 | sc, sn, cl, ch), DEBUG_PROBE); |
247 | /* | | 247 | /* |
248 | * sc and sn are supposed to be 0x1 for ATAPI, but in some | | 248 | * sc and sn are supposed to be 0x1 for ATAPI, but in some |
249 | * cases we get wrong values here, so ignore it. | | 249 | * cases we get wrong values here, so ignore it. |
250 | */ | | 250 | */ |
251 | s = splbio(); | | 251 | s = splbio(); |
252 | if (cl == 0x14 && ch == 0xeb) | | 252 | if (cl == 0x14 && ch == 0xeb) |
253 | chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; | | 253 | chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; |
254 | else | | 254 | else |
255 | chp->ch_drive[0].drive_flags |= DRIVE_ATA; | | 255 | chp->ch_drive[0].drive_flags |= DRIVE_ATA; |
256 | splx(s); | | 256 | splx(s); |
257 | | | 257 | |
258 | /* | | 258 | /* |
259 | * issue a reset in case only the interface part of the drive | | 259 | * issue a reset in case only the interface part of the drive |
260 | * is up | | 260 | * is up |
261 | */ | | 261 | */ |
262 | if (wdcreset(chp, RESET_SLEEP) != 0) | | 262 | if (wdcreset(chp, RESET_SLEEP) != 0) |
263 | chp->ch_drive[0].drive_flags = 0; | | 263 | chp->ch_drive[0].drive_flags = 0; |
264 | break; | | 264 | break; |
265 | | | 265 | |
266 | default: | | 266 | default: |
267 | break; | | 267 | break; |
268 | } | | 268 | } |
269 | } | | 269 | } |
270 | #endif /* NSATA > 0 */ | | 270 | #endif /* NSATA > 0 */ |
271 | | | 271 | |
272 | | | 272 | |
273 | /* Test to see controller with at last one attached drive is there. | | 273 | /* Test to see controller with at last one attached drive is there. |
274 | * Returns a bit for each possible drive found (0x01 for drive 0, | | 274 | * Returns a bit for each possible drive found (0x01 for drive 0, |
275 | * 0x02 for drive 1). | | 275 | * 0x02 for drive 1). |
276 | * Logic: | | 276 | * Logic: |
277 | * - If a status register is at 0xff, assume there is no drive here | | 277 | * - If a status register is at 0xff, assume there is no drive here |
278 | * (ISA has pull-up resistors). Similarly if the status register has | | 278 | * (ISA has pull-up resistors). Similarly if the status register has |
279 | * the value we last wrote to the bus (for IDE interfaces without pullups). | | 279 | * the value we last wrote to the bus (for IDE interfaces without pullups). |
280 | * If no drive at all -> return. | | 280 | * If no drive at all -> return. |
281 | * - reset the controller, wait for it to complete (may take up to 31s !). | | 281 | * - reset the controller, wait for it to complete (may take up to 31s !). |
282 | * If timeout -> return. | | 282 | * If timeout -> return. |
283 | * - test ATA/ATAPI signatures. If at last one drive found -> return. | | 283 | * - test ATA/ATAPI signatures. If at last one drive found -> return. |
284 | * - try an ATA command on the master. | | 284 | * - try an ATA command on the master. |
285 | */ | | 285 | */ |
286 | | | 286 | |
287 | void | | 287 | void |
288 | wdc_drvprobe(struct ata_channel *chp) | | 288 | wdc_drvprobe(struct ata_channel *chp) |
289 | { | | 289 | { |
290 | struct ataparams params; /* XXX: large struct */ | | 290 | struct ataparams params; /* XXX: large struct */ |
291 | struct atac_softc *atac = chp->ch_atac; | | 291 | struct atac_softc *atac = chp->ch_atac; |
292 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 292 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
293 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 293 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
294 | u_int8_t st0 = 0, st1 = 0; | | 294 | u_int8_t st0 = 0, st1 = 0; |
295 | int i, j, error, s; | | 295 | int i, j, error, s; |
296 | | | 296 | |
297 | if (wdcprobe1(chp, 0) == 0) { | | 297 | if (wdcprobe1(chp, 0) == 0) { |
298 | /* No drives, abort the attach here. */ | | 298 | /* No drives, abort the attach here. */ |
299 | return; | | 299 | return; |
300 | } | | 300 | } |
301 | | | 301 | |
302 | #ifndef WDC_NO_IDS | | | |
303 | s = splbio(); | | 302 | s = splbio(); |
304 | #endif | | | |
305 | /* for ATA/OLD drives, wait for DRDY, 3s timeout */ | | 303 | /* for ATA/OLD drives, wait for DRDY, 3s timeout */ |
306 | for (i = 0; i < mstohz(3000); i++) { | | 304 | for (i = 0; i < mstohz(3000); i++) { |
307 | /* | | 305 | /* |
308 | * select drive 1 first, so that master is selected on | | 306 | * select drive 1 first, so that master is selected on |
309 | * exit from the loop | | 307 | * exit from the loop |
310 | */ | | 308 | */ |
311 | if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { | | 309 | if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { |
312 | if (wdc->select) | | 310 | if (wdc->select) |
313 | wdc->select(chp,1); | | 311 | wdc->select(chp,1); |
314 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 312 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
315 | 0, WDSD_IBM | 0x10); | | 313 | 0, WDSD_IBM | 0x10); |
316 | delay(10); /* 400ns delay */ | | 314 | delay(10); /* 400ns delay */ |
317 | st1 = bus_space_read_1(wdr->cmd_iot, | | 315 | st1 = bus_space_read_1(wdr->cmd_iot, |
318 | wdr->cmd_iohs[wd_status], 0); | | 316 | wdr->cmd_iohs[wd_status], 0); |
319 | } | | 317 | } |
320 | if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { | | 318 | if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { |
321 | if (wdc->select) | | 319 | if (wdc->select) |
322 | wdc->select(chp,0); | | 320 | wdc->select(chp,0); |
323 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 321 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
324 | 0, WDSD_IBM); | | 322 | 0, WDSD_IBM); |
325 | delay(10); /* 400ns delay */ | | 323 | delay(10); /* 400ns delay */ |
326 | st0 = bus_space_read_1(wdr->cmd_iot, | | 324 | st0 = bus_space_read_1(wdr->cmd_iot, |
327 | wdr->cmd_iohs[wd_status], 0); | | 325 | wdr->cmd_iohs[wd_status], 0); |
328 | } | | 326 | } |
329 | | | 327 | |
330 | | | 328 | |
331 | if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) | | 329 | if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) |
332 | == 0 || | | 330 | == 0 || |
333 | (st0 & WDCS_DRDY)) && | | 331 | (st0 & WDCS_DRDY)) && |
334 | ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) | | 332 | ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) |
335 | == 0 || | | 333 | == 0 || |
336 | (st1 & WDCS_DRDY))) | | 334 | (st1 & WDCS_DRDY))) |
337 | break; | | 335 | break; |
338 | #ifdef WDC_NO_IDS | | 336 | #ifdef WDC_NO_IDS |
339 | /* cannot tsleep here (can't enable IPL_BIO interrups), | | 337 | /* cannot tsleep here (can't enable IPL_BIO interrups), |
340 | * delay instead | | 338 | * delay instead |
341 | */ | | 339 | */ |
342 | delay(1000000 / hz); | | 340 | delay(1000000 / hz); |
343 | } | | | |
344 | #else | | 341 | #else |
345 | tsleep(¶ms, PRIBIO, "atadrdy", 1); | | 342 | tsleep(¶ms, PRIBIO, "atadrdy", 1); |
346 | } | | | |
347 | s = splbio(); | | | |
348 | #endif | | 343 | #endif |
| | | 344 | } |
349 | if ((st0 & WDCS_DRDY) == 0) | | 345 | if ((st0 & WDCS_DRDY) == 0) |
350 | chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); | | 346 | chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); |
351 | if ((st1 & WDCS_DRDY) == 0) | | 347 | if ((st1 & WDCS_DRDY) == 0) |
352 | chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); | | 348 | chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); |
353 | splx(s); | | 349 | splx(s); |
354 | | | 350 | |
355 | ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", | | 351 | ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", |
356 | device_xname(atac->atac_dev), | | 352 | device_xname(atac->atac_dev), |
357 | chp->ch_channel, st0, st1), DEBUG_PROBE); | | 353 | chp->ch_channel, st0, st1), DEBUG_PROBE); |
358 | | | 354 | |
359 | /* Wait a bit, some devices are weird just after a reset. */ | | 355 | /* Wait a bit, some devices are weird just after a reset. */ |
360 | delay(5000); | | 356 | delay(5000); |
361 | | | 357 | |
362 | for (i = 0; i < chp->ch_ndrive; i++) { | | 358 | for (i = 0; i < chp->ch_ndrive; i++) { |
363 | /* XXX This should be done by other code. */ | | 359 | /* XXX This should be done by other code. */ |
364 | chp->ch_drive[i].chnl_softc = chp; | | 360 | chp->ch_drive[i].chnl_softc = chp; |
365 | chp->ch_drive[i].drive = i; | | 361 | chp->ch_drive[i].drive = i; |
366 | | | 362 | |
367 | #if NATA_DMA | | 363 | #if NATA_DMA |
368 | /* | | 364 | /* |
369 | * Init error counter so that an error withing the first xfers | | 365 | * Init error counter so that an error withing the first xfers |
370 | * will trigger a downgrade | | 366 | * will trigger a downgrade |
371 | */ | | 367 | */ |
372 | chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; | | 368 | chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; |
373 | #endif | | 369 | #endif |
374 | | | 370 | |
375 | /* If controller can't do 16bit flag the drives as 32bit */ | | 371 | /* If controller can't do 16bit flag the drives as 32bit */ |
376 | if ((atac->atac_cap & | | 372 | if ((atac->atac_cap & |
377 | (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { | | 373 | (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { |
378 | s = splbio(); | | 374 | s = splbio(); |
379 | chp->ch_drive[i].drive_flags |= DRIVE_CAP32; | | 375 | chp->ch_drive[i].drive_flags |= DRIVE_CAP32; |
380 | splx(s); | | 376 | splx(s); |
381 | } | | 377 | } |
382 | if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) | | 378 | if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) |
383 | continue; | | 379 | continue; |
384 | | | 380 | |
385 | /* Shortcut in case we've been shutdown */ | | 381 | /* Shortcut in case we've been shutdown */ |
386 | if (chp->ch_flags & ATACH_SHUTDOWN) | | 382 | if (chp->ch_flags & ATACH_SHUTDOWN) |
387 | return; | | 383 | return; |
388 | | | 384 | |
389 | /* | | 385 | /* |
390 | * Issue an identify, to try to detect ghosts. | | 386 | * Issue an identify, to try to detect ghosts. |
391 | * Note that we can't use interrupts here, because if there | | 387 | * Note that we can't use interrupts here, because if there |
392 | * is no devices, we will get a command aborted without | | 388 | * is no devices, we will get a command aborted without |
393 | * interrupts. | | 389 | * interrupts. |
394 | */ | | 390 | */ |
395 | error = ata_get_params(&chp->ch_drive[i], | | 391 | error = ata_get_params(&chp->ch_drive[i], |
396 | AT_WAIT | AT_POLL, ¶ms); | | 392 | AT_WAIT | AT_POLL, ¶ms); |
397 | if (error != CMD_OK) { | | 393 | if (error != CMD_OK) { |
398 | tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); | | 394 | tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); |
399 | | | 395 | |
400 | /* Shortcut in case we've been shutdown */ | | 396 | /* Shortcut in case we've been shutdown */ |
401 | if (chp->ch_flags & ATACH_SHUTDOWN) | | 397 | if (chp->ch_flags & ATACH_SHUTDOWN) |
402 | return; | | 398 | return; |
403 | | | 399 | |
404 | error = ata_get_params(&chp->ch_drive[i], | | 400 | error = ata_get_params(&chp->ch_drive[i], |
405 | AT_WAIT | AT_POLL, ¶ms); | | 401 | AT_WAIT | AT_POLL, ¶ms); |
406 | } | | 402 | } |
407 | if (error == CMD_OK) { | | 403 | if (error == CMD_OK) { |
408 | /* If IDENTIFY succeeded, this is not an OLD ctrl */ | | 404 | /* If IDENTIFY succeeded, this is not an OLD ctrl */ |
409 | s = splbio(); | | 405 | s = splbio(); |
410 | for (j = 0; j < chp->ch_ndrive; j++) | | 406 | for (j = 0; j < chp->ch_ndrive; j++) |
411 | chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; | | 407 | chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; |
412 | splx(s); | | 408 | splx(s); |
413 | } else { | | 409 | } else { |
414 | s = splbio(); | | 410 | s = splbio(); |
415 | chp->ch_drive[i].drive_flags &= | | 411 | chp->ch_drive[i].drive_flags &= |
416 | ~(DRIVE_ATA | DRIVE_ATAPI); | | 412 | ~(DRIVE_ATA | DRIVE_ATAPI); |
417 | splx(s); | | 413 | splx(s); |
418 | ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", | | 414 | ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", |
419 | device_xname(atac->atac_dev), | | 415 | device_xname(atac->atac_dev), |
420 | chp->ch_channel, i, error), DEBUG_PROBE); | | 416 | chp->ch_channel, i, error), DEBUG_PROBE); |
421 | if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) | | 417 | if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) |
422 | continue; | | 418 | continue; |
423 | /* | | 419 | /* |
424 | * Pre-ATA drive ? | | 420 | * Pre-ATA drive ? |
425 | * Test registers writability (Error register not | | 421 | * Test registers writability (Error register not |
426 | * writable, but cyllo is), then try an ATA command. | | 422 | * writable, but cyllo is), then try an ATA command. |
427 | */ | | 423 | */ |
428 | if (wdc->select) | | 424 | if (wdc->select) |
429 | wdc->select(chp,i); | | 425 | wdc->select(chp,i); |
430 | bus_space_write_1(wdr->cmd_iot, | | 426 | bus_space_write_1(wdr->cmd_iot, |
431 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); | | 427 | wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); |
432 | delay(10); /* 400ns delay */ | | 428 | delay(10); /* 400ns delay */ |
433 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], | | 429 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], |
434 | 0, 0x58); | | 430 | 0, 0x58); |
435 | bus_space_write_1(wdr->cmd_iot, | | 431 | bus_space_write_1(wdr->cmd_iot, |
436 | wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); | | 432 | wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); |
437 | if (bus_space_read_1(wdr->cmd_iot, | | 433 | if (bus_space_read_1(wdr->cmd_iot, |
438 | wdr->cmd_iohs[wd_error], 0) == 0x58 || | | 434 | wdr->cmd_iohs[wd_error], 0) == 0x58 || |
439 | bus_space_read_1(wdr->cmd_iot, | | 435 | bus_space_read_1(wdr->cmd_iot, |
440 | wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { | | 436 | wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { |
441 | ATADEBUG_PRINT(("%s:%d:%d: register " | | 437 | ATADEBUG_PRINT(("%s:%d:%d: register " |
442 | "writability failed\n", | | 438 | "writability failed\n", |
443 | device_xname(atac->atac_dev), | | 439 | device_xname(atac->atac_dev), |
444 | chp->ch_channel, i), DEBUG_PROBE); | | 440 | chp->ch_channel, i), DEBUG_PROBE); |
445 | s = splbio(); | | 441 | s = splbio(); |
446 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; | | 442 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; |
447 | splx(s); | | 443 | splx(s); |
448 | continue; | | 444 | continue; |
449 | } | | 445 | } |
450 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { | | 446 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { |
451 | ATADEBUG_PRINT(("%s:%d:%d: not ready\n", | | 447 | ATADEBUG_PRINT(("%s:%d:%d: not ready\n", |
452 | device_xname(atac->atac_dev), | | 448 | device_xname(atac->atac_dev), |
453 | chp->ch_channel, i), DEBUG_PROBE); | | 449 | chp->ch_channel, i), DEBUG_PROBE); |
454 | s = splbio(); | | 450 | s = splbio(); |
455 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; | | 451 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; |
456 | splx(s); | | 452 | splx(s); |
457 | continue; | | 453 | continue; |
458 | } | | 454 | } |
459 | bus_space_write_1(wdr->cmd_iot, | | 455 | bus_space_write_1(wdr->cmd_iot, |
460 | wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); | | 456 | wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); |
461 | delay(10); /* 400ns delay */ | | 457 | delay(10); /* 400ns delay */ |
462 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { | | 458 | if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { |
463 | ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", | | 459 | ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", |
464 | device_xname(atac->atac_dev), | | 460 | device_xname(atac->atac_dev), |
465 | chp->ch_channel, i), DEBUG_PROBE); | | 461 | chp->ch_channel, i), DEBUG_PROBE); |
466 | s = splbio(); | | 462 | s = splbio(); |
467 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; | | 463 | chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; |
468 | splx(s); | | 464 | splx(s); |
469 | } else { | | 465 | } else { |
470 | s = splbio(); | | 466 | s = splbio(); |
471 | for (j = 0; j < chp->ch_ndrive; j++) | | 467 | for (j = 0; j < chp->ch_ndrive; j++) |
472 | chp->ch_drive[j].drive_flags &= | | 468 | chp->ch_drive[j].drive_flags &= |
473 | ~(DRIVE_ATA | DRIVE_ATAPI); | | 469 | ~(DRIVE_ATA | DRIVE_ATAPI); |
474 | splx(s); | | 470 | splx(s); |
475 | } | | 471 | } |
476 | } | | 472 | } |
477 | } | | 473 | } |
478 | } | | 474 | } |
479 | | | 475 | |
480 | int | | 476 | int |
481 | wdcprobe(struct ata_channel *chp) | | 477 | wdcprobe(struct ata_channel *chp) |
482 | { | | 478 | { |
483 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 479 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
484 | /* default reset method */ | | 480 | /* default reset method */ |
485 | if (wdc->reset == NULL) | | 481 | if (wdc->reset == NULL) |
486 | wdc->reset = wdc_do_reset; | | 482 | wdc->reset = wdc_do_reset; |
487 | | | 483 | |
488 | return (wdcprobe1(chp, 1)); | | 484 | return (wdcprobe1(chp, 1)); |
489 | } | | 485 | } |
490 | | | 486 | |
491 | static int | | 487 | static int |
492 | wdcprobe1(struct ata_channel *chp, int poll) | | 488 | wdcprobe1(struct ata_channel *chp, int poll) |
493 | { | | 489 | { |
494 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 490 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
495 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 491 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
496 | u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; | | 492 | u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; |
497 | u_int8_t ret_value = 0x03; | | 493 | u_int8_t ret_value = 0x03; |
498 | u_int8_t drive; | | 494 | u_int8_t drive; |
499 | int s; | | 495 | int s; |
500 | /* XXX if poll, wdc_probe_count is 0. */ | | 496 | /* XXX if poll, wdc_probe_count is 0. */ |
501 | int wdc_probe_count = | | 497 | int wdc_probe_count = |
502 | poll ? (WDC_PROBE_WAIT / WDCDELAY) | | 498 | poll ? (WDC_PROBE_WAIT / WDCDELAY) |
503 | : (WDC_PROBE_WAIT * hz); | | 499 | : (WDC_PROBE_WAIT * hz); |
504 | | | 500 | |
505 | /* | | 501 | /* |
506 | * Sanity check to see if the wdc channel responds at all. | | 502 | * Sanity check to see if the wdc channel responds at all. |
507 | */ | | 503 | */ |
508 | | | 504 | |
509 | s = splbio(); | | 505 | s = splbio(); |
510 | if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { | | 506 | if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { |
511 | while (wdc_probe_count-- > 0) { | | 507 | while (wdc_probe_count-- > 0) { |
512 | if (wdc->select) | | 508 | if (wdc->select) |
513 | wdc->select(chp,0); | | 509 | wdc->select(chp,0); |
514 | | | 510 | |
515 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 511 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
516 | 0, WDSD_IBM); | | 512 | 0, WDSD_IBM); |
517 | delay(10); /* 400ns delay */ | | 513 | delay(10); /* 400ns delay */ |
518 | st0 = bus_space_read_1(wdr->cmd_iot, | | 514 | st0 = bus_space_read_1(wdr->cmd_iot, |
519 | wdr->cmd_iohs[wd_status], 0); | | 515 | wdr->cmd_iohs[wd_status], 0); |
520 | | | 516 | |
521 | if (wdc->select) | | 517 | if (wdc->select) |
522 | wdc->select(chp,1); | | 518 | wdc->select(chp,1); |
523 | | | 519 | |
524 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 520 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
525 | 0, WDSD_IBM | 0x10); | | 521 | 0, WDSD_IBM | 0x10); |
526 | delay(10); /* 400ns delay */ | | 522 | delay(10); /* 400ns delay */ |
527 | st1 = bus_space_read_1(wdr->cmd_iot, | | 523 | st1 = bus_space_read_1(wdr->cmd_iot, |
528 | wdr->cmd_iohs[wd_status], 0); | | 524 | wdr->cmd_iohs[wd_status], 0); |
529 | if ((st0 & WDCS_BSY) == 0) | | 525 | if ((st0 & WDCS_BSY) == 0) |
530 | break; | | 526 | break; |
531 | } | | 527 | } |
532 | | | 528 | |
533 | ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", | | 529 | ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", |
534 | device_xname(chp->ch_atac->atac_dev), | | 530 | device_xname(chp->ch_atac->atac_dev), |
535 | chp->ch_channel, st0, st1), DEBUG_PROBE); | | 531 | chp->ch_channel, st0, st1), DEBUG_PROBE); |
536 | | | 532 | |
537 | if (st0 == 0xff || st0 == WDSD_IBM) | | 533 | if (st0 == 0xff || st0 == WDSD_IBM) |
538 | ret_value &= ~0x01; | | 534 | ret_value &= ~0x01; |
539 | if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) | | 535 | if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) |
540 | ret_value &= ~0x02; | | 536 | ret_value &= ~0x02; |
541 | /* Register writability test, drive 0. */ | | 537 | /* Register writability test, drive 0. */ |
542 | if (ret_value & 0x01) { | | 538 | if (ret_value & 0x01) { |
543 | if (wdc->select) | | 539 | if (wdc->select) |
544 | wdc->select(chp,0); | | 540 | wdc->select(chp,0); |
545 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 541 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
546 | 0, WDSD_IBM); | | 542 | 0, WDSD_IBM); |
547 | bus_space_write_1(wdr->cmd_iot, | | 543 | bus_space_write_1(wdr->cmd_iot, |
548 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); | | 544 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); |
549 | cl = bus_space_read_1(wdr->cmd_iot, | | 545 | cl = bus_space_read_1(wdr->cmd_iot, |
550 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 546 | wdr->cmd_iohs[wd_cyl_lo], 0); |
551 | if (cl != 0x02) { | | 547 | if (cl != 0x02) { |
552 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " | | 548 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " |
553 | "got 0x%x != 0x02\n", | | 549 | "got 0x%x != 0x02\n", |
554 | device_xname(chp->ch_atac->atac_dev), | | 550 | device_xname(chp->ch_atac->atac_dev), |
555 | chp->ch_channel, cl), | | 551 | chp->ch_channel, cl), |
556 | DEBUG_PROBE); | | 552 | DEBUG_PROBE); |
557 | ret_value &= ~0x01; | | 553 | ret_value &= ~0x01; |
558 | } | | 554 | } |
559 | bus_space_write_1(wdr->cmd_iot, | | 555 | bus_space_write_1(wdr->cmd_iot, |
560 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); | | 556 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); |
561 | cl = bus_space_read_1(wdr->cmd_iot, | | 557 | cl = bus_space_read_1(wdr->cmd_iot, |
562 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 558 | wdr->cmd_iohs[wd_cyl_lo], 0); |
563 | if (cl != 0x01) { | | 559 | if (cl != 0x01) { |
564 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " | | 560 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " |
565 | "got 0x%x != 0x01\n", | | 561 | "got 0x%x != 0x01\n", |
566 | device_xname(chp->ch_atac->atac_dev), | | 562 | device_xname(chp->ch_atac->atac_dev), |
567 | chp->ch_channel, cl), | | 563 | chp->ch_channel, cl), |
568 | DEBUG_PROBE); | | 564 | DEBUG_PROBE); |
569 | ret_value &= ~0x01; | | 565 | ret_value &= ~0x01; |
570 | } | | 566 | } |
571 | bus_space_write_1(wdr->cmd_iot, | | 567 | bus_space_write_1(wdr->cmd_iot, |
572 | wdr->cmd_iohs[wd_sector], 0, 0x01); | | 568 | wdr->cmd_iohs[wd_sector], 0, 0x01); |
573 | cl = bus_space_read_1(wdr->cmd_iot, | | 569 | cl = bus_space_read_1(wdr->cmd_iot, |
574 | wdr->cmd_iohs[wd_sector], 0); | | 570 | wdr->cmd_iohs[wd_sector], 0); |
575 | if (cl != 0x01) { | | 571 | if (cl != 0x01) { |
576 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " | | 572 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " |
577 | "got 0x%x != 0x01\n", | | 573 | "got 0x%x != 0x01\n", |
578 | device_xname(chp->ch_atac->atac_dev), | | 574 | device_xname(chp->ch_atac->atac_dev), |
579 | chp->ch_channel, cl), | | 575 | chp->ch_channel, cl), |
580 | DEBUG_PROBE); | | 576 | DEBUG_PROBE); |
581 | ret_value &= ~0x01; | | 577 | ret_value &= ~0x01; |
582 | } | | 578 | } |
583 | bus_space_write_1(wdr->cmd_iot, | | 579 | bus_space_write_1(wdr->cmd_iot, |
584 | wdr->cmd_iohs[wd_sector], 0, 0x02); | | 580 | wdr->cmd_iohs[wd_sector], 0, 0x02); |
585 | cl = bus_space_read_1(wdr->cmd_iot, | | 581 | cl = bus_space_read_1(wdr->cmd_iot, |
586 | wdr->cmd_iohs[wd_sector], 0); | | 582 | wdr->cmd_iohs[wd_sector], 0); |
587 | if (cl != 0x02) { | | 583 | if (cl != 0x02) { |
588 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " | | 584 | ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " |
589 | "got 0x%x != 0x02\n", | | 585 | "got 0x%x != 0x02\n", |
590 | device_xname(chp->ch_atac->atac_dev), | | 586 | device_xname(chp->ch_atac->atac_dev), |
591 | chp->ch_channel, cl), | | 587 | chp->ch_channel, cl), |
592 | DEBUG_PROBE); | | 588 | DEBUG_PROBE); |
593 | ret_value &= ~0x01; | | 589 | ret_value &= ~0x01; |
594 | } | | 590 | } |
595 | cl = bus_space_read_1(wdr->cmd_iot, | | 591 | cl = bus_space_read_1(wdr->cmd_iot, |
596 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 592 | wdr->cmd_iohs[wd_cyl_lo], 0); |
597 | if (cl != 0x01) { | | 593 | if (cl != 0x01) { |
598 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " | | 594 | ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " |
599 | "got 0x%x != 0x01\n", | | 595 | "got 0x%x != 0x01\n", |
600 | device_xname(chp->ch_atac->atac_dev), | | 596 | device_xname(chp->ch_atac->atac_dev), |
601 | chp->ch_channel, cl), | | 597 | chp->ch_channel, cl), |
602 | DEBUG_PROBE); | | 598 | DEBUG_PROBE); |
603 | ret_value &= ~0x01; | | 599 | ret_value &= ~0x01; |
604 | } | | 600 | } |
605 | } | | 601 | } |
606 | /* Register writability test, drive 1. */ | | 602 | /* Register writability test, drive 1. */ |
607 | if (ret_value & 0x02) { | | 603 | if (ret_value & 0x02) { |
608 | if (wdc->select) | | 604 | if (wdc->select) |
609 | wdc->select(chp,1); | | 605 | wdc->select(chp,1); |
610 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 606 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
611 | 0, WDSD_IBM | 0x10); | | 607 | 0, WDSD_IBM | 0x10); |
612 | bus_space_write_1(wdr->cmd_iot, | | 608 | bus_space_write_1(wdr->cmd_iot, |
613 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); | | 609 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); |
614 | cl = bus_space_read_1(wdr->cmd_iot, | | 610 | cl = bus_space_read_1(wdr->cmd_iot, |
615 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 611 | wdr->cmd_iohs[wd_cyl_lo], 0); |
616 | if (cl != 0x02) { | | 612 | if (cl != 0x02) { |
617 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " | | 613 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " |
618 | "got 0x%x != 0x02\n", | | 614 | "got 0x%x != 0x02\n", |
619 | device_xname(chp->ch_atac->atac_dev), | | 615 | device_xname(chp->ch_atac->atac_dev), |
620 | chp->ch_channel, cl), | | 616 | chp->ch_channel, cl), |
621 | DEBUG_PROBE); | | 617 | DEBUG_PROBE); |
622 | ret_value &= ~0x02; | | 618 | ret_value &= ~0x02; |
623 | } | | 619 | } |
624 | bus_space_write_1(wdr->cmd_iot, | | 620 | bus_space_write_1(wdr->cmd_iot, |
625 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); | | 621 | wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); |
626 | cl = bus_space_read_1(wdr->cmd_iot, | | 622 | cl = bus_space_read_1(wdr->cmd_iot, |
627 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 623 | wdr->cmd_iohs[wd_cyl_lo], 0); |
628 | if (cl != 0x01) { | | 624 | if (cl != 0x01) { |
629 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " | | 625 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " |
630 | "got 0x%x != 0x01\n", | | 626 | "got 0x%x != 0x01\n", |
631 | device_xname(chp->ch_atac->atac_dev), | | 627 | device_xname(chp->ch_atac->atac_dev), |
632 | chp->ch_channel, cl), | | 628 | chp->ch_channel, cl), |
633 | DEBUG_PROBE); | | 629 | DEBUG_PROBE); |
634 | ret_value &= ~0x02; | | 630 | ret_value &= ~0x02; |
635 | } | | 631 | } |
636 | bus_space_write_1(wdr->cmd_iot, | | 632 | bus_space_write_1(wdr->cmd_iot, |
637 | wdr->cmd_iohs[wd_sector], 0, 0x01); | | 633 | wdr->cmd_iohs[wd_sector], 0, 0x01); |
638 | cl = bus_space_read_1(wdr->cmd_iot, | | 634 | cl = bus_space_read_1(wdr->cmd_iot, |
639 | wdr->cmd_iohs[wd_sector], 0); | | 635 | wdr->cmd_iohs[wd_sector], 0); |
640 | if (cl != 0x01) { | | 636 | if (cl != 0x01) { |
641 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " | | 637 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " |
642 | "got 0x%x != 0x01\n", | | 638 | "got 0x%x != 0x01\n", |
643 | device_xname(chp->ch_atac->atac_dev), | | 639 | device_xname(chp->ch_atac->atac_dev), |
644 | chp->ch_channel, cl), | | 640 | chp->ch_channel, cl), |
645 | DEBUG_PROBE); | | 641 | DEBUG_PROBE); |
646 | ret_value &= ~0x02; | | 642 | ret_value &= ~0x02; |
647 | } | | 643 | } |
648 | bus_space_write_1(wdr->cmd_iot, | | 644 | bus_space_write_1(wdr->cmd_iot, |
649 | wdr->cmd_iohs[wd_sector], 0, 0x02); | | 645 | wdr->cmd_iohs[wd_sector], 0, 0x02); |
650 | cl = bus_space_read_1(wdr->cmd_iot, | | 646 | cl = bus_space_read_1(wdr->cmd_iot, |
651 | wdr->cmd_iohs[wd_sector], 0); | | 647 | wdr->cmd_iohs[wd_sector], 0); |
652 | if (cl != 0x02) { | | 648 | if (cl != 0x02) { |
653 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " | | 649 | ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " |
654 | "got 0x%x != 0x02\n", | | 650 | "got 0x%x != 0x02\n", |
655 | device_xname(chp->ch_atac->atac_dev), | | 651 | device_xname(chp->ch_atac->atac_dev), |
656 | chp->ch_channel, cl), | | 652 | chp->ch_channel, cl), |
657 | DEBUG_PROBE); | | 653 | DEBUG_PROBE); |
658 | ret_value &= ~0x02; | | 654 | ret_value &= ~0x02; |
659 | } | | 655 | } |
660 | cl = bus_space_read_1(wdr->cmd_iot, | | 656 | cl = bus_space_read_1(wdr->cmd_iot, |
661 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 657 | wdr->cmd_iohs[wd_cyl_lo], 0); |
662 | if (cl != 0x01) { | | 658 | if (cl != 0x01) { |
663 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " | | 659 | ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " |
664 | "got 0x%x != 0x01\n", | | 660 | "got 0x%x != 0x01\n", |
665 | device_xname(chp->ch_atac->atac_dev), | | 661 | device_xname(chp->ch_atac->atac_dev), |
666 | chp->ch_channel, cl), | | 662 | chp->ch_channel, cl), |
667 | DEBUG_PROBE); | | 663 | DEBUG_PROBE); |
668 | ret_value &= ~0x02; | | 664 | ret_value &= ~0x02; |
669 | } | | 665 | } |
670 | } | | 666 | } |
671 | | | 667 | |
672 | if (ret_value == 0) { | | 668 | if (ret_value == 0) { |
673 | splx(s); | | 669 | splx(s); |
674 | return 0; | | 670 | return 0; |
675 | } | | 671 | } |
676 | } | | 672 | } |
677 | | | 673 | |
678 | | | 674 | |
679 | #if 0 /* XXX this break some ATA or ATAPI devices */ | | 675 | #if 0 /* XXX this break some ATA or ATAPI devices */ |
680 | /* | | 676 | /* |
681 | * reset bus. Also send an ATAPI_RESET to devices, in case there are | | 677 | * reset bus. Also send an ATAPI_RESET to devices, in case there are |
682 | * ATAPI device out there which don't react to the bus reset | | 678 | * ATAPI device out there which don't react to the bus reset |
683 | */ | | 679 | */ |
684 | if (ret_value & 0x01) { | | 680 | if (ret_value & 0x01) { |
685 | if (wdc->select) | | 681 | if (wdc->select) |
686 | wdc->select(chp,0); | | 682 | wdc->select(chp,0); |
687 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 683 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
688 | 0, WDSD_IBM); | | 684 | 0, WDSD_IBM); |
689 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, | | 685 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, |
690 | ATAPI_SOFT_RESET); | | 686 | ATAPI_SOFT_RESET); |
691 | } | | 687 | } |
692 | if (ret_value & 0x02) { | | 688 | if (ret_value & 0x02) { |
693 | if (wdc->select) | | 689 | if (wdc->select) |
694 | wdc->select(chp,0); | | 690 | wdc->select(chp,0); |
695 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 691 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
696 | 0, WDSD_IBM | 0x10); | | 692 | 0, WDSD_IBM | 0x10); |
697 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, | | 693 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, |
698 | ATAPI_SOFT_RESET); | | 694 | ATAPI_SOFT_RESET); |
699 | } | | 695 | } |
700 | | | 696 | |
701 | delay(5000); | | 697 | delay(5000); |
702 | #endif | | 698 | #endif |
703 | | | 699 | |
704 | wdc->reset(chp, RESET_POLL); | | 700 | wdc->reset(chp, RESET_POLL); |
705 | DELAY(2000); | | 701 | DELAY(2000); |
706 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); | | 702 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); |
707 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); | | 703 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); |
708 | #ifdef WDC_NO_IDS | | 704 | #ifdef WDC_NO_IDS |
709 | ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); | | 705 | ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); |
710 | #else | | 706 | #else |
711 | splx(s); | | 707 | splx(s); |
712 | ret_value = __wdcwait_reset(chp, ret_value, poll); | | 708 | ret_value = __wdcwait_reset(chp, ret_value, poll); |
713 | s = splbio(); | | 709 | s = splbio(); |
714 | #endif | | 710 | #endif |
715 | ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", | | 711 | ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", |
716 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 712 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
717 | ret_value), DEBUG_PROBE); | | 713 | ret_value), DEBUG_PROBE); |
718 | | | 714 | |
719 | /* if reset failed, there's nothing here */ | | 715 | /* if reset failed, there's nothing here */ |
720 | if (ret_value == 0) { | | 716 | if (ret_value == 0) { |
721 | splx(s); | | 717 | splx(s); |
722 | return 0; | | 718 | return 0; |
723 | } | | 719 | } |
724 | | | 720 | |
725 | /* | | 721 | /* |
726 | * Test presence of drives. First test register signatures looking | | 722 | * Test presence of drives. First test register signatures looking |
727 | * for ATAPI devices. If it's not an ATAPI and reset said there may | | 723 | * for ATAPI devices. If it's not an ATAPI and reset said there may |
728 | * be something here assume it's ATA or OLD. Ghost will be killed | | 724 | * be something here assume it's ATA or OLD. Ghost will be killed |
729 | * later in attach routine. | | 725 | * later in attach routine. |
730 | */ | | 726 | */ |
731 | for (drive = 0; drive < chp->ch_ndrive; drive++) { | | 727 | for (drive = 0; drive < chp->ch_ndrive; drive++) { |
732 | if ((ret_value & (0x01 << drive)) == 0) | | 728 | if ((ret_value & (0x01 << drive)) == 0) |
733 | continue; | | 729 | continue; |
734 | if (wdc->select) | | 730 | if (wdc->select) |
735 | wdc->select(chp,drive); | | 731 | wdc->select(chp,drive); |
736 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 732 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
737 | WDSD_IBM | (drive << 4)); | | 733 | WDSD_IBM | (drive << 4)); |
738 | delay(10); /* 400ns delay */ | | 734 | delay(10); /* 400ns delay */ |
739 | /* Save registers contents */ | | 735 | /* Save registers contents */ |
740 | sc = bus_space_read_1(wdr->cmd_iot, | | 736 | sc = bus_space_read_1(wdr->cmd_iot, |
741 | wdr->cmd_iohs[wd_seccnt], 0); | | 737 | wdr->cmd_iohs[wd_seccnt], 0); |
742 | sn = bus_space_read_1(wdr->cmd_iot, | | 738 | sn = bus_space_read_1(wdr->cmd_iot, |
743 | wdr->cmd_iohs[wd_sector], 0); | | 739 | wdr->cmd_iohs[wd_sector], 0); |
744 | cl = bus_space_read_1(wdr->cmd_iot, | | 740 | cl = bus_space_read_1(wdr->cmd_iot, |
745 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 741 | wdr->cmd_iohs[wd_cyl_lo], 0); |
746 | ch = bus_space_read_1(wdr->cmd_iot, | | 742 | ch = bus_space_read_1(wdr->cmd_iot, |
747 | wdr->cmd_iohs[wd_cyl_hi], 0); | | 743 | wdr->cmd_iohs[wd_cyl_hi], 0); |
748 | | | 744 | |
749 | ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " | | 745 | ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " |
750 | "cl=0x%x ch=0x%x\n", | | 746 | "cl=0x%x ch=0x%x\n", |
751 | device_xname(chp->ch_atac->atac_dev), | | 747 | device_xname(chp->ch_atac->atac_dev), |
752 | chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); | | 748 | chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); |
753 | /* | | 749 | /* |
754 | * sc & sn are supposted to be 0x1 for ATAPI but in some cases | | 750 | * sc & sn are supposted to be 0x1 for ATAPI but in some cases |
755 | * we get wrong values here, so ignore it. | | 751 | * we get wrong values here, so ignore it. |
756 | */ | | 752 | */ |
757 | if (cl == 0x14 && ch == 0xeb) { | | 753 | if (cl == 0x14 && ch == 0xeb) { |
758 | chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; | | 754 | chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; |
759 | } else { | | 755 | } else { |
760 | chp->ch_drive[drive].drive_flags |= DRIVE_ATA; | | 756 | chp->ch_drive[drive].drive_flags |= DRIVE_ATA; |
761 | if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) | | 757 | if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) |
762 | chp->ch_drive[drive].drive_flags |= DRIVE_OLD; | | 758 | chp->ch_drive[drive].drive_flags |= DRIVE_OLD; |
763 | } | | 759 | } |
764 | } | | 760 | } |
765 | /* | | 761 | /* |
766 | * Select an existing drive before lowering spl, some WDC_NO_IDS | | 762 | * Select an existing drive before lowering spl, some WDC_NO_IDS |
767 | * devices incorrectly assert IRQ on nonexistent slave | | 763 | * devices incorrectly assert IRQ on nonexistent slave |
768 | */ | | 764 | */ |
769 | if (ret_value & 0x01) { | | 765 | if (ret_value & 0x01) { |
770 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 766 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
771 | WDSD_IBM); | | 767 | WDSD_IBM); |
772 | (void)bus_space_read_1(wdr->cmd_iot, | | 768 | (void)bus_space_read_1(wdr->cmd_iot, |
773 | wdr->cmd_iohs[wd_status], 0); | | 769 | wdr->cmd_iohs[wd_status], 0); |
774 | } | | 770 | } |
775 | splx(s); | | 771 | splx(s); |
776 | return (ret_value); | | 772 | return (ret_value); |
777 | } | | 773 | } |
778 | | | 774 | |
779 | void | | 775 | void |
780 | wdcattach(struct ata_channel *chp) | | 776 | wdcattach(struct ata_channel *chp) |
781 | { | | 777 | { |
782 | struct atac_softc *atac = chp->ch_atac; | | 778 | struct atac_softc *atac = chp->ch_atac; |
783 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 779 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
784 | | | 780 | |
785 | KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); | | 781 | KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); |
786 | | | 782 | |
787 | /* default data transfer methods */ | | 783 | /* default data transfer methods */ |
788 | if (wdc->datain_pio == NULL) | | 784 | if (wdc->datain_pio == NULL) |
789 | wdc->datain_pio = wdc_datain_pio; | | 785 | wdc->datain_pio = wdc_datain_pio; |
790 | if (wdc->dataout_pio == NULL) | | 786 | if (wdc->dataout_pio == NULL) |
791 | wdc->dataout_pio = wdc_dataout_pio; | | 787 | wdc->dataout_pio = wdc_dataout_pio; |
792 | /* default reset method */ | | 788 | /* default reset method */ |
793 | if (wdc->reset == NULL) | | 789 | if (wdc->reset == NULL) |
794 | wdc->reset = wdc_do_reset; | | 790 | wdc->reset = wdc_do_reset; |
795 | | | 791 | |
796 | /* initialise global data */ | | 792 | /* initialise global data */ |
797 | if (atac->atac_bustype_ata == NULL) | | 793 | if (atac->atac_bustype_ata == NULL) |
798 | atac->atac_bustype_ata = &wdc_ata_bustype; | | 794 | atac->atac_bustype_ata = &wdc_ata_bustype; |
799 | if (atac->atac_probe == NULL) | | 795 | if (atac->atac_probe == NULL) |
800 | atac->atac_probe = wdc_drvprobe; | | 796 | atac->atac_probe = wdc_drvprobe; |
801 | #if NATAPIBUS > 0 | | 797 | #if NATAPIBUS > 0 |
802 | if (atac->atac_atapibus_attach == NULL) | | 798 | if (atac->atac_atapibus_attach == NULL) |
803 | atac->atac_atapibus_attach = wdc_atapibus_attach; | | 799 | atac->atac_atapibus_attach = wdc_atapibus_attach; |
804 | #endif | | 800 | #endif |
805 | | | 801 | |
806 | ata_channel_attach(chp); | | 802 | ata_channel_attach(chp); |
807 | } | | 803 | } |
808 | | | 804 | |
809 | void | | 805 | void |
810 | wdc_childdetached(device_t self, device_t child) | | 806 | wdc_childdetached(device_t self, device_t child) |
811 | { | | 807 | { |
812 | struct atac_softc *atac = device_private(self); | | 808 | struct atac_softc *atac = device_private(self); |
813 | struct ata_channel *chp; | | 809 | struct ata_channel *chp; |
814 | int i; | | 810 | int i; |
815 | | | 811 | |
816 | for (i = 0; i < atac->atac_nchannels; i++) { | | 812 | for (i = 0; i < atac->atac_nchannels; i++) { |
817 | chp = atac->atac_channels[i]; | | 813 | chp = atac->atac_channels[i]; |
818 | if (child == chp->atabus) { | | 814 | if (child == chp->atabus) { |
819 | chp->atabus = NULL; | | 815 | chp->atabus = NULL; |
820 | return; | | 816 | return; |
821 | } | | 817 | } |
822 | } | | 818 | } |
823 | } | | 819 | } |
824 | | | 820 | |
825 | int | | 821 | int |
826 | wdcdetach(device_t self, int flags) | | 822 | wdcdetach(device_t self, int flags) |
827 | { | | 823 | { |
828 | struct atac_softc *atac = device_private(self); | | 824 | struct atac_softc *atac = device_private(self); |
829 | struct ata_channel *chp; | | 825 | struct ata_channel *chp; |
830 | struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; | | 826 | struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; |
831 | int i, error = 0; | | 827 | int i, error = 0; |
832 | | | 828 | |
833 | for (i = 0; i < atac->atac_nchannels; i++) { | | 829 | for (i = 0; i < atac->atac_nchannels; i++) { |
834 | chp = atac->atac_channels[i]; | | 830 | chp = atac->atac_channels[i]; |
835 | if (chp->atabus == NULL) | | 831 | if (chp->atabus == NULL) |
836 | continue; | | 832 | continue; |
837 | ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", | | 833 | ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", |
838 | device_xname(atac->atac_dev), device_xname(chp->atabus)), | | 834 | device_xname(atac->atac_dev), device_xname(chp->atabus)), |
839 | DEBUG_DETACH); | | 835 | DEBUG_DETACH); |
840 | if ((error = config_detach(chp->atabus, flags)) != 0) | | 836 | if ((error = config_detach(chp->atabus, flags)) != 0) |
841 | return error; | | 837 | return error; |
842 | } | | 838 | } |
843 | if (adapt->adapt_refcnt != 0) | | 839 | if (adapt->adapt_refcnt != 0) |
844 | return EBUSY; | | 840 | return EBUSY; |
845 | return 0; | | 841 | return 0; |
846 | } | | 842 | } |
847 | | | 843 | |
848 | /* restart an interrupted I/O */ | | 844 | /* restart an interrupted I/O */ |
849 | void | | 845 | void |
850 | wdcrestart(void *v) | | 846 | wdcrestart(void *v) |
851 | { | | 847 | { |
852 | struct ata_channel *chp = v; | | 848 | struct ata_channel *chp = v; |
853 | int s; | | 849 | int s; |
854 | | | 850 | |
855 | s = splbio(); | | 851 | s = splbio(); |
856 | atastart(chp); | | 852 | atastart(chp); |
857 | splx(s); | | 853 | splx(s); |
858 | } | | 854 | } |
859 | | | 855 | |
860 | | | 856 | |
861 | /* | | 857 | /* |
862 | * Interrupt routine for the controller. Acknowledge the interrupt, check for | | 858 | * Interrupt routine for the controller. Acknowledge the interrupt, check for |
863 | * errors on the current operation, mark it done if necessary, and start the | | 859 | * errors on the current operation, mark it done if necessary, and start the |
864 | * next request. Also check for a partially done transfer, and continue with | | 860 | * next request. Also check for a partially done transfer, and continue with |
865 | * the next chunk if so. | | 861 | * the next chunk if so. |
866 | */ | | 862 | */ |
867 | int | | 863 | int |
868 | wdcintr(void *arg) | | 864 | wdcintr(void *arg) |
869 | { | | 865 | { |
870 | struct ata_channel *chp = arg; | | 866 | struct ata_channel *chp = arg; |
871 | struct atac_softc *atac = chp->ch_atac; | | 867 | struct atac_softc *atac = chp->ch_atac; |
872 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 868 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
873 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 869 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
874 | struct ata_xfer *xfer; | | 870 | struct ata_xfer *xfer; |
875 | int ret; | | 871 | int ret; |
876 | | | 872 | |
877 | if (!device_is_active(atac->atac_dev)) { | | 873 | if (!device_is_active(atac->atac_dev)) { |
878 | ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), | | 874 | ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), |
879 | DEBUG_INTR); | | 875 | DEBUG_INTR); |
880 | return (0); | | 876 | return (0); |
881 | } | | 877 | } |
882 | if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { | | 878 | if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { |
883 | ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); | | 879 | ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); |
884 | /* try to clear the pending interrupt anyway */ | | 880 | /* try to clear the pending interrupt anyway */ |
885 | (void)bus_space_read_1(wdr->cmd_iot, | | 881 | (void)bus_space_read_1(wdr->cmd_iot, |
886 | wdr->cmd_iohs[wd_status], 0); | | 882 | wdr->cmd_iohs[wd_status], 0); |
887 | return (0); | | 883 | return (0); |
888 | } | | 884 | } |
889 | | | 885 | |
890 | ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); | | 886 | ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); |
891 | xfer = chp->ch_queue->active_xfer; | | 887 | xfer = chp->ch_queue->active_xfer; |
892 | #ifdef DIAGNOSTIC | | 888 | #ifdef DIAGNOSTIC |
893 | if (xfer == NULL) | | 889 | if (xfer == NULL) |
894 | panic("wdcintr: no xfer"); | | 890 | panic("wdcintr: no xfer"); |
895 | if (xfer->c_chp != chp) { | | 891 | if (xfer->c_chp != chp) { |
896 | printf("channel %d expected %d\n", xfer->c_chp->ch_channel, | | 892 | printf("channel %d expected %d\n", xfer->c_chp->ch_channel, |
897 | chp->ch_channel); | | 893 | chp->ch_channel); |
898 | panic("wdcintr: wrong channel"); | | 894 | panic("wdcintr: wrong channel"); |
899 | } | | 895 | } |
900 | #endif | | 896 | #endif |
901 | #if NATA_DMA || NATA_PIOBM | | 897 | #if NATA_DMA || NATA_PIOBM |
902 | if (chp->ch_flags & ATACH_DMA_WAIT) { | | 898 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
903 | wdc->dma_status = | | 899 | wdc->dma_status = |
904 | (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, | | 900 | (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, |
905 | xfer->c_drive, WDC_DMAEND_END); | | 901 | xfer->c_drive, WDC_DMAEND_END); |
906 | if (wdc->dma_status & WDC_DMAST_NOIRQ) { | | 902 | if (wdc->dma_status & WDC_DMAST_NOIRQ) { |
907 | /* IRQ not for us, not detected by DMA engine */ | | 903 | /* IRQ not for us, not detected by DMA engine */ |
908 | return 0; | | 904 | return 0; |
909 | } | | 905 | } |
910 | chp->ch_flags &= ~ATACH_DMA_WAIT; | | 906 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
911 | } | | 907 | } |
912 | #endif | | 908 | #endif |
913 | chp->ch_flags &= ~ATACH_IRQ_WAIT; | | 909 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
914 | KASSERT(xfer->c_intr != NULL); | | 910 | KASSERT(xfer->c_intr != NULL); |
915 | ret = xfer->c_intr(chp, xfer, 1); | | 911 | ret = xfer->c_intr(chp, xfer, 1); |
916 | if (ret == 0) /* irq was not for us, still waiting for irq */ | | 912 | if (ret == 0) /* irq was not for us, still waiting for irq */ |
917 | chp->ch_flags |= ATACH_IRQ_WAIT; | | 913 | chp->ch_flags |= ATACH_IRQ_WAIT; |
918 | return (ret); | | 914 | return (ret); |
919 | } | | 915 | } |
920 | | | 916 | |
921 | /* Put all disk in RESET state */ | | 917 | /* Put all disk in RESET state */ |
922 | void | | 918 | void |
923 | wdc_reset_drive(struct ata_drive_datas *drvp, int flags) | | 919 | wdc_reset_drive(struct ata_drive_datas *drvp, int flags) |
924 | { | | 920 | { |
925 | struct ata_channel *chp = drvp->chnl_softc; | | 921 | struct ata_channel *chp = drvp->chnl_softc; |
926 | | | 922 | |
927 | ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", | | 923 | ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", |
928 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 924 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
929 | drvp->drive), DEBUG_FUNCS); | | 925 | drvp->drive), DEBUG_FUNCS); |
930 | | | 926 | |
931 | ata_reset_channel(chp, flags); | | 927 | ata_reset_channel(chp, flags); |
932 | } | | 928 | } |
933 | | | 929 | |
934 | void | | 930 | void |
935 | wdc_reset_channel(struct ata_channel *chp, int flags) | | 931 | wdc_reset_channel(struct ata_channel *chp, int flags) |
936 | { | | 932 | { |
937 | TAILQ_HEAD(, ata_xfer) reset_xfer; | | 933 | TAILQ_HEAD(, ata_xfer) reset_xfer; |
938 | struct ata_xfer *xfer, *next_xfer; | | 934 | struct ata_xfer *xfer, *next_xfer; |
939 | #if NATA_DMA || NATA_PIOBM | | 935 | #if NATA_DMA || NATA_PIOBM |
940 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 936 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
941 | #endif | | 937 | #endif |
942 | TAILQ_INIT(&reset_xfer); | | 938 | TAILQ_INIT(&reset_xfer); |
943 | | | 939 | |
944 | chp->ch_flags &= ~ATACH_IRQ_WAIT; | | 940 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
945 | | | 941 | |
946 | /* | | 942 | /* |
947 | * if the current command if on an ATAPI device, issue a | | 943 | * if the current command if on an ATAPI device, issue a |
948 | * ATAPI_SOFT_RESET | | 944 | * ATAPI_SOFT_RESET |
949 | */ | | 945 | */ |
950 | xfer = chp->ch_queue->active_xfer; | | 946 | xfer = chp->ch_queue->active_xfer; |
951 | if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { | | 947 | if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { |
952 | wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); | | 948 | wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); |
953 | if (flags & AT_WAIT) | | 949 | if (flags & AT_WAIT) |
954 | tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); | | 950 | tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); |
955 | else | | 951 | else |
956 | delay(1000); | | 952 | delay(1000); |
957 | } | | 953 | } |
958 | | | 954 | |
959 | /* reset the channel */ | | 955 | /* reset the channel */ |
960 | if (flags & AT_WAIT) | | 956 | if (flags & AT_WAIT) |
961 | (void) wdcreset(chp, RESET_SLEEP); | | 957 | (void) wdcreset(chp, RESET_SLEEP); |
962 | else | | 958 | else |
963 | (void) wdcreset(chp, RESET_POLL); | | 959 | (void) wdcreset(chp, RESET_POLL); |
964 | | | 960 | |
965 | /* | | 961 | /* |
966 | * wait a bit after reset; in case the DMA engines needs some time | | 962 | * wait a bit after reset; in case the DMA engines needs some time |
967 | * to recover. | | 963 | * to recover. |
968 | */ | | 964 | */ |
969 | if (flags & AT_WAIT) | | 965 | if (flags & AT_WAIT) |
970 | tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); | | 966 | tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); |
971 | else | | 967 | else |
972 | delay(1000); | | 968 | delay(1000); |
973 | /* | | 969 | /* |
974 | * look for pending xfers. If we have a shared queue, we'll also reset | | 970 | * look for pending xfers. If we have a shared queue, we'll also reset |
975 | * the other channel if the current xfer is running on it. | | 971 | * the other channel if the current xfer is running on it. |
976 | * Then we'll dequeue only the xfers for this channel. | | 972 | * Then we'll dequeue only the xfers for this channel. |
977 | */ | | 973 | */ |
978 | if ((flags & AT_RST_NOCMD) == 0) { | | 974 | if ((flags & AT_RST_NOCMD) == 0) { |
979 | /* | | 975 | /* |
980 | * move all xfers queued for this channel to the reset queue, | | 976 | * move all xfers queued for this channel to the reset queue, |
981 | * and then process the current xfer and then the reset queue. | | 977 | * and then process the current xfer and then the reset queue. |
982 | * We have to use a temporary queue because c_kill_xfer() | | 978 | * We have to use a temporary queue because c_kill_xfer() |
983 | * may requeue commands. | | 979 | * may requeue commands. |
984 | */ | | 980 | */ |
985 | for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); | | 981 | for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); |
986 | xfer != NULL; xfer = next_xfer) { | | 982 | xfer != NULL; xfer = next_xfer) { |
987 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); | | 983 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); |
988 | if (xfer->c_chp != chp) | | 984 | if (xfer->c_chp != chp) |
989 | continue; | | 985 | continue; |
990 | TAILQ_REMOVE(&chp->ch_queue->queue_xfer, | | 986 | TAILQ_REMOVE(&chp->ch_queue->queue_xfer, |
991 | xfer, c_xferchain); | | 987 | xfer, c_xferchain); |
992 | TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); | | 988 | TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); |
993 | } | | 989 | } |
994 | xfer = chp->ch_queue->active_xfer; | | 990 | xfer = chp->ch_queue->active_xfer; |
995 | if (xfer) { | | 991 | if (xfer) { |
996 | if (xfer->c_chp != chp) | | 992 | if (xfer->c_chp != chp) |
997 | ata_reset_channel(xfer->c_chp, flags); | | 993 | ata_reset_channel(xfer->c_chp, flags); |
998 | else { | | 994 | else { |
999 | callout_stop(&chp->ch_callout); | | 995 | callout_stop(&chp->ch_callout); |
1000 | #if NATA_DMA || NATA_PIOBM | | 996 | #if NATA_DMA || NATA_PIOBM |
1001 | /* | | 997 | /* |
1002 | * If we're waiting for DMA, stop the | | 998 | * If we're waiting for DMA, stop the |
1003 | * DMA engine | | 999 | * DMA engine |
1004 | */ | | 1000 | */ |
1005 | if (chp->ch_flags & ATACH_DMA_WAIT) { | | 1001 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
1006 | (*wdc->dma_finish)( | | 1002 | (*wdc->dma_finish)( |
1007 | wdc->dma_arg, | | 1003 | wdc->dma_arg, |
1008 | chp->ch_channel, | | 1004 | chp->ch_channel, |
1009 | xfer->c_drive, | | 1005 | xfer->c_drive, |
1010 | WDC_DMAEND_ABRT_QUIET); | | 1006 | WDC_DMAEND_ABRT_QUIET); |
1011 | chp->ch_flags &= ~ATACH_DMA_WAIT; | | 1007 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
1012 | } | | 1008 | } |
1013 | #endif | | 1009 | #endif |
1014 | chp->ch_queue->active_xfer = NULL; | | 1010 | chp->ch_queue->active_xfer = NULL; |
1015 | if ((flags & AT_RST_EMERG) == 0) | | 1011 | if ((flags & AT_RST_EMERG) == 0) |
1016 | xfer->c_kill_xfer( | | 1012 | xfer->c_kill_xfer( |
1017 | chp, xfer, KILL_RESET); | | 1013 | chp, xfer, KILL_RESET); |
1018 | } | | 1014 | } |
1019 | } | | 1015 | } |
1020 | | | 1016 | |
1021 | for (xfer = TAILQ_FIRST(&reset_xfer); | | 1017 | for (xfer = TAILQ_FIRST(&reset_xfer); |
1022 | xfer != NULL; xfer = next_xfer) { | | 1018 | xfer != NULL; xfer = next_xfer) { |
1023 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); | | 1019 | next_xfer = TAILQ_NEXT(xfer, c_xferchain); |
1024 | TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); | | 1020 | TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); |
1025 | if ((flags & AT_RST_EMERG) == 0) | | 1021 | if ((flags & AT_RST_EMERG) == 0) |
1026 | xfer->c_kill_xfer(chp, xfer, KILL_RESET); | | 1022 | xfer->c_kill_xfer(chp, xfer, KILL_RESET); |
1027 | } | | 1023 | } |
1028 | } | | 1024 | } |
1029 | } | | 1025 | } |
1030 | | | 1026 | |
1031 | static int | | 1027 | static int |
1032 | wdcreset(struct ata_channel *chp, int poll) | | 1028 | wdcreset(struct ata_channel *chp, int poll) |
1033 | { | | 1029 | { |
1034 | struct atac_softc *atac = chp->ch_atac; | | 1030 | struct atac_softc *atac = chp->ch_atac; |
1035 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1031 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1036 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1032 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1037 | int drv_mask1, drv_mask2; | | 1033 | int drv_mask1, drv_mask2; |
1038 | | | 1034 | |
1039 | #ifdef WDC_NO_IDS | | 1035 | #ifdef WDC_NO_IDS |
1040 | poll = RESET_POLL; | | 1036 | poll = RESET_POLL; |
1041 | #endif | | 1037 | #endif |
1042 | wdc->reset(chp, poll); | | 1038 | wdc->reset(chp, poll); |
1043 | | | 1039 | |
1044 | drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; | | 1040 | drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; |
1045 | drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; | | 1041 | drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; |
1046 | drv_mask2 = __wdcwait_reset(chp, drv_mask1, | | 1042 | drv_mask2 = __wdcwait_reset(chp, drv_mask1, |
1047 | (poll == RESET_SLEEP) ? 0 : 1); | | 1043 | (poll == RESET_SLEEP) ? 0 : 1); |
1048 | if (drv_mask2 != drv_mask1) { | | 1044 | if (drv_mask2 != drv_mask1) { |
1049 | aprint_error("%s channel %d: reset failed for", | | 1045 | aprint_error("%s channel %d: reset failed for", |
1050 | device_xname(atac->atac_dev), chp->ch_channel); | | 1046 | device_xname(atac->atac_dev), chp->ch_channel); |
1051 | if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) | | 1047 | if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) |
1052 | aprint_normal(" drive 0"); | | 1048 | aprint_normal(" drive 0"); |
1053 | if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) | | 1049 | if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) |
1054 | aprint_normal(" drive 1"); | | 1050 | aprint_normal(" drive 1"); |
1055 | aprint_normal("\n"); | | 1051 | aprint_normal("\n"); |
1056 | } | | 1052 | } |
1057 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); | | 1053 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); |
1058 | return (drv_mask1 != drv_mask2) ? 1 : 0; | | 1054 | return (drv_mask1 != drv_mask2) ? 1 : 0; |
1059 | } | | 1055 | } |
1060 | | | 1056 | |
1061 | void | | 1057 | void |
1062 | wdc_do_reset(struct ata_channel *chp, int poll) | | 1058 | wdc_do_reset(struct ata_channel *chp, int poll) |
1063 | { | | 1059 | { |
1064 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1060 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1065 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1061 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1066 | int s = 0; | | 1062 | int s = 0; |
1067 | | | 1063 | |
1068 | if (poll != RESET_SLEEP) | | 1064 | if (poll != RESET_SLEEP) |
1069 | s = splbio(); | | 1065 | s = splbio(); |
1070 | if (wdc->select) | | 1066 | if (wdc->select) |
1071 | wdc->select(chp,0); | | 1067 | wdc->select(chp,0); |
1072 | /* master */ | | 1068 | /* master */ |
1073 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); | | 1069 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); |
1074 | delay(10); /* 400ns delay */ | | 1070 | delay(10); /* 400ns delay */ |
1075 | /* assert SRST, wait for reset to complete */ | | 1071 | /* assert SRST, wait for reset to complete */ |
1076 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, | | 1072 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1077 | WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); | | 1073 | WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); |
1078 | delay(2000); | | 1074 | delay(2000); |
1079 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); | | 1075 | (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); |
1080 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, | | 1076 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1081 | WDCTL_4BIT | WDCTL_IDS); | | 1077 | WDCTL_4BIT | WDCTL_IDS); |
1082 | delay(10); /* 400ns delay */ | | 1078 | delay(10); /* 400ns delay */ |
1083 | if (poll != RESET_SLEEP) { | | 1079 | if (poll != RESET_SLEEP) { |
1084 | /* ACK interrupt in case there is one pending left */ | | 1080 | /* ACK interrupt in case there is one pending left */ |
1085 | if (wdc->irqack) | | 1081 | if (wdc->irqack) |
1086 | wdc->irqack(chp); | | 1082 | wdc->irqack(chp); |
1087 | splx(s); | | 1083 | splx(s); |
1088 | } | | 1084 | } |
1089 | } | | 1085 | } |
1090 | | | 1086 | |
1091 | static int | | 1087 | static int |
1092 | __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) | | 1088 | __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) |
1093 | { | | 1089 | { |
1094 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1090 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1095 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1091 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1096 | int timeout, nloop; | | 1092 | int timeout, nloop; |
1097 | u_int8_t st0 = 0, st1 = 0; | | 1093 | u_int8_t st0 = 0, st1 = 0; |
1098 | #ifdef ATADEBUG | | 1094 | #ifdef ATADEBUG |
1099 | u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; | | 1095 | u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; |
1100 | u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; | | 1096 | u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; |
1101 | #endif | | 1097 | #endif |
1102 | KASSERT(poll == RESET_POLL); | | | |
1103 | if (poll) | | 1098 | if (poll) |
1104 | nloop = WDCNDELAY_RST; | | 1099 | nloop = WDCNDELAY_RST; |
1105 | else | | 1100 | else |
1106 | nloop = WDC_RESET_WAIT * hz / 1000; | | 1101 | nloop = WDC_RESET_WAIT * hz / 1000; |
1107 | /* wait for BSY to deassert */ | | 1102 | /* wait for BSY to deassert */ |
1108 | for (timeout = 0; timeout < nloop; timeout++) { | | 1103 | for (timeout = 0; timeout < nloop; timeout++) { |
1109 | if ((drv_mask & 0x01) != 0) { | | 1104 | if ((drv_mask & 0x01) != 0) { |
1110 | if (wdc->select) | | 1105 | if (wdc->select) |
1111 | wdc->select(chp,0); | | 1106 | wdc->select(chp,0); |
1112 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 1107 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
1113 | 0, WDSD_IBM); /* master */ | | 1108 | 0, WDSD_IBM); /* master */ |
1114 | delay(10); | | 1109 | delay(10); |
1115 | st0 = bus_space_read_1(wdr->cmd_iot, | | 1110 | st0 = bus_space_read_1(wdr->cmd_iot, |
1116 | wdr->cmd_iohs[wd_status], 0); | | 1111 | wdr->cmd_iohs[wd_status], 0); |
1117 | #ifdef ATADEBUG | | 1112 | #ifdef ATADEBUG |
1118 | sc0 = bus_space_read_1(wdr->cmd_iot, | | 1113 | sc0 = bus_space_read_1(wdr->cmd_iot, |
1119 | wdr->cmd_iohs[wd_seccnt], 0); | | 1114 | wdr->cmd_iohs[wd_seccnt], 0); |
1120 | sn0 = bus_space_read_1(wdr->cmd_iot, | | 1115 | sn0 = bus_space_read_1(wdr->cmd_iot, |
1121 | wdr->cmd_iohs[wd_sector], 0); | | 1116 | wdr->cmd_iohs[wd_sector], 0); |
1122 | cl0 = bus_space_read_1(wdr->cmd_iot, | | 1117 | cl0 = bus_space_read_1(wdr->cmd_iot, |
1123 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 1118 | wdr->cmd_iohs[wd_cyl_lo], 0); |
1124 | ch0 = bus_space_read_1(wdr->cmd_iot, | | 1119 | ch0 = bus_space_read_1(wdr->cmd_iot, |
1125 | wdr->cmd_iohs[wd_cyl_hi], 0); | | 1120 | wdr->cmd_iohs[wd_cyl_hi], 0); |
1126 | #endif | | 1121 | #endif |
1127 | } | | 1122 | } |
1128 | if ((drv_mask & 0x02) != 0) { | | 1123 | if ((drv_mask & 0x02) != 0) { |
1129 | if (wdc->select) | | 1124 | if (wdc->select) |
1130 | wdc->select(chp,1); | | 1125 | wdc->select(chp,1); |
1131 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], | | 1126 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], |
1132 | 0, WDSD_IBM | 0x10); /* slave */ | | 1127 | 0, WDSD_IBM | 0x10); /* slave */ |
1133 | delay(10); | | 1128 | delay(10); |
1134 | st1 = bus_space_read_1(wdr->cmd_iot, | | 1129 | st1 = bus_space_read_1(wdr->cmd_iot, |
1135 | wdr->cmd_iohs[wd_status], 0); | | 1130 | wdr->cmd_iohs[wd_status], 0); |
1136 | #ifdef ATADEBUG | | 1131 | #ifdef ATADEBUG |
1137 | sc1 = bus_space_read_1(wdr->cmd_iot, | | 1132 | sc1 = bus_space_read_1(wdr->cmd_iot, |
1138 | wdr->cmd_iohs[wd_seccnt], 0); | | 1133 | wdr->cmd_iohs[wd_seccnt], 0); |
1139 | sn1 = bus_space_read_1(wdr->cmd_iot, | | 1134 | sn1 = bus_space_read_1(wdr->cmd_iot, |
1140 | wdr->cmd_iohs[wd_sector], 0); | | 1135 | wdr->cmd_iohs[wd_sector], 0); |
1141 | cl1 = bus_space_read_1(wdr->cmd_iot, | | 1136 | cl1 = bus_space_read_1(wdr->cmd_iot, |
1142 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 1137 | wdr->cmd_iohs[wd_cyl_lo], 0); |
1143 | ch1 = bus_space_read_1(wdr->cmd_iot, | | 1138 | ch1 = bus_space_read_1(wdr->cmd_iot, |
1144 | wdr->cmd_iohs[wd_cyl_hi], 0); | | 1139 | wdr->cmd_iohs[wd_cyl_hi], 0); |
1145 | #endif | | 1140 | #endif |
1146 | } | | 1141 | } |
1147 | | | 1142 | |
1148 | if ((drv_mask & 0x01) == 0) { | | 1143 | if ((drv_mask & 0x01) == 0) { |
1149 | /* no master */ | | 1144 | /* no master */ |
1150 | if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { | | 1145 | if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { |
1151 | /* No master, slave is ready, it's done */ | | 1146 | /* No master, slave is ready, it's done */ |
1152 | goto end; | | 1147 | goto end; |
1153 | } | | 1148 | } |
1154 | if ((drv_mask & 0x02) == 0) { | | 1149 | if ((drv_mask & 0x02) == 0) { |
1155 | /* No master, no slave: it's done */ | | 1150 | /* No master, no slave: it's done */ |
1156 | goto end; | | 1151 | goto end; |
1157 | } | | 1152 | } |
1158 | } else if ((drv_mask & 0x02) == 0) { | | 1153 | } else if ((drv_mask & 0x02) == 0) { |
1159 | /* no slave */ | | 1154 | /* no slave */ |
1160 | if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { | | 1155 | if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { |
1161 | /* No slave, master is ready, it's done */ | | 1156 | /* No slave, master is ready, it's done */ |
1162 | goto end; | | 1157 | goto end; |
1163 | } | | 1158 | } |
1164 | } else { | | 1159 | } else { |
1165 | /* Wait for both master and slave to be ready */ | | 1160 | /* Wait for both master and slave to be ready */ |
1166 | if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { | | 1161 | if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { |
1167 | goto end; | | 1162 | goto end; |
1168 | } | | 1163 | } |
1169 | } | | 1164 | } |
1170 | if (poll) | | 1165 | if (poll) |
1171 | delay(WDCDELAY); | | 1166 | delay(WDCDELAY); |
1172 | else | | 1167 | else |
1173 | tsleep(&nloop, PRIBIO, "atarst", 1); | | 1168 | tsleep(&nloop, PRIBIO, "atarst", 1); |
1174 | } | | 1169 | } |
1175 | /* Reset timed out. Maybe it's because drv_mask was not right */ | | 1170 | /* Reset timed out. Maybe it's because drv_mask was not right */ |
1176 | if (st0 & WDCS_BSY) | | 1171 | if (st0 & WDCS_BSY) |
1177 | drv_mask &= ~0x01; | | 1172 | drv_mask &= ~0x01; |
1178 | if (st1 & WDCS_BSY) | | 1173 | if (st1 & WDCS_BSY) |
1179 | drv_mask &= ~0x02; | | 1174 | drv_mask &= ~0x02; |
1180 | end: | | 1175 | end: |
1181 | ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " | | 1176 | ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " |
1182 | "cl=0x%x ch=0x%x\n", | | 1177 | "cl=0x%x ch=0x%x\n", |
1183 | device_xname(chp->ch_atac->atac_dev), | | 1178 | device_xname(chp->ch_atac->atac_dev), |
1184 | chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); | | 1179 | chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); |
1185 | ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " | | 1180 | ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " |
1186 | "cl=0x%x ch=0x%x\n", | | 1181 | "cl=0x%x ch=0x%x\n", |
1187 | device_xname(chp->ch_atac->atac_dev), | | 1182 | device_xname(chp->ch_atac->atac_dev), |
1188 | chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); | | 1183 | chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); |
1189 | | | 1184 | |
1190 | ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", | | 1185 | ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", |
1191 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 1186 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1192 | st0, st1), DEBUG_PROBE); | | 1187 | st0, st1), DEBUG_PROBE); |
1193 | | | 1188 | |
1194 | return drv_mask; | | 1189 | return drv_mask; |
1195 | } | | 1190 | } |
1196 | | | 1191 | |
1197 | /* | | 1192 | /* |
1198 | * Wait for a drive to be !BSY, and have mask in its status register. | | 1193 | * Wait for a drive to be !BSY, and have mask in its status register. |
1199 | * return -1 for a timeout after "timeout" ms. | | 1194 | * return -1 for a timeout after "timeout" ms. |
1200 | */ | | 1195 | */ |
1201 | static int | | 1196 | static int |
1202 | __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) | | 1197 | __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) |
1203 | { | | 1198 | { |
1204 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1199 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1205 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1200 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1206 | u_char status; | | 1201 | u_char status; |
1207 | int xtime = 0; | | 1202 | int xtime = 0; |
1208 | | | 1203 | |
1209 | ATADEBUG_PRINT(("__wdcwait %s:%d\n", | | 1204 | ATADEBUG_PRINT(("__wdcwait %s:%d\n", |
1210 | device_xname(chp->ch_atac->atac_dev), | | 1205 | device_xname(chp->ch_atac->atac_dev), |
1211 | chp->ch_channel), DEBUG_STATUS); | | 1206 | chp->ch_channel), DEBUG_STATUS); |
1212 | chp->ch_error = 0; | | 1207 | chp->ch_error = 0; |
1213 | | | 1208 | |
1214 | timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ | | 1209 | timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ |
1215 | | | 1210 | |
1216 | for (;;) { | | 1211 | for (;;) { |
1217 | chp->ch_status = status = | | 1212 | chp->ch_status = status = |
1218 | bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); | | 1213 | bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); |
1219 | if ((status & (WDCS_BSY | mask)) == bits) | | 1214 | if ((status & (WDCS_BSY | mask)) == bits) |
1220 | break; | | 1215 | break; |
1221 | if (++xtime > timeout) { | | 1216 | if (++xtime > timeout) { |
1222 | ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " | | 1217 | ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " |
1223 | "status %x error %x (mask 0x%x bits 0x%x)\n", | | 1218 | "status %x error %x (mask 0x%x bits 0x%x)\n", |
1224 | xtime, status, | | 1219 | xtime, status, |
1225 | bus_space_read_1(wdr->cmd_iot, | | 1220 | bus_space_read_1(wdr->cmd_iot, |
1226 | wdr->cmd_iohs[wd_error], 0), mask, bits), | | 1221 | wdr->cmd_iohs[wd_error], 0), mask, bits), |
1227 | DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); | | 1222 | DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); |
1228 | return(WDCWAIT_TOUT); | | 1223 | return(WDCWAIT_TOUT); |
1229 | } | | 1224 | } |
1230 | delay(WDCDELAY); | | 1225 | delay(WDCDELAY); |
1231 | } | | 1226 | } |
1232 | #ifdef ATADEBUG | | 1227 | #ifdef ATADEBUG |
1233 | if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) | | 1228 | if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) |
1234 | printf("__wdcwait: did busy-wait, time=%d\n", xtime); | | 1229 | printf("__wdcwait: did busy-wait, time=%d\n", xtime); |
1235 | #endif | | 1230 | #endif |
1236 | if (status & WDCS_ERR) | | 1231 | if (status & WDCS_ERR) |
1237 | chp->ch_error = bus_space_read_1(wdr->cmd_iot, | | 1232 | chp->ch_error = bus_space_read_1(wdr->cmd_iot, |
1238 | wdr->cmd_iohs[wd_error], 0); | | 1233 | wdr->cmd_iohs[wd_error], 0); |
1239 | #ifdef WDCNDELAY_DEBUG | | 1234 | #ifdef WDCNDELAY_DEBUG |
1240 | /* After autoconfig, there should be no long delays. */ | | 1235 | /* After autoconfig, there should be no long delays. */ |
1241 | if (!cold && xtime > WDCNDELAY_DEBUG) { | | 1236 | if (!cold && xtime > WDCNDELAY_DEBUG) { |
1242 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; | | 1237 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1243 | if (xfer == NULL) | | 1238 | if (xfer == NULL) |
1244 | printf("%s channel %d: warning: busy-wait took %dus\n", | | 1239 | printf("%s channel %d: warning: busy-wait took %dus\n", |
1245 | device_xname(chp->ch_atac->atac_dev), | | 1240 | device_xname(chp->ch_atac->atac_dev), |
1246 | chp->ch_channel, WDCDELAY * xtime); | | 1241 | chp->ch_channel, WDCDELAY * xtime); |
1247 | else | | 1242 | else |
1248 | printf("%s:%d:%d: warning: busy-wait took %dus\n", | | 1243 | printf("%s:%d:%d: warning: busy-wait took %dus\n", |
1249 | device_xname(chp->ch_atac->atac_dev), | | 1244 | device_xname(chp->ch_atac->atac_dev), |
1250 | chp->ch_channel, xfer->c_drive, | | 1245 | chp->ch_channel, xfer->c_drive, |
1251 | WDCDELAY * xtime); | | 1246 | WDCDELAY * xtime); |
1252 | } | | 1247 | } |
1253 | #endif | | 1248 | #endif |
1254 | return(WDCWAIT_OK); | | 1249 | return(WDCWAIT_OK); |
1255 | } | | 1250 | } |
1256 | | | 1251 | |
1257 | /* | | 1252 | /* |
1258 | * Call __wdcwait(), polling using tsleep() or waking up the kernel | | 1253 | * Call __wdcwait(), polling using tsleep() or waking up the kernel |
1259 | * thread if possible | | 1254 | * thread if possible |
1260 | */ | | 1255 | */ |
1261 | int | | 1256 | int |
1262 | wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) | | 1257 | wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) |
1263 | { | | 1258 | { |
1264 | int error, i, timeout_hz = mstohz(timeout); | | 1259 | int error, i, timeout_hz = mstohz(timeout); |
1265 | | | 1260 | |
1266 | if (timeout_hz == 0 || | | 1261 | if (timeout_hz == 0 || |
1267 | (flags & (AT_WAIT | AT_POLL)) == AT_POLL) | | 1262 | (flags & (AT_WAIT | AT_POLL)) == AT_POLL) |
1268 | error = __wdcwait(chp, mask, bits, timeout); | | 1263 | error = __wdcwait(chp, mask, bits, timeout); |
1269 | else { | | 1264 | else { |
1270 | error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); | | 1265 | error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); |
1271 | if (error != 0) { | | 1266 | if (error != 0) { |
1272 | if ((chp->ch_flags & ATACH_TH_RUN) || | | 1267 | if ((chp->ch_flags & ATACH_TH_RUN) || |
1273 | (flags & AT_WAIT)) { | | 1268 | (flags & AT_WAIT)) { |
1274 | /* | | 1269 | /* |
1275 | * we're running in the channel thread | | 1270 | * we're running in the channel thread |
1276 | * or some userland thread context | | 1271 | * or some userland thread context |
1277 | */ | | 1272 | */ |
1278 | for (i = 0; i < timeout_hz; i++) { | | 1273 | for (i = 0; i < timeout_hz; i++) { |
1279 | if (__wdcwait(chp, mask, bits, | | 1274 | if (__wdcwait(chp, mask, bits, |
1280 | WDCDELAY_POLL) == 0) { | | 1275 | WDCDELAY_POLL) == 0) { |
1281 | error = 0; | | 1276 | error = 0; |
1282 | break; | | 1277 | break; |
1283 | } | | 1278 | } |
1284 | tsleep(&chp, PRIBIO, "atapoll", 1); | | 1279 | tsleep(&chp, PRIBIO, "atapoll", 1); |
1285 | } | | 1280 | } |
1286 | } else { | | 1281 | } else { |
1287 | /* | | 1282 | /* |
1288 | * we're probably in interrupt context, | | 1283 | * we're probably in interrupt context, |
1289 | * ask the thread to come back here | | 1284 | * ask the thread to come back here |
1290 | */ | | 1285 | */ |
1291 | #ifdef DIAGNOSTIC | | 1286 | #ifdef DIAGNOSTIC |
1292 | if (chp->ch_queue->queue_freeze > 0) | | 1287 | if (chp->ch_queue->queue_freeze > 0) |
1293 | panic("wdcwait: queue_freeze"); | | 1288 | panic("wdcwait: queue_freeze"); |
1294 | #endif | | 1289 | #endif |
1295 | chp->ch_queue->queue_freeze++; | | 1290 | chp->ch_queue->queue_freeze++; |
1296 | wakeup(&chp->ch_thread); | | 1291 | wakeup(&chp->ch_thread); |
1297 | return(WDCWAIT_THR); | | 1292 | return(WDCWAIT_THR); |
1298 | } | | 1293 | } |
1299 | } | | 1294 | } |
1300 | } | | 1295 | } |
1301 | return (error); | | 1296 | return (error); |
1302 | } | | 1297 | } |
1303 | | | 1298 | |
1304 | | | 1299 | |
1305 | #if NATA_DMA | | 1300 | #if NATA_DMA |
1306 | /* | | 1301 | /* |
1307 | * Busy-wait for DMA to complete | | 1302 | * Busy-wait for DMA to complete |
1308 | */ | | 1303 | */ |
1309 | int | | 1304 | int |
1310 | wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) | | 1305 | wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) |
1311 | { | | 1306 | { |
1312 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1307 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1313 | int xtime; | | 1308 | int xtime; |
1314 | | | 1309 | |
1315 | for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { | | 1310 | for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { |
1316 | wdc->dma_status = | | 1311 | wdc->dma_status = |
1317 | (*wdc->dma_finish)(wdc->dma_arg, | | 1312 | (*wdc->dma_finish)(wdc->dma_arg, |
1318 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); | | 1313 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); |
1319 | if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) | | 1314 | if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) |
1320 | return 0; | | 1315 | return 0; |
1321 | delay(WDCDELAY); | | 1316 | delay(WDCDELAY); |
1322 | } | | 1317 | } |
1323 | /* timeout, force a DMA halt */ | | 1318 | /* timeout, force a DMA halt */ |
1324 | wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, | | 1319 | wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, |
1325 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); | | 1320 | chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); |
1326 | return 1; | | 1321 | return 1; |
1327 | } | | 1322 | } |
1328 | #endif | | 1323 | #endif |
1329 | | | 1324 | |
1330 | void | | 1325 | void |
1331 | wdctimeout(void *arg) | | 1326 | wdctimeout(void *arg) |
1332 | { | | 1327 | { |
1333 | struct ata_channel *chp = (struct ata_channel *)arg; | | 1328 | struct ata_channel *chp = (struct ata_channel *)arg; |
1334 | #if NATA_DMA || NATA_PIOBM | | 1329 | #if NATA_DMA || NATA_PIOBM |
1335 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1330 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1336 | #endif | | 1331 | #endif |
1337 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; | | 1332 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1338 | int s; | | 1333 | int s; |
1339 | | | 1334 | |
1340 | ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); | | 1335 | ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); |
1341 | | | 1336 | |
1342 | s = splbio(); | | 1337 | s = splbio(); |
1343 | if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { | | 1338 | if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { |
1344 | __wdcerror(chp, "lost interrupt"); | | 1339 | __wdcerror(chp, "lost interrupt"); |
1345 | printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", | | 1340 | printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", |
1346 | (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", | | 1341 | (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", |
1347 | xfer->c_bcount, | | 1342 | xfer->c_bcount, |
1348 | xfer->c_skip); | | 1343 | xfer->c_skip); |
1349 | #if NATA_DMA || NATA_PIOBM | | 1344 | #if NATA_DMA || NATA_PIOBM |
1350 | if (chp->ch_flags & ATACH_DMA_WAIT) { | | 1345 | if (chp->ch_flags & ATACH_DMA_WAIT) { |
1351 | wdc->dma_status = | | 1346 | wdc->dma_status = |
1352 | (*wdc->dma_finish)(wdc->dma_arg, | | 1347 | (*wdc->dma_finish)(wdc->dma_arg, |
1353 | chp->ch_channel, xfer->c_drive, | | 1348 | chp->ch_channel, xfer->c_drive, |
1354 | WDC_DMAEND_ABRT); | | 1349 | WDC_DMAEND_ABRT); |
1355 | chp->ch_flags &= ~ATACH_DMA_WAIT; | | 1350 | chp->ch_flags &= ~ATACH_DMA_WAIT; |
1356 | } | | 1351 | } |
1357 | #endif | | 1352 | #endif |
1358 | /* | | 1353 | /* |
1359 | * Call the interrupt routine. If we just missed an interrupt, | | 1354 | * Call the interrupt routine. If we just missed an interrupt, |
1360 | * it will do what's needed. Else, it will take the needed | | 1355 | * it will do what's needed. Else, it will take the needed |
1361 | * action (reset the device). | | 1356 | * action (reset the device). |
1362 | * Before that we need to reinstall the timeout callback, | | 1357 | * Before that we need to reinstall the timeout callback, |
1363 | * in case it will miss another irq while in this transfer | | 1358 | * in case it will miss another irq while in this transfer |
1364 | * We arbitray chose it to be 1s | | 1359 | * We arbitray chose it to be 1s |
1365 | */ | | 1360 | */ |
1366 | callout_reset(&chp->ch_callout, hz, wdctimeout, chp); | | 1361 | callout_reset(&chp->ch_callout, hz, wdctimeout, chp); |
1367 | xfer->c_flags |= C_TIMEOU; | | 1362 | xfer->c_flags |= C_TIMEOU; |
1368 | chp->ch_flags &= ~ATACH_IRQ_WAIT; | | 1363 | chp->ch_flags &= ~ATACH_IRQ_WAIT; |
1369 | KASSERT(xfer->c_intr != NULL); | | 1364 | KASSERT(xfer->c_intr != NULL); |
1370 | xfer->c_intr(chp, xfer, 1); | | 1365 | xfer->c_intr(chp, xfer, 1); |
1371 | } else | | 1366 | } else |
1372 | __wdcerror(chp, "missing untimeout"); | | 1367 | __wdcerror(chp, "missing untimeout"); |
1373 | splx(s); | | 1368 | splx(s); |
1374 | } | | 1369 | } |
1375 | | | 1370 | |
1376 | int | | 1371 | int |
1377 | wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) | | 1372 | wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) |
1378 | { | | 1373 | { |
1379 | struct ata_channel *chp = drvp->chnl_softc; | | 1374 | struct ata_channel *chp = drvp->chnl_softc; |
1380 | struct ata_xfer *xfer; | | 1375 | struct ata_xfer *xfer; |
1381 | int s, ret; | | 1376 | int s, ret; |
1382 | | | 1377 | |
1383 | ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", | | 1378 | ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", |
1384 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 1379 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1385 | drvp->drive), DEBUG_FUNCS); | | 1380 | drvp->drive), DEBUG_FUNCS); |
1386 | | | 1381 | |
1387 | /* set up an xfer and queue. Wait for completion */ | | 1382 | /* set up an xfer and queue. Wait for completion */ |
1388 | xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : | | 1383 | xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : |
1389 | ATAXF_NOSLEEP); | | 1384 | ATAXF_NOSLEEP); |
1390 | if (xfer == NULL) { | | 1385 | if (xfer == NULL) { |
1391 | return ATACMD_TRY_AGAIN; | | 1386 | return ATACMD_TRY_AGAIN; |
1392 | } | | 1387 | } |
1393 | | | 1388 | |
1394 | if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) | | 1389 | if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) |
1395 | ata_c->flags |= AT_POLL; | | 1390 | ata_c->flags |= AT_POLL; |
1396 | if (ata_c->flags & AT_POLL) | | 1391 | if (ata_c->flags & AT_POLL) |
1397 | xfer->c_flags |= C_POLL; | | 1392 | xfer->c_flags |= C_POLL; |
1398 | if (ata_c->flags & AT_WAIT) | | 1393 | if (ata_c->flags & AT_WAIT) |
1399 | xfer->c_flags |= C_WAIT; | | 1394 | xfer->c_flags |= C_WAIT; |
1400 | xfer->c_drive = drvp->drive; | | 1395 | xfer->c_drive = drvp->drive; |
1401 | xfer->c_databuf = ata_c->data; | | 1396 | xfer->c_databuf = ata_c->data; |
1402 | xfer->c_bcount = ata_c->bcount; | | 1397 | xfer->c_bcount = ata_c->bcount; |
1403 | xfer->c_cmd = ata_c; | | 1398 | xfer->c_cmd = ata_c; |
1404 | xfer->c_start = __wdccommand_start; | | 1399 | xfer->c_start = __wdccommand_start; |
1405 | xfer->c_intr = __wdccommand_intr; | | 1400 | xfer->c_intr = __wdccommand_intr; |
1406 | xfer->c_kill_xfer = __wdccommand_kill_xfer; | | 1401 | xfer->c_kill_xfer = __wdccommand_kill_xfer; |
1407 | | | 1402 | |
1408 | s = splbio(); | | 1403 | s = splbio(); |
1409 | ata_exec_xfer(chp, xfer); | | 1404 | ata_exec_xfer(chp, xfer); |
1410 | #ifdef DIAGNOSTIC | | 1405 | #ifdef DIAGNOSTIC |
1411 | if ((ata_c->flags & AT_POLL) != 0 && | | 1406 | if ((ata_c->flags & AT_POLL) != 0 && |
1412 | (ata_c->flags & AT_DONE) == 0) | | 1407 | (ata_c->flags & AT_DONE) == 0) |
1413 | panic("wdc_exec_command: polled command not done"); | | 1408 | panic("wdc_exec_command: polled command not done"); |
1414 | #endif | | 1409 | #endif |
1415 | if (ata_c->flags & AT_DONE) { | | 1410 | if (ata_c->flags & AT_DONE) { |
1416 | ret = ATACMD_COMPLETE; | | 1411 | ret = ATACMD_COMPLETE; |
1417 | } else { | | 1412 | } else { |
1418 | if (ata_c->flags & AT_WAIT) { | | 1413 | if (ata_c->flags & AT_WAIT) { |
1419 | while ((ata_c->flags & AT_DONE) == 0) { | | 1414 | while ((ata_c->flags & AT_DONE) == 0) { |
1420 | tsleep(ata_c, PRIBIO, "wdccmd", 0); | | 1415 | tsleep(ata_c, PRIBIO, "wdccmd", 0); |
1421 | } | | 1416 | } |
1422 | ret = ATACMD_COMPLETE; | | 1417 | ret = ATACMD_COMPLETE; |
1423 | } else { | | 1418 | } else { |
1424 | ret = ATACMD_QUEUED; | | 1419 | ret = ATACMD_QUEUED; |
1425 | } | | 1420 | } |
1426 | } | | 1421 | } |
1427 | splx(s); | | 1422 | splx(s); |
1428 | return ret; | | 1423 | return ret; |
1429 | } | | 1424 | } |
1430 | | | 1425 | |
1431 | static void | | 1426 | static void |
1432 | __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) | | 1427 | __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) |
1433 | { | | 1428 | { |
1434 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1429 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1435 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1430 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1436 | int drive = xfer->c_drive; | | 1431 | int drive = xfer->c_drive; |
1437 | int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; | | 1432 | int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; |
1438 | struct ata_command *ata_c = xfer->c_cmd; | | 1433 | struct ata_command *ata_c = xfer->c_cmd; |
1439 | | | 1434 | |
1440 | ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", | | 1435 | ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", |
1441 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 1436 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1442 | xfer->c_drive), | | 1437 | xfer->c_drive), |
1443 | DEBUG_FUNCS); | | 1438 | DEBUG_FUNCS); |
1444 | | | 1439 | |
1445 | if (wdc->select) | | 1440 | if (wdc->select) |
1446 | wdc->select(chp,drive); | | 1441 | wdc->select(chp,drive); |
1447 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 1442 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1448 | WDSD_IBM | (drive << 4)); | | 1443 | WDSD_IBM | (drive << 4)); |
1449 | switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, | | 1444 | switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, |
1450 | ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { | | 1445 | ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { |
1451 | case WDCWAIT_OK: | | 1446 | case WDCWAIT_OK: |
1452 | break; | | 1447 | break; |
1453 | case WDCWAIT_TOUT: | | 1448 | case WDCWAIT_TOUT: |
1454 | ata_c->flags |= AT_TIMEOU; | | 1449 | ata_c->flags |= AT_TIMEOU; |
1455 | __wdccommand_done(chp, xfer); | | 1450 | __wdccommand_done(chp, xfer); |
1456 | return; | | 1451 | return; |
1457 | case WDCWAIT_THR: | | 1452 | case WDCWAIT_THR: |
1458 | return; | | 1453 | return; |
1459 | } | | 1454 | } |
1460 | if (ata_c->flags & AT_POLL) { | | 1455 | if (ata_c->flags & AT_POLL) { |
1461 | /* polled command, disable interrupts */ | | 1456 | /* polled command, disable interrupts */ |
1462 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, | | 1457 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1463 | WDCTL_4BIT | WDCTL_IDS); | | 1458 | WDCTL_4BIT | WDCTL_IDS); |
1464 | } | | 1459 | } |
1465 | wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, | | 1460 | wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, |
1466 | ata_c->r_sector, ata_c->r_count, ata_c->r_features); | | 1461 | ata_c->r_sector, ata_c->r_count, ata_c->r_features); |
1467 | | | 1462 | |
1468 | if ((ata_c->flags & AT_POLL) == 0) { | | 1463 | if ((ata_c->flags & AT_POLL) == 0) { |
1469 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ | | 1464 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
1470 | callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, | | 1465 | callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, |
1471 | wdctimeout, chp); | | 1466 | wdctimeout, chp); |
1472 | return; | | 1467 | return; |
1473 | } | | 1468 | } |
1474 | /* | | 1469 | /* |
1475 | * Polled command. Wait for drive ready or drq. Done in intr(). | | 1470 | * Polled command. Wait for drive ready or drq. Done in intr(). |
1476 | * Wait for at last 400ns for status bit to be valid. | | 1471 | * Wait for at last 400ns for status bit to be valid. |
1477 | */ | | 1472 | */ |
1478 | delay(10); /* 400ns delay */ | | 1473 | delay(10); /* 400ns delay */ |
1479 | __wdccommand_intr(chp, xfer, 0); | | 1474 | __wdccommand_intr(chp, xfer, 0); |
1480 | } | | 1475 | } |
1481 | | | 1476 | |
1482 | static int | | 1477 | static int |
1483 | __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) | | 1478 | __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) |
1484 | { | | 1479 | { |
1485 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1480 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1486 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1481 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1487 | struct ata_command *ata_c = xfer->c_cmd; | | 1482 | struct ata_command *ata_c = xfer->c_cmd; |
1488 | int bcount = ata_c->bcount; | | 1483 | int bcount = ata_c->bcount; |
1489 | char *data = ata_c->data; | | 1484 | char *data = ata_c->data; |
1490 | int wflags; | | 1485 | int wflags; |
1491 | int drive_flags; | | 1486 | int drive_flags; |
1492 | | | 1487 | |
1493 | if (ata_c->r_command == WDCC_IDENTIFY || | | 1488 | if (ata_c->r_command == WDCC_IDENTIFY || |
1494 | ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { | | 1489 | ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { |
1495 | /* | | 1490 | /* |
1496 | * The IDENTIFY data has been designed as an array of | | 1491 | * The IDENTIFY data has been designed as an array of |
1497 | * u_int16_t, so we can byteswap it on the fly. | | 1492 | * u_int16_t, so we can byteswap it on the fly. |
1498 | * Historically it's what we have always done so keeping it | | 1493 | * Historically it's what we have always done so keeping it |
1499 | * here ensure binary backward compatibility. | | 1494 | * here ensure binary backward compatibility. |
1500 | */ | | 1495 | */ |
1501 | drive_flags = DRIVE_NOSTREAM | | | 1496 | drive_flags = DRIVE_NOSTREAM | |
1502 | chp->ch_drive[xfer->c_drive].drive_flags; | | 1497 | chp->ch_drive[xfer->c_drive].drive_flags; |
1503 | } else { | | 1498 | } else { |
1504 | /* | | 1499 | /* |
1505 | * Other data structure are opaque and should be transfered | | 1500 | * Other data structure are opaque and should be transfered |
1506 | * as is. | | 1501 | * as is. |
1507 | */ | | 1502 | */ |
1508 | drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; | | 1503 | drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; |
1509 | } | | 1504 | } |
1510 | | | 1505 | |
1511 | #ifndef WDC_NO_IDS | | 1506 | #ifdef WDC_NO_IDS |
| | | 1507 | wflags = AT_POLL; |
| | | 1508 | #else |
1512 | if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { | | 1509 | if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { |
1513 | /* both wait and poll, we can tsleep here */ | | 1510 | /* both wait and poll, we can tsleep here */ |
1514 | wflags = AT_WAIT | AT_POLL; | | 1511 | wflags = AT_WAIT | AT_POLL; |
1515 | } else | | 1512 | } else { |
1516 | #endif | | | |
1517 | wflags = AT_POLL; | | 1513 | wflags = AT_POLL; |
| | | 1514 | } |
| | | 1515 | #endif |
1518 | | | 1516 | |
1519 | again: | | 1517 | again: |
1520 | ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", | | 1518 | ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", |
1521 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, | | 1519 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, |
1522 | xfer->c_drive), DEBUG_INTR); | | 1520 | xfer->c_drive), DEBUG_INTR); |
1523 | /* | | 1521 | /* |
1524 | * after a ATAPI_SOFT_RESET, the device will have released the bus. | | 1522 | * after a ATAPI_SOFT_RESET, the device will have released the bus. |
1525 | * Reselect again, it doesn't hurt for others commands, and the time | | 1523 | * Reselect again, it doesn't hurt for others commands, and the time |
1526 | * penalty for the extra regiter write is acceptable, | | 1524 | * penalty for the extra regiter write is acceptable, |
1527 | * wdc_exec_command() isn't called often (mosly for autoconfig) | | 1525 | * wdc_exec_command() isn't called often (mosly for autoconfig) |
1528 | */ | | 1526 | */ |
1529 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 1527 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1530 | WDSD_IBM | (xfer->c_drive << 4)); | | 1528 | WDSD_IBM | (xfer->c_drive << 4)); |
1531 | if ((ata_c->flags & AT_XFDONE) != 0) { | | 1529 | if ((ata_c->flags & AT_XFDONE) != 0) { |
1532 | /* | | 1530 | /* |
1533 | * We have completed a data xfer. The drive should now be | | 1531 | * We have completed a data xfer. The drive should now be |
1534 | * in its initial state | | 1532 | * in its initial state |
1535 | */ | | 1533 | */ |
1536 | if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, | | 1534 | if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, |
1537 | ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, | | 1535 | ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, |
1538 | wflags) == WDCWAIT_TOUT) { | | 1536 | wflags) == WDCWAIT_TOUT) { |
1539 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) | | 1537 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) |
1540 | return 0; /* IRQ was not for us */ | | 1538 | return 0; /* IRQ was not for us */ |
1541 | ata_c->flags |= AT_TIMEOU; | | 1539 | ata_c->flags |= AT_TIMEOU; |
1542 | } | | 1540 | } |
1543 | goto out; | | 1541 | goto out; |
1544 | } | | 1542 | } |
1545 | if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, | | 1543 | if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, |
1546 | (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { | | 1544 | (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { |
1547 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) | | 1545 | if (irq && (xfer->c_flags & C_TIMEOU) == 0) |
1548 | return 0; /* IRQ was not for us */ | | 1546 | return 0; /* IRQ was not for us */ |
1549 | ata_c->flags |= AT_TIMEOU; | | 1547 | ata_c->flags |= AT_TIMEOU; |
1550 | goto out; | | 1548 | goto out; |
1551 | } | | 1549 | } |
1552 | if (wdc->irqack) | | 1550 | if (wdc->irqack) |
1553 | wdc->irqack(chp); | | 1551 | wdc->irqack(chp); |
1554 | if (ata_c->flags & AT_READ) { | | 1552 | if (ata_c->flags & AT_READ) { |
1555 | if ((chp->ch_status & WDCS_DRQ) == 0) { | | 1553 | if ((chp->ch_status & WDCS_DRQ) == 0) { |
1556 | ata_c->flags |= AT_TIMEOU; | | 1554 | ata_c->flags |= AT_TIMEOU; |
1557 | goto out; | | 1555 | goto out; |
1558 | } | | 1556 | } |
1559 | wdc->datain_pio(chp, drive_flags, data, bcount); | | 1557 | wdc->datain_pio(chp, drive_flags, data, bcount); |
1560 | /* at this point the drive should be in its initial state */ | | 1558 | /* at this point the drive should be in its initial state */ |
1561 | ata_c->flags |= AT_XFDONE; | | 1559 | ata_c->flags |= AT_XFDONE; |
1562 | /* | | 1560 | /* |
1563 | * XXX checking the status register again here cause some | | 1561 | * XXX checking the status register again here cause some |
1564 | * hardware to timeout. | | 1562 | * hardware to timeout. |
1565 | */ | | 1563 | */ |
1566 | } else if (ata_c->flags & AT_WRITE) { | | 1564 | } else if (ata_c->flags & AT_WRITE) { |
1567 | if ((chp->ch_status & WDCS_DRQ) == 0) { | | 1565 | if ((chp->ch_status & WDCS_DRQ) == 0) { |
1568 | ata_c->flags |= AT_TIMEOU; | | 1566 | ata_c->flags |= AT_TIMEOU; |
1569 | goto out; | | 1567 | goto out; |
1570 | } | | 1568 | } |
1571 | wdc->dataout_pio(chp, drive_flags, data, bcount); | | 1569 | wdc->dataout_pio(chp, drive_flags, data, bcount); |
1572 | ata_c->flags |= AT_XFDONE; | | 1570 | ata_c->flags |= AT_XFDONE; |
1573 | if ((ata_c->flags & AT_POLL) == 0) { | | 1571 | if ((ata_c->flags & AT_POLL) == 0) { |
1574 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ | | 1572 | chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ |
1575 | callout_reset(&chp->ch_callout, | | 1573 | callout_reset(&chp->ch_callout, |
1576 | mstohz(ata_c->timeout), wdctimeout, chp); | | 1574 | mstohz(ata_c->timeout), wdctimeout, chp); |
1577 | return 1; | | 1575 | return 1; |
1578 | } else { | | 1576 | } else { |
1579 | goto again; | | 1577 | goto again; |
1580 | } | | 1578 | } |
1581 | } | | 1579 | } |
1582 | out: | | 1580 | out: |
1583 | __wdccommand_done(chp, xfer); | | 1581 | __wdccommand_done(chp, xfer); |
1584 | return 1; | | 1582 | return 1; |
1585 | } | | 1583 | } |
1586 | | | 1584 | |
1587 | static void | | 1585 | static void |
1588 | __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) | | 1586 | __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) |
1589 | { | | 1587 | { |
1590 | struct atac_softc *atac = chp->ch_atac; | | 1588 | struct atac_softc *atac = chp->ch_atac; |
1591 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1589 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1592 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1590 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1593 | struct ata_command *ata_c = xfer->c_cmd; | | 1591 | struct ata_command *ata_c = xfer->c_cmd; |
1594 | | | 1592 | |
1595 | ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", | | 1593 | ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", |
1596 | device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, | | 1594 | device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, |
1597 | ata_c->flags), DEBUG_FUNCS); | | 1595 | ata_c->flags), DEBUG_FUNCS); |
1598 | | | 1596 | |
1599 | | | 1597 | |
1600 | if (chp->ch_status & WDCS_DWF) | | 1598 | if (chp->ch_status & WDCS_DWF) |
1601 | ata_c->flags |= AT_DF; | | 1599 | ata_c->flags |= AT_DF; |
1602 | if (chp->ch_status & WDCS_ERR) { | | 1600 | if (chp->ch_status & WDCS_ERR) { |
1603 | ata_c->flags |= AT_ERROR; | | 1601 | ata_c->flags |= AT_ERROR; |
1604 | ata_c->r_error = chp->ch_error; | | 1602 | ata_c->r_error = chp->ch_error; |
1605 | } | | 1603 | } |
1606 | if ((ata_c->flags & AT_READREG) != 0 && | | 1604 | if ((ata_c->flags & AT_READREG) != 0 && |
1607 | device_is_active(atac->atac_dev) && | | 1605 | device_is_active(atac->atac_dev) && |
1608 | (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { | | 1606 | (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { |
1609 | ata_c->r_head = bus_space_read_1(wdr->cmd_iot, | | 1607 | ata_c->r_head = bus_space_read_1(wdr->cmd_iot, |
1610 | wdr->cmd_iohs[wd_sdh], 0); | | 1608 | wdr->cmd_iohs[wd_sdh], 0); |
1611 | ata_c->r_count = bus_space_read_1(wdr->cmd_iot, | | 1609 | ata_c->r_count = bus_space_read_1(wdr->cmd_iot, |
1612 | wdr->cmd_iohs[wd_seccnt], 0); | | 1610 | wdr->cmd_iohs[wd_seccnt], 0); |
1613 | ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, | | 1611 | ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, |
1614 | wdr->cmd_iohs[wd_sector], 0); | | 1612 | wdr->cmd_iohs[wd_sector], 0); |
1615 | ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, | | 1613 | ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, |
1616 | wdr->cmd_iohs[wd_cyl_hi], 0) << 8; | | 1614 | wdr->cmd_iohs[wd_cyl_hi], 0) << 8; |
1617 | ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, | | 1615 | ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, |
1618 | wdr->cmd_iohs[wd_cyl_lo], 0); | | 1616 | wdr->cmd_iohs[wd_cyl_lo], 0); |
1619 | ata_c->r_error = bus_space_read_1(wdr->cmd_iot, | | 1617 | ata_c->r_error = bus_space_read_1(wdr->cmd_iot, |
1620 | wdr->cmd_iohs[wd_error], 0); | | 1618 | wdr->cmd_iohs[wd_error], 0); |
1621 | ata_c->r_features = bus_space_read_1(wdr->cmd_iot, | | 1619 | ata_c->r_features = bus_space_read_1(wdr->cmd_iot, |
1622 | wdr->cmd_iohs[wd_features], 0); | | 1620 | wdr->cmd_iohs[wd_features], 0); |
1623 | } | | 1621 | } |
1624 | callout_stop(&chp->ch_callout); | | 1622 | callout_stop(&chp->ch_callout); |
1625 | chp->ch_queue->active_xfer = NULL; | | 1623 | chp->ch_queue->active_xfer = NULL; |
1626 | if (ata_c->flags & AT_POLL) { | | 1624 | if (ata_c->flags & AT_POLL) { |
1627 | /* enable interrupts */ | | 1625 | /* enable interrupts */ |
1628 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, | | 1626 | bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, |
1629 | WDCTL_4BIT); | | 1627 | WDCTL_4BIT); |
1630 | delay(10); /* some drives need a little delay here */ | | 1628 | delay(10); /* some drives need a little delay here */ |
1631 | } | | 1629 | } |
1632 | if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { | | 1630 | if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { |
1633 | __wdccommand_kill_xfer(chp, xfer, KILL_GONE); | | 1631 | __wdccommand_kill_xfer(chp, xfer, KILL_GONE); |
1634 | chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; | | 1632 | chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; |
1635 | wakeup(&chp->ch_queue->active_xfer); | | 1633 | wakeup(&chp->ch_queue->active_xfer); |
1636 | } else | | 1634 | } else |
1637 | __wdccommand_done_end(chp, xfer); | | 1635 | __wdccommand_done_end(chp, xfer); |
1638 | } | | 1636 | } |
1639 | | | 1637 | |
1640 | static void | | 1638 | static void |
1641 | __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) | | 1639 | __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) |
1642 | { | | 1640 | { |
1643 | struct ata_command *ata_c = xfer->c_cmd; | | 1641 | struct ata_command *ata_c = xfer->c_cmd; |
1644 | | | 1642 | |
1645 | ata_c->flags |= AT_DONE; | | 1643 | ata_c->flags |= AT_DONE; |
1646 | ata_free_xfer(chp, xfer); | | 1644 | ata_free_xfer(chp, xfer); |
1647 | if (ata_c->flags & AT_WAIT) | | 1645 | if (ata_c->flags & AT_WAIT) |
1648 | wakeup(ata_c); | | 1646 | wakeup(ata_c); |
1649 | else if (ata_c->callback) | | 1647 | else if (ata_c->callback) |
1650 | ata_c->callback(ata_c->callback_arg); | | 1648 | ata_c->callback(ata_c->callback_arg); |
1651 | atastart(chp); | | 1649 | atastart(chp); |
1652 | return; | | 1650 | return; |
1653 | } | | 1651 | } |
1654 | | | 1652 | |
1655 | static void | | 1653 | static void |
1656 | __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, | | 1654 | __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, |
1657 | int reason) | | 1655 | int reason) |
1658 | { | | 1656 | { |
1659 | struct ata_command *ata_c = xfer->c_cmd; | | 1657 | struct ata_command *ata_c = xfer->c_cmd; |
1660 | | | 1658 | |
1661 | switch (reason) { | | 1659 | switch (reason) { |
1662 | case KILL_GONE: | | 1660 | case KILL_GONE: |
1663 | ata_c->flags |= AT_GONE; | | 1661 | ata_c->flags |= AT_GONE; |
1664 | break; | | 1662 | break; |
1665 | case KILL_RESET: | | 1663 | case KILL_RESET: |
1666 | ata_c->flags |= AT_RESET; | | 1664 | ata_c->flags |= AT_RESET; |
1667 | break; | | 1665 | break; |
1668 | default: | | 1666 | default: |
1669 | printf("__wdccommand_kill_xfer: unknown reason %d\n", | | 1667 | printf("__wdccommand_kill_xfer: unknown reason %d\n", |
1670 | reason); | | 1668 | reason); |
1671 | panic("__wdccommand_kill_xfer"); | | 1669 | panic("__wdccommand_kill_xfer"); |
1672 | } | | 1670 | } |
1673 | __wdccommand_done_end(chp, xfer); | | 1671 | __wdccommand_done_end(chp, xfer); |
1674 | } | | 1672 | } |
1675 | | | 1673 | |
1676 | /* | | 1674 | /* |
1677 | * Send a command. The drive should be ready. | | 1675 | * Send a command. The drive should be ready. |
1678 | * Assumes interrupts are blocked. | | 1676 | * Assumes interrupts are blocked. |
1679 | */ | | 1677 | */ |
1680 | void | | 1678 | void |
1681 | wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, | | 1679 | wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, |
1682 | u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, | | 1680 | u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, |
1683 | u_int8_t features) | | 1681 | u_int8_t features) |
1684 | { | | 1682 | { |
1685 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1683 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1686 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1684 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1687 | | | 1685 | |
1688 | ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " | | 1686 | ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " |
1689 | "sector=%d count=%d features=%d\n", | | 1687 | "sector=%d count=%d features=%d\n", |
1690 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, | | 1688 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, |
1691 | command, cylin, head, sector, count, features), DEBUG_FUNCS); | | 1689 | command, cylin, head, sector, count, features), DEBUG_FUNCS); |
1692 | | | 1690 | |
1693 | if (wdc->select) | | 1691 | if (wdc->select) |
1694 | wdc->select(chp,drive); | | 1692 | wdc->select(chp,drive); |
1695 | | | 1693 | |
1696 | /* Select drive, head, and addressing mode. */ | | 1694 | /* Select drive, head, and addressing mode. */ |
1697 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 1695 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1698 | WDSD_IBM | (drive << 4) | head); | | 1696 | WDSD_IBM | (drive << 4) | head); |
1699 | /* Load parameters into the wd_features register. */ | | 1697 | /* Load parameters into the wd_features register. */ |
1700 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, | | 1698 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, |
1701 | features); | | 1699 | features); |
1702 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); | | 1700 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); |
1703 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); | | 1701 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); |
1704 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); | | 1702 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); |
1705 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], | | 1703 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], |
1706 | 0, cylin >> 8); | | 1704 | 0, cylin >> 8); |
1707 | | | 1705 | |
1708 | /* Send command. */ | | 1706 | /* Send command. */ |
1709 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); | | 1707 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1710 | return; | | 1708 | return; |
1711 | } | | 1709 | } |
1712 | | | 1710 | |
1713 | /* | | 1711 | /* |
1714 | * Send a 48-bit addressing command. The drive should be ready. | | 1712 | * Send a 48-bit addressing command. The drive should be ready. |
1715 | * Assumes interrupts are blocked. | | 1713 | * Assumes interrupts are blocked. |
1716 | */ | | 1714 | */ |
1717 | void | | 1715 | void |
1718 | wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, | | 1716 | wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, |
1719 | u_int64_t blkno, u_int16_t count) | | 1717 | u_int64_t blkno, u_int16_t count) |
1720 | { | | 1718 | { |
1721 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1719 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1722 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1720 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1723 | | | 1721 | |
1724 | ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " | | 1722 | ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " |
1725 | "count=%d\n", device_xname(chp->ch_atac->atac_dev), | | 1723 | "count=%d\n", device_xname(chp->ch_atac->atac_dev), |
1726 | chp->ch_channel, drive, command, (u_int32_t) blkno, count), | | 1724 | chp->ch_channel, drive, command, (u_int32_t) blkno, count), |
1727 | DEBUG_FUNCS); | | 1725 | DEBUG_FUNCS); |
1728 | | | 1726 | |
1729 | if (wdc->select) | | 1727 | if (wdc->select) |
1730 | wdc->select(chp,drive); | | 1728 | wdc->select(chp,drive); |
1731 | | | 1729 | |
1732 | /* Select drive, head, and addressing mode. */ | | 1730 | /* Select drive, head, and addressing mode. */ |
1733 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 1731 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1734 | (drive << 4) | WDSD_LBA); | | 1732 | (drive << 4) | WDSD_LBA); |
1735 | | | 1733 | |
1736 | if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { | | 1734 | if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { |
1737 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, | | 1735 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, |
1738 | 0); | | 1736 | 0); |
1739 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], | | 1737 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], |
1740 | 0, count); | | 1738 | 0, count); |
1741 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], | | 1739 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], |
1742 | 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); | | 1740 | 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); |
1743 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], | | 1741 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1744 | 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); | | 1742 | 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); |
1745 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], | | 1743 | bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1746 | 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); | | 1744 | 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); |
1747 | } else { | | 1745 | } else { |
1748 | /* previous */ | | 1746 | /* previous */ |
1749 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, | | 1747 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, |
1750 | 0); | | 1748 | 0); |
1751 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], | | 1749 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], |
1752 | 0, count >> 8); | | 1750 | 0, count >> 8); |
1753 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], | | 1751 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], |
1754 | 0, blkno >> 24); | | 1752 | 0, blkno >> 24); |
1755 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], | | 1753 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1756 | 0, blkno >> 32); | | 1754 | 0, blkno >> 32); |
1757 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], | | 1755 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1758 | 0, blkno >> 40); | | 1756 | 0, blkno >> 40); |
1759 | | | 1757 | |
1760 | /* current */ | | 1758 | /* current */ |
1761 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, | | 1759 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, |
1762 | 0); | | 1760 | 0); |
1763 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, | | 1761 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, |
1764 | count); | | 1762 | count); |
1765 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, | | 1763 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, |
1766 | blkno); | | 1764 | blkno); |
1767 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], | | 1765 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], |
1768 | 0, blkno >> 8); | | 1766 | 0, blkno >> 8); |
1769 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], | | 1767 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], |
1770 | 0, blkno >> 16); | | 1768 | 0, blkno >> 16); |
1771 | } | | 1769 | } |
1772 | | | 1770 | |
1773 | /* Send command. */ | | 1771 | /* Send command. */ |
1774 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); | | 1772 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1775 | return; | | 1773 | return; |
1776 | } | | 1774 | } |
1777 | | | 1775 | |
1778 | /* | | 1776 | /* |
1779 | * Simplified version of wdccommand(). Unbusy/ready/drq must be | | 1777 | * Simplified version of wdccommand(). Unbusy/ready/drq must be |
1780 | * tested by the caller. | | 1778 | * tested by the caller. |
1781 | */ | | 1779 | */ |
1782 | void | | 1780 | void |
1783 | wdccommandshort(struct ata_channel *chp, int drive, int command) | | 1781 | wdccommandshort(struct ata_channel *chp, int drive, int command) |
1784 | { | | 1782 | { |
1785 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); | | 1783 | struct wdc_softc *wdc = CHAN_TO_WDC(chp); |
1786 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; | | 1784 | struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; |
1787 | | | 1785 | |
1788 | ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", | | 1786 | ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", |
1789 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, | | 1787 | device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, |
1790 | command), DEBUG_FUNCS); | | 1788 | command), DEBUG_FUNCS); |
1791 | | | 1789 | |
1792 | if (wdc->select) | | 1790 | if (wdc->select) |
1793 | wdc->select(chp,drive); | | 1791 | wdc->select(chp,drive); |
1794 | | | 1792 | |
1795 | /* Select drive. */ | | 1793 | /* Select drive. */ |
1796 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, | | 1794 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, |
1797 | WDSD_IBM | (drive << 4)); | | 1795 | WDSD_IBM | (drive << 4)); |
1798 | | | 1796 | |
1799 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); | | 1797 | bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); |
1800 | } | | 1798 | } |
1801 | | | 1799 | |
1802 | static void | | 1800 | static void |
1803 | __wdcerror(struct ata_channel *chp, const char *msg) | | 1801 | __wdcerror(struct ata_channel *chp, const char *msg) |
1804 | { | | 1802 | { |
1805 | struct atac_softc *atac = chp->ch_atac; | | 1803 | struct atac_softc *atac = chp->ch_atac; |
1806 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; | | 1804 | struct ata_xfer *xfer = chp->ch_queue->active_xfer; |
1807 | | | 1805 | |
1808 | if (xfer == NULL) | | 1806 | if (xfer == NULL) |
1809 | aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), | | 1807 | aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), |
1810 | chp->ch_channel, msg); | | 1808 | chp->ch_channel, msg); |
1811 | else | | 1809 | else |
1812 | aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), | | 1810 | aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), |
1813 | chp->ch_channel, xfer->c_drive, msg); | | 1811 | chp->ch_channel, xfer->c_drive, msg); |
1814 | } | | 1812 | } |
1815 | | | 1813 | |
1816 | /* | | 1814 | /* |
1817 | * the bit bucket | | 1815 | * the bit bucket |
1818 | */ | | 1816 | */ |
1819 | void | | 1817 | void |
1820 | wdcbit_bucket(struct ata_channel *chp, int size) | | 1818 | wdcbit_bucket(struct ata_channel *chp, int size) |
1821 | { | | 1819 | { |
1822 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); | | 1820 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1823 | | | 1821 | |
1824 | for (; size >= 2; size -= 2) | | 1822 | for (; size >= 2; size -= 2) |
1825 | (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); | | 1823 | (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); |
1826 | if (size) | | 1824 | if (size) |
1827 | (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); | | 1825 | (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); |
1828 | } | | 1826 | } |
1829 | | | 1827 | |
1830 | static void | | 1828 | static void |
1831 | wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) | | 1829 | wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) |
1832 | { | | 1830 | { |
1833 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); | | 1831 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1834 | | | 1832 | |
1835 | #ifndef __NO_STRICT_ALIGNMENT | | 1833 | #ifndef __NO_STRICT_ALIGNMENT |
1836 | if ((uintptr_t)bf & 1) | | 1834 | if ((uintptr_t)bf & 1) |
1837 | goto unaligned; | | 1835 | goto unaligned; |
1838 | if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) | | 1836 | if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) |
1839 | goto unaligned; | | 1837 | goto unaligned; |
1840 | #endif | | 1838 | #endif |
1841 | | | 1839 | |
1842 | if (flags & DRIVE_NOSTREAM) { | | 1840 | if (flags & DRIVE_NOSTREAM) { |
1843 | if (flags & DRIVE_CAP32) { | | 1841 | if (flags & DRIVE_CAP32) { |
1844 | bus_space_read_multi_4(wdr->data32iot, | | 1842 | bus_space_read_multi_4(wdr->data32iot, |
1845 | wdr->data32ioh, 0, bf, len >> 2); | | 1843 | wdr->data32ioh, 0, bf, len >> 2); |
1846 | bf = (char *)bf + (len & ~3); | | 1844 | bf = (char *)bf + (len & ~3); |
1847 | len &= 3; | | 1845 | len &= 3; |
1848 | } | | 1846 | } |
1849 | if (len) { | | 1847 | if (len) { |
1850 | bus_space_read_multi_2(wdr->cmd_iot, | | 1848 | bus_space_read_multi_2(wdr->cmd_iot, |
1851 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); | | 1849 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1852 | } | | 1850 | } |
1853 | } else { | | 1851 | } else { |
1854 | if (flags & DRIVE_CAP32) { | | 1852 | if (flags & DRIVE_CAP32) { |
1855 | bus_space_read_multi_stream_4(wdr->data32iot, | | 1853 | bus_space_read_multi_stream_4(wdr->data32iot, |
1856 | wdr->data32ioh, 0, bf, len >> 2); | | 1854 | wdr->data32ioh, 0, bf, len >> 2); |
1857 | bf = (char *)bf + (len & ~3); | | 1855 | bf = (char *)bf + (len & ~3); |
1858 | len &= 3; | | 1856 | len &= 3; |
1859 | } | | 1857 | } |
1860 | if (len) { | | 1858 | if (len) { |
1861 | bus_space_read_multi_stream_2(wdr->cmd_iot, | | 1859 | bus_space_read_multi_stream_2(wdr->cmd_iot, |
1862 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); | | 1860 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1863 | } | | 1861 | } |
1864 | } | | 1862 | } |
1865 | return; | | 1863 | return; |
1866 | | | 1864 | |
1867 | #ifndef __NO_STRICT_ALIGNMENT | | 1865 | #ifndef __NO_STRICT_ALIGNMENT |
1868 | unaligned: | | 1866 | unaligned: |
1869 | if (flags & DRIVE_NOSTREAM) { | | 1867 | if (flags & DRIVE_NOSTREAM) { |
1870 | if (flags & DRIVE_CAP32) { | | 1868 | if (flags & DRIVE_CAP32) { |
1871 | while (len > 3) { | | 1869 | while (len > 3) { |
1872 | uint32_t val; | | 1870 | uint32_t val; |
1873 | | | 1871 | |
1874 | val = bus_space_read_4(wdr->data32iot, | | 1872 | val = bus_space_read_4(wdr->data32iot, |
1875 | wdr->data32ioh, 0); | | 1873 | wdr->data32ioh, 0); |
1876 | memcpy(bf, &val, 4); | | 1874 | memcpy(bf, &val, 4); |
1877 | bf = (char *)bf + 4; | | 1875 | bf = (char *)bf + 4; |
1878 | len -= 4; | | 1876 | len -= 4; |
1879 | } | | 1877 | } |
1880 | } | | 1878 | } |
1881 | while (len > 1) { | | 1879 | while (len > 1) { |
1882 | uint16_t val; | | 1880 | uint16_t val; |
1883 | | | 1881 | |
1884 | val = bus_space_read_2(wdr->cmd_iot, | | 1882 | val = bus_space_read_2(wdr->cmd_iot, |
1885 | wdr->cmd_iohs[wd_data], 0); | | 1883 | wdr->cmd_iohs[wd_data], 0); |
1886 | memcpy(bf, &val, 2); | | 1884 | memcpy(bf, &val, 2); |
1887 | bf = (char *)bf + 2; | | 1885 | bf = (char *)bf + 2; |
1888 | len -= 2; | | 1886 | len -= 2; |
1889 | } | | 1887 | } |
1890 | } else { | | 1888 | } else { |
1891 | if (flags & DRIVE_CAP32) { | | 1889 | if (flags & DRIVE_CAP32) { |
1892 | while (len > 3) { | | 1890 | while (len > 3) { |
1893 | uint32_t val; | | 1891 | uint32_t val; |
1894 | | | 1892 | |
1895 | val = bus_space_read_stream_4(wdr->data32iot, | | 1893 | val = bus_space_read_stream_4(wdr->data32iot, |
1896 | wdr->data32ioh, 0); | | 1894 | wdr->data32ioh, 0); |
1897 | memcpy(bf, &val, 4); | | 1895 | memcpy(bf, &val, 4); |
1898 | bf = (char *)bf + 4; | | 1896 | bf = (char *)bf + 4; |
1899 | len -= 4; | | 1897 | len -= 4; |
1900 | } | | 1898 | } |
1901 | } | | 1899 | } |
1902 | while (len > 1) { | | 1900 | while (len > 1) { |
1903 | uint16_t val; | | 1901 | uint16_t val; |
1904 | | | 1902 | |
1905 | val = bus_space_read_stream_2(wdr->cmd_iot, | | 1903 | val = bus_space_read_stream_2(wdr->cmd_iot, |
1906 | wdr->cmd_iohs[wd_data], 0); | | 1904 | wdr->cmd_iohs[wd_data], 0); |
1907 | memcpy(bf, &val, 2); | | 1905 | memcpy(bf, &val, 2); |
1908 | bf = (char *)bf + 2; | | 1906 | bf = (char *)bf + 2; |
1909 | len -= 2; | | 1907 | len -= 2; |
1910 | } | | 1908 | } |
1911 | } | | 1909 | } |
1912 | #endif | | 1910 | #endif |
1913 | } | | 1911 | } |
1914 | | | 1912 | |
1915 | static void | | 1913 | static void |
1916 | wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) | | 1914 | wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) |
1917 | { | | 1915 | { |
1918 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); | | 1916 | struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); |
1919 | | | 1917 | |
1920 | #ifndef __NO_STRICT_ALIGNMENT | | 1918 | #ifndef __NO_STRICT_ALIGNMENT |
1921 | if ((uintptr_t)bf & 1) | | 1919 | if ((uintptr_t)bf & 1) |
1922 | goto unaligned; | | 1920 | goto unaligned; |
1923 | if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) | | 1921 | if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) |
1924 | goto unaligned; | | 1922 | goto unaligned; |
1925 | #endif | | 1923 | #endif |
1926 | | | 1924 | |
1927 | if (flags & DRIVE_NOSTREAM) { | | 1925 | if (flags & DRIVE_NOSTREAM) { |
1928 | if (flags & DRIVE_CAP32) { | | 1926 | if (flags & DRIVE_CAP32) { |
1929 | bus_space_write_multi_4(wdr->data32iot, | | 1927 | bus_space_write_multi_4(wdr->data32iot, |
1930 | wdr->data32ioh, 0, bf, len >> 2); | | 1928 | wdr->data32ioh, 0, bf, len >> 2); |
1931 | bf = (char *)bf + (len & ~3); | | 1929 | bf = (char *)bf + (len & ~3); |
1932 | len &= 3; | | 1930 | len &= 3; |
1933 | } | | 1931 | } |
1934 | if (len) { | | 1932 | if (len) { |
1935 | bus_space_write_multi_2(wdr->cmd_iot, | | 1933 | bus_space_write_multi_2(wdr->cmd_iot, |
1936 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); | | 1934 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1937 | } | | 1935 | } |
1938 | } else { | | 1936 | } else { |
1939 | if (flags & DRIVE_CAP32) { | | 1937 | if (flags & DRIVE_CAP32) { |
1940 | bus_space_write_multi_stream_4(wdr->data32iot, | | 1938 | bus_space_write_multi_stream_4(wdr->data32iot, |
1941 | wdr->data32ioh, 0, bf, len >> 2); | | 1939 | wdr->data32ioh, 0, bf, len >> 2); |
1942 | bf = (char *)bf + (len & ~3); | | 1940 | bf = (char *)bf + (len & ~3); |
1943 | len &= 3; | | 1941 | len &= 3; |
1944 | } | | 1942 | } |
1945 | if (len) { | | 1943 | if (len) { |
1946 | bus_space_write_multi_stream_2(wdr->cmd_iot, | | 1944 | bus_space_write_multi_stream_2(wdr->cmd_iot, |
1947 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); | | 1945 | wdr->cmd_iohs[wd_data], 0, bf, len >> 1); |
1948 | } | | 1946 | } |
1949 | } | | 1947 | } |
1950 | return; | | 1948 | return; |
1951 | | | 1949 | |
1952 | #ifndef __NO_STRICT_ALIGNMENT | | 1950 | #ifndef __NO_STRICT_ALIGNMENT |
1953 | unaligned: | | 1951 | unaligned: |
1954 | if (flags & DRIVE_NOSTREAM) { | | 1952 | if (flags & DRIVE_NOSTREAM) { |
1955 | if (flags & DRIVE_CAP32) { | | 1953 | if (flags & DRIVE_CAP32) { |
1956 | while (len > 3) { | | 1954 | while (len > 3) { |
1957 | uint32_t val; | | 1955 | uint32_t val; |
1958 | | | 1956 | |
1959 | memcpy(&val, bf, 4); | | 1957 | memcpy(&val, bf, 4); |
1960 | bus_space_write_4(wdr->data32iot, | | 1958 | bus_space_write_4(wdr->data32iot, |
1961 | wdr->data32ioh, 0, val); | | 1959 | wdr->data32ioh, 0, val); |
1962 | bf = (char *)bf + 4; | | 1960 | bf = (char *)bf + 4; |
1963 | len -= 4; | | 1961 | len -= 4; |
1964 | } | | 1962 | } |
1965 | } | | 1963 | } |
1966 | while (len > 1) { | | 1964 | while (len > 1) { |
1967 | uint16_t val; | | 1965 | uint16_t val; |
1968 | | | 1966 | |
1969 | memcpy(&val, bf, 2); | | 1967 | memcpy(&val, bf, 2); |
1970 | bus_space_write_2(wdr->cmd_iot, | | 1968 | bus_space_write_2(wdr->cmd_iot, |
1971 | wdr->cmd_iohs[wd_data], 0, val); | | 1969 | wdr->cmd_iohs[wd_data], 0, val); |
1972 | bf = (char *)bf + 2; | | 1970 | bf = (char *)bf + 2; |
1973 | len -= 2; | | 1971 | len -= 2; |
1974 | } | | 1972 | } |
1975 | } else { | | 1973 | } else { |
1976 | if (flags & DRIVE_CAP32) { | | 1974 | if (flags & DRIVE_CAP32) { |
1977 | while (len > 3) { | | 1975 | while (len > 3) { |
1978 | uint32_t val; | | 1976 | uint32_t val; |
1979 | | | 1977 | |
1980 | memcpy(&val, bf, 4); | | 1978 | memcpy(&val, bf, 4); |
1981 | bus_space_write_stream_4(wdr->data32iot, | | 1979 | bus_space_write_stream_4(wdr->data32iot, |
1982 | wdr->data32ioh, 0, val); | | 1980 | wdr->data32ioh, 0, val); |
1983 | bf = (char *)bf + 4; | | 1981 | bf = (char *)bf + 4; |
1984 | len -= 4; | | 1982 | len -= 4; |
1985 | } | | 1983 | } |
1986 | } | | 1984 | } |
1987 | while (len > 1) { | | 1985 | while (len > 1) { |
1988 | uint16_t val; | | 1986 | uint16_t val; |
1989 | | | 1987 | |
1990 | memcpy(&val, bf, 2); | | 1988 | memcpy(&val, bf, 2); |
1991 | bus_space_write_stream_2(wdr->cmd_iot, | | 1989 | bus_space_write_stream_2(wdr->cmd_iot, |
1992 | wdr->cmd_iohs[wd_data], 0, val); | | 1990 | wdr->cmd_iohs[wd_data], 0, val); |
1993 | bf = (char *)bf + 2; | | 1991 | bf = (char *)bf + 2; |
1994 | len -= 2; | | 1992 | len -= 2; |
1995 | } | | 1993 | } |
1996 | } | | 1994 | } |
1997 | #endif | | 1995 | #endif |
1998 | } | | 1996 | } |