 @@ -1,14 +1,14 @@
-/*	$NetBSD: i386.c,v 1.25 2011/05/03 09:06:22 jruoho Exp $	*/
+/*	$NetBSD: i386.c,v 1.26 2011/12/04 17:00:10 chs Exp $	*/
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Frank van der Linden,  and by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -47,27 +47,27 @@
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
 #ifndef lint
-__RCSID("$NetBSD: i386.c,v 1.25 2011/05/03 09:06:22 jruoho Exp $");
+__RCSID("$NetBSD: i386.c,v 1.26 2011/12/04 17:00:10 chs Exp $");
 #endif /* not lint */
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/bitops.h>
 #include <sys/sysctl.h>
 #include <string.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <err.h>
 #include <assert.h>
 #include <math.h>
 @@ -172,26 +172,27 @@ static const char * const i386_intel_bra
  * AMD processors don't have Brand IDs, so we need these names for probe.
  */
 static const char * const amd_brand[] = {
 	"",
 	"Duron",	/* AMD Duron(tm) */
 	"MP",		/* AMD Athlon(tm) MP */
 	"XP",		/* AMD Athlon(tm) XP */
 	"4"		/* AMD Athlon(tm) 4 */
 };
 static int cpu_vendor;
 static char cpu_brand_string[49];
 static char amd_brand_name[48];
 static int use_pae, largepagesize;
 static void via_cpu_probe(struct cpu_info *);
 static void amd_family6_probe(struct cpu_info *);
 static void intel_family_new_probe(struct cpu_info *);
 static const char *intel_family6_name(struct cpu_info *);
 static const char *amd_amd64_name(struct cpu_info *);
 static void amd_family5_setup(struct cpu_info *);
 static void transmeta_cpu_info(struct cpu_info *);
 static const char *print_cache_config(struct cpu_info *, int, const char *,
     const char *);
 static const char *print_tlb_config(struct cpu_info *, int, const char *,
     const char *);
 static void 	amd_cpu_cacheinfo(struct cpu_info *);
 @@ -1370,26 +1371,29 @@ identifycpu(const char *cpuname)
 						name = tmp;
+				}
+			}
 			if (cpu_vendor == CPUVENDOR_IDT && family >= 6)
 				vendorname = "VIA";
+		}
+	}
 	ci->ci_cpu_class = class;
 	sz = sizeof(ci->ci_tsc_freq);
 	(void)sysctlbyname("machdep.tsc_freq", &ci->ci_tsc_freq, &sz, NULL, 0);
 	sz = sizeof(use_pae);
 	(void)sysctlbyname("machdep.pae", &use_pae, &sz, NULL, 0);
 	largepagesize = (use_pae ? 2 * 1024 * 1024 : 4 * 1024 * 1024);
 	snprintf(cpu_model, sizeof(cpu_model), "%s%s%s%s%s%s%s (%s-class)",
 	    vendorname,
 	    *modifier ? " " : "", modifier,
 	    *name ? " " : "", name,
 	    *brand ? " " : "", brand,
 	    classnames[class]);
 	aprint_normal("%s: %s", cpuname, cpu_model);
 	if (ci->ci_tsc_freq != 0)
 		aprint_normal(", %qd.%02qd MHz",
 		    (ci->ci_tsc_freq + 4999) / 1000000,
 		    ((ci->ci_tsc_freq + 4999) / 10000) % 100);
 @@ -1659,32 +1663,32 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
 		/* No L1 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000005, descs);
 	/*
 	 * K6-III and higher have large page TLBs.
 	 */
 	if ((family == 5 && model >= 9) || family >= 6) {
 		cai = &ci->ci_cinfo[CAI_ITLB2];
 		cai->cai_totalsize = AMD_L1_EAX_ITLB_ENTRIES(descs[0]);
 		cai->cai_associativity = AMD_L1_EAX_ITLB_ASSOC(descs[0]);
-		cai->cai_linesize = (4 * 1024 * 1024);
+		cai->cai_linesize = largepagesize;
 		cai = &ci->ci_cinfo[CAI_DTLB2];
 		cai->cai_totalsize = AMD_L1_EAX_DTLB_ENTRIES(descs[0]);
 		cai->cai_associativity = AMD_L1_EAX_DTLB_ASSOC(descs[0]);
-		cai->cai_linesize = (4 * 1024 * 1024);
+		cai->cai_linesize = largepagesize;
+	}
 	cai = &ci->ci_cinfo[CAI_ITLB];
 	cai->cai_totalsize = AMD_L1_EBX_ITLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L1_EBX_ITLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DTLB];
 	cai->cai_totalsize = AMD_L1_EBX_DTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L1_EBX_DTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cai = &ci->ci_cinfo[CAI_DCACHE];
 @@ -1697,26 +1701,70 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
 	cai->cai_associativity = AMD_L1_EDX_IC_ASSOC(descs[3]);
 	cai->cai_linesize = AMD_L1_EDX_IC_LS(descs[3]);
 	/*
 	 * Determine L2 cache/TLB info.
 	 */
 	if (lfunc < 0x80000006) {
 		/* No L2 cache info available. */
 		return;
+	}
 	x86_cpuid(0x80000006, descs);
 	cai = &ci->ci_cinfo[CAI_L2_ITLB];
 	cai->cai_totalsize = AMD_L2_EBX_IUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_EBX_IUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_ITLB2];
 	cai->cai_totalsize = AMD_L2_EAX_IUTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L2_EAX_IUTLB_ASSOC(descs[0]);
 	cai->cai_linesize = largepagesize;
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_DTLB];
 	cai->cai_totalsize = AMD_L2_EBX_DTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_EBX_DTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (4 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_DTLB2];
 	cai->cai_totalsize = AMD_L2_EAX_DTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L2_EAX_DTLB_ASSOC(descs[0]);
 	cai->cai_linesize = largepagesize;
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2CACHE];
 	cai->cai_totalsize = AMD_L2_ECX_C_SIZE(descs[2]);
 	cai->cai_associativity = AMD_L2_ECX_C_ASSOC(descs[2]);
 	cai->cai_linesize = AMD_L2_ECX_C_LS(descs[2]);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	/*
 @@ -1725,26 +1773,80 @@ amd_cpu_cacheinfo(struct cpu_info *ci)
 	if (family == 0x10) {
 		cai = &ci->ci_cinfo[CAI_L3CACHE];
 		cai->cai_totalsize = AMD_L3_EDX_C_SIZE(descs[3]);
 		cai->cai_associativity = AMD_L3_EDX_C_ASSOC(descs[3]);
 		cai->cai_linesize = AMD_L3_EDX_C_LS(descs[3]);
 		cp = cache_info_lookup(amd_cpuid_l3cache_assoc_info,
 		    cai->cai_associativity);
 		if (cp != NULL)
 			cai->cai_associativity = cp->cai_associativity;
 		else
 			cai->cai_associativity = 0;	/* XXX Unkn/Rsvd */
+	}
 	/*
 	 * Determine 1GB TLB info.
 	 */
 	if (lfunc < 0x80000019) {
 		/* No 1GB TLB info available. */
 		return;
+	}
 	x86_cpuid(0x80000019, descs);
 	cai = &ci->ci_cinfo[CAI_L1_1GBITLB];
 	cai->cai_totalsize = AMD_L1_1GB_EAX_IUTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L1_1GB_EAX_IUTLB_ASSOC(descs[0]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L1_1GBDTLB];
 	cai->cai_totalsize = AMD_L1_1GB_EAX_DTLB_ENTRIES(descs[0]);
 	cai->cai_associativity = AMD_L1_1GB_EAX_DTLB_ASSOC(descs[0]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_1GBITLB];
 	cai->cai_totalsize = AMD_L2_1GB_EBX_IUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_1GB_EBX_IUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
 	cai = &ci->ci_cinfo[CAI_L2_1GBDTLB];
 	cai->cai_totalsize = AMD_L2_1GB_EBX_DUTLB_ENTRIES(descs[1]);
 	cai->cai_associativity = AMD_L2_1GB_EBX_DUTLB_ASSOC(descs[1]);
 	cai->cai_linesize = (1024 * 1024 * 1024);
 	cp = cache_info_lookup(amd_cpuid_l2cache_assoc_info,
 	    cai->cai_associativity);
 	if (cp != NULL)
 		cai->cai_associativity = cp->cai_associativity;
 	else
 		cai->cai_associativity = 0;	/* XXX Unknown/reserved */
+}
 static void
 via_cpu_cacheinfo(struct cpu_info *ci)
+{
 	struct x86_cache_info *cai;
 	int family, model, stepping;
 	u_int descs[4];
 	u_int lfunc;
 	family = (ci->ci_signature >> 8) & 15;
 	model = CPUID2MODEL(ci->ci_signature);
 	stepping = CPUID2STEPPING(ci->ci_signature);
 @@ -1822,40 +1924,72 @@ x86_print_cacheinfo(struct cpu_info *ci)
 	if (ci->ci_cinfo[CAI_ICACHE].cai_totalsize != 0 ||
 	    ci->ci_cinfo[CAI_DCACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_ICACHE, "I-cache", NULL);
 		sep = print_cache_config(ci, CAI_DCACHE, "D-cache", sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2CACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_L2CACHE, "L2 cache", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
 		sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_ITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_ITLB, "ITLB", NULL);
 		sep = print_tlb_config(ci, CAI_ITLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_DTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_DTLB, "DTLB", NULL);
 		sep = print_tlb_config(ci, CAI_DTLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
-	if (ci->ci_cinfo[CAI_L3CACHE].cai_totalsize != 0) {
+	if (ci->ci_cinfo[CAI_L2_ITLB].cai_totalsize != 0) {
-		sep = print_cache_config(ci, CAI_L3CACHE, "L3 cache", NULL);
+		sep = print_tlb_config(ci, CAI_L2_ITLB, "L2 ITLB", NULL);
 		sep = print_tlb_config(ci, CAI_L2_ITLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_DTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_DTLB, "L2 DTLB", NULL);
 		sep = print_tlb_config(ci, CAI_L2_DTLB2, NULL, sep);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L1_1GBITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L1_1GBITLB, "L1 1GB page ITLB", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L1_1GBDTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L1_1GBDTLB, "L1 1GB page DTLB", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_1GBITLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_1GBITLB, "L2 1GB page ITLB", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
 	if (ci->ci_cinfo[CAI_L2_1GBDTLB].cai_totalsize != 0) {
 		sep = print_tlb_config(ci, CAI_L2_1GBDTLB, "L2 1GB page DTLB", NULL);
 		if (sep != NULL)
 			aprint_verbose("\n");
+	}
+}
 static void
 powernow_probe(struct cpu_info *ci)
+{
 	uint32_t regs[4];
 	char buf[256];
 	x86_cpuid(0x80000007, regs);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cacheinfo.h,v 1.12 2009/05/13 23:26:38 pgoyette Exp $	*/
+/*	$NetBSD: cacheinfo.h,v 1.13 2011/12/04 17:00:10 chs Exp $	*/
 #ifndef _X86_CACHEINFO_H_
 #define _X86_CACHEINFO_H_
 struct x86_cache_info {
 	uint8_t		cai_index;
 	uint8_t		cai_desc;
 	uint8_t		cai_associativity;
 	u_int		cai_totalsize; /* #entries for TLB, bytes for cache */
 	u_int		cai_linesize;	/* or page size for TLB */
 #ifndef _KERNEL
 	const char	*cai_string;
 #endif
 @@ -16,28 +16,32 @@ struct x86_cache_info {
 #define	CAI_ITLB	0		/* Instruction TLB (4K pages) */
 #define	CAI_ITLB2	1		/* Instruction TLB (2/4M pages) */
 #define	CAI_DTLB	2		/* Data TLB (4K pages) */
 #define	CAI_DTLB2	3		/* Data TLB (2/4M pages) */
 #define	CAI_ICACHE	4		/* Instruction cache */
 #define	CAI_DCACHE	5		/* Data cache */
 #define	CAI_L2CACHE	6		/* Level 2 cache */
 #define	CAI_L3CACHE	7		/* Level 3 cache */
 #define	CAI_L1_1GBITLB	8		/* L1 1GB Page instruction TLB */
 #define	CAI_L1_1GBDTLB	9		/* L1 1GB Page data TLB */
 #define CAI_L2_1GBITLB	10		/* L2 1GB Page instruction TLB */
 #define CAI_L2_1GBDTLB	11		/* L2 1GB Page data TLB */
 #define CAI_L2_ITLB	12		/* L2 Instruction TLB (4K pages) */
 #define CAI_L2_ITLB2	13		/* L2 Instruction TLB (2/4M pages) */
 #define CAI_L2_DTLB	14		/* L2 Data TLB (4K pages) */
 #define CAI_L2_DTLB2	15		/* L2 Data TLB (2/4M pages) */
-#define	CAI_COUNT	12
+#define	CAI_COUNT	16
 /*
  * AMD Cache Info:
+ *
  *      Barcelona, Phenom:
+ *
  *		Function 8000.0005 L1 TLB/Cache Information
  *		EAX -- L1 TLB 2/4MB pages
  *		EBX -- L1 TLB 4K pages
  *		ECX -- L1 D-cache
  *		EDX -- L1 I-cache
+ *
  *		Function 8000.0006 L2 TLB/Cache Information