Wed Dec 7 08:49:29 2011 UTC ()
add a bunch of register definitions


(macallan)
diff -r1.4 -r1.5 src/sys/dev/ic/sm502reg.h
cvs diff -r1.4 -r1.5 src/sys/dev/ic/sm502reg.h (expand / switch to unified diff)

--- src/sys/dev/ic/sm502reg.h 2011/11/08 06:56:36 1.4
+++ src/sys/dev/ic/sm502reg.h 2011/12/07 08:49:29 1.5
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: sm502reg.h,v 1.4 2011/11/08 06:56:36 macallan Exp $ */ 1/* $NetBSD: sm502reg.h,v 1.5 2011/12/07 08:49:29 macallan Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2009 Michael Lorenz 4 * Copyright (c) 2009 Michael Lorenz
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -49,26 +49,27 @@ @@ -49,26 +49,27 @@
49#define SM502_SYSCTL_CRT_FLIP_PENDING 0x00020000 49#define SM502_SYSCTL_CRT_FLIP_PENDING 0x00020000
50#define SM502_SYSCTL_ENGINE_BUSY 0x00080000 50#define SM502_SYSCTL_ENGINE_BUSY 0x00080000
51#define SM502_SYSCTL_FIFO_EMPTY 0x00100000 51#define SM502_SYSCTL_FIFO_EMPTY 0x00100000
52#define SM502_SYSCTL_VIDEO_FLIP_PENDING 0x00400000 52#define SM502_SYSCTL_VIDEO_FLIP_PENDING 0x00400000
53#define SM502_SYSCTL_PANEL_FLIP_PENDING 0x00800000 53#define SM502_SYSCTL_PANEL_FLIP_PENDING 0x00800000
54#define SM502_SYSCTL_PCI_LT_E 0x01000000 54#define SM502_SYSCTL_PCI_LT_E 0x01000000
55#define SM502_SYSCTL_PCI_BM_E 0x02000000 55#define SM502_SYSCTL_PCI_BM_E 0x02000000
56#define SM502_SYSCTL_CSC_BUSY 0x10000000 56#define SM502_SYSCTL_CSC_BUSY 0x10000000
57#define SM502_SYSCTL_PCI_BURST_E 0x20000000 57#define SM502_SYSCTL_PCI_BURST_E 0x20000000
58#define SM502_SYSCTL_DISABLE_HSYNC 0x40000000 58#define SM502_SYSCTL_DISABLE_HSYNC 0x40000000
59#define SM502_SYSCTL_DISABLE_VSYNC 0x80000000 59#define SM502_SYSCTL_DISABLE_VSYNC 0x80000000
60 60
61#define SM502_MISC_CONTROL 0x00000004 61#define SM502_MISC_CONTROL 0x00000004
 62#define SM502_DAC_POWER_DOWN 0x00001000
62/* each bit: 0 - GPIO, 1 - other stuff */ 63/* each bit: 0 - GPIO, 1 - other stuff */
63#define SM502_GPIO0_CONTROL 0x00000008 64#define SM502_GPIO0_CONTROL 0x00000008
64#define SM502_GPIO1_CONTROL 0x0000000c 65#define SM502_GPIO1_CONTROL 0x0000000c
65#define SM502_DRAM_CONTROL 0x00000010 66#define SM502_DRAM_CONTROL 0x00000010
66#define SM502_ARB_CONTROL 0x00000014 67#define SM502_ARB_CONTROL 0x00000014
67#define SM502_COMMANDLIST_STATUS 0x00000024 68#define SM502_COMMANDLIST_STATUS 0x00000024
68#define SM502_INTR_STATUS_R 0x00000028 /* on read */ 69#define SM502_INTR_STATUS_R 0x00000028 /* on read */
69#define SM502_INTR_CLEAR_R 0x00000028 /* on write */ 70#define SM502_INTR_CLEAR_R 0x00000028 /* on write */
70 #define SM502_RINTR_ZV1 0x00000040 /* zoomed video 1 */ 71 #define SM502_RINTR_ZV1 0x00000040 /* zoomed video 1 */
71 #define SM502_RINTR_UP 0x00000020 /* USB slave plug */ 72 #define SM502_RINTR_UP 0x00000020 /* USB slave plug */
72 #define SM502_RINTR_ZV0 0x00000010 /* zoomed video 0 */ 73 #define SM502_RINTR_ZV0 0x00000010 /* zoomed video 0 */
73 #define SM502_RINTR_CV 0x00000008 /* CRT vsync */ 74 #define SM502_RINTR_CV 0x00000008 /* CRT vsync */
74 #define SM502_RINTR_US 0x00000004 /* USB slave */ 75 #define SM502_RINTR_US 0x00000004 /* USB slave */
@@ -102,26 +103,40 @@ @@ -102,26 +103,40 @@
102 #define SM502_INTR_SSP0 0x00000100 103 #define SM502_INTR_SSP0 0x00000100
103 #define SM502_INTR_RES3 0x00000080 /* reserved */ 104 #define SM502_INTR_RES3 0x00000080 /* reserved */
104 #define SM502_INTR_UH 0x00000040 /* USB host */ 105 #define SM502_INTR_UH 0x00000040 /* USB host */
105 #define SM502_INTR_RES4 0x00000020 /* reserved */ 106 #define SM502_INTR_RES4 0x00000020 /* reserved */
106 #define SM502_INTR_ZV1 0x00000010 /* zoomed video 1 */ 107 #define SM502_INTR_ZV1 0x00000010 /* zoomed video 1 */
107 #define SM502_INTR_2D 0x00000008 /* 2D engine */ 108 #define SM502_INTR_2D 0x00000008 /* 2D engine */
108 #define SM502_INTR_ZV0 0x00000004 /* zoomed video 0 */ 109 #define SM502_INTR_ZV0 0x00000004 /* zoomed video 0 */
109 #define SM502_INTR_PV 0x00000002 /* panel vsync */ 110 #define SM502_INTR_PV 0x00000002 /* panel vsync */
110 #define SM502_INTR_CI 0x00000001 /* command interpreter */ 111 #define SM502_INTR_CI 0x00000001 /* command interpreter */
111 112
112#define SM502_DEBUG_CONTROL 0x00000034 113#define SM502_DEBUG_CONTROL 0x00000034
113 114
114#define SM502_CURRENT_GATE 0x00000038 115#define SM502_CURRENT_GATE 0x00000038
 116#define SM502_GATE_AUDIO_ENABLE 0x00040000
 117#define SM502_GATE_8051_ENABLE 0x00020000
 118#define SM502_GATE_USB_SLAVE_ENABLE 0x00001000
 119#define SM502_GATE_USB_HOST_ENABLE 0x00000800
 120#define SM502_GATE_SSP_ENABLE 0x00000400
 121#define SM502_GATE_UART1_ENABLE 0x00000100
 122#define SM502_GATE_UART0_ENABLE 0x00000080
 123#define SM502_GATE_GPIO_ENABLE 0x00000040
 124#define SM502_GATE_ZV_ENABLE 0x00000020
 125#define SM502_GATE_CSC_ENABLE 0x00000010
 126#define SM502_GATE_2D_ENGINE_ENABLE 0x00000008
 127#define SM502_GATE_DISPLAY_ENABLE 0x00000004
 128#define SM502_GATE_MEMORY_ENABLE 0x00000002
 129#define SM502_GATE_HOST_ENABLE 0x00000001
115#define SM502_CURRENT_CLOCK 0x0000003c 130#define SM502_CURRENT_CLOCK 0x0000003c
116#define SM502_POWER_MODE0_GATE 0x00000040 131#define SM502_POWER_MODE0_GATE 0x00000040
117#define SM502_POWER_MODE0_CLOCK 0x00000044 132#define SM502_POWER_MODE0_CLOCK 0x00000044
118#define SM502_POWER_MODE1_GATE 0x00000048 133#define SM502_POWER_MODE1_GATE 0x00000048
119#define SM502_POWER_MODE1_CLOCK 0x0000004c 134#define SM502_POWER_MODE1_CLOCK 0x0000004c
120#define SM502_SLEEP_MODE_GATE 0x00000050 135#define SM502_SLEEP_MODE_GATE 0x00000050
121#define SM502_POWER_MODE_CONTROL 0x00000054 136#define SM502_POWER_MODE_CONTROL 0x00000054
122 137
123/* GPIO */ 138/* GPIO */
124#define SM502_GPIO_DATA0 0x00010000 139#define SM502_GPIO_DATA0 0x00010000
125#define SM502_GPIO_DATA1 0x00010004 140#define SM502_GPIO_DATA1 0x00010004
126#define SM502_GPIO_DIR0 0x00010008 /* 1 is output */ 141#define SM502_GPIO_DIR0 0x00010008 /* 1 is output */
127#define SM502_GPIO_DIR1 0x0001000c 142#define SM502_GPIO_DIR1 0x0001000c
@@ -354,14 +369,73 @@ @@ -354,14 +369,73 @@
354#define SM502_DST_BASE_SYSMEM 0x08000000 /* local otherw. */ 369#define SM502_DST_BASE_SYSMEM 0x08000000 /* local otherw. */
355 370
356#define SM502_ALPHA 0x100048 371#define SM502_ALPHA 0x100048
357#define SM502_WRAP 0x10004c 372#define SM502_WRAP 0x10004c
358#define SM502_WRAP_HEIGHT_MASK 0x0000ffff 373#define SM502_WRAP_HEIGHT_MASK 0x0000ffff
359#define SM502_WRAP_WIDTH_MASK 0xffff0000 374#define SM502_WRAP_WIDTH_MASK 0xffff0000
360 375
361#define SM502_STATUS 0x100050 376#define SM502_STATUS 0x100050
362#define SM502_CMD_DONE 0x00000001 377#define SM502_CMD_DONE 0x00000001
363#define SM502_CSC_DONE 0x00000002 378#define SM502_CSC_DONE 0x00000002
364 379
365#define SM502_DATAPORT 0x110000 380#define SM502_DATAPORT 0x110000
366 381
 382/* AC97 Link */
 383#define SM502_AC97_TX_TAG 0x0A0100
 384#define SM502_AC97_FRAME_VALID 0x8000
 385#define SM502_AC97_S1_VALID 0x4000
 386#define SM502_AC97_S2_VALID 0x2000
 387#define SM502_AC97_S3_VALID 0x1000
 388#define SM502_AC97_S4_VALID 0x0800
 389#define SM502_AC97_TX_ADDR 0x0A0104
 390#define SM502_AC97_READ 0x00100000 /* write otherwise */
 391#define SM502_AC97_ADDR_MASK 0x000fe000
 392#define SM502_AC97_TX_DATA 0x0A0108
 393#define SM502_AC97_DATA_MASK 0x000ffff0
 394#define SM502_AC97_TX_LEFT 0x0A010C
 395#define SM502_AC97_TX_RIGHT 0x0A0110
 396#define SM502_AC97_RX_TAG 0x0A0140
 397#define SM502_AC97_RX_ADDR 0x0A0144
 398#define SM502_AC97_RX_DATA 0x0A0148
 399#define SM502_AC97_RX_LEFT 0x0A014C
 400#define SM502_AC97_RX_RIGHT 0x0A0150
 401#define SM502_AC97_CONTROL 0x0A0180
 402#define SM502_AC97_DROP_COUNT 0x0000fc00
 403#define SM502_AC97_STOP_SYNC 0x00000200
 404#define SM502_AC97_BCLK_RUNNING 0x00000100
 405#define SM502_AC97_WAKEUP_REQ 0x00000080
 406#define SM502_AC97_STATUS_MASK 0x00000030
 407#define SM502_AC97_STATUS_OFF 0x00000000
 408#define SM502_AC97_STATUS_RESET 0x00000010
 409#define SM502_AC97_STATUS_WAIT 0x00000020
 410#define SM502_AC97_STATUS_ON 0x00000030
 411#define SM502_AC97_WI_ENABLE 0x00000008 /* wakeup interrupt */
 412#define SM502_AC97_WARM_RESET 0x00000004 /* 1uS at least */
 413#define SM502_AC97_COLD_RESET 0x00000002 /* 1uS at least */
 414#define SM502_AC97_ENABLE 0x00000001
 415
 416#define SM502_AUDIO_GPIO_MASK 0x1f000000 /* pins used */
 417
 418/* 8051 Microcontroller */
 419#define SM502_uC_RESET 0x000b0000
 420#define SM502_uC_ENABLE 0x00000001 /* reset otherwise */
 421#define SM502_uC_MODE_SELECT 0x000b0004
 422#define SM502_uC_CLOCK_MASK 0x00000003
 423#define SM502_uC_CLOCK_DIV2 0x00000000
 424#define SM502_uC_CLOCK_DIV3 0x00000001
 425#define SM502_uC_CLOCK_DIV4 0x00000002
 426#define SM502_uC_CLOCK_DIV5 0x00000003
 427#define SM502_uC_CODEC_I2S 0x00000004 /* AC97 otherwise */
 428#define SM502_uC_AUDIO_TEST 0x00000008 /* test mode */
 429#define SM502_uC_IO_8BIT 0x00000010 /* 12 bit otherwise */
 430#define SM502_uC_SRAM_DISABLE 0x00000020
 431#define SM502_uC_USB_WAIT_MASK 0x000000c0
 432#define SM502_uC_USB_NO_WAIT 0x00000000
 433#define SM502_uC_USB_1_WAIT 0x00000040
 434#define SM502_uC_USB_2_WAIT 0x00000080
 435#define SM502_uC_8051_INTR 0x000b0008
 436#define SM502_uC_CPU_INTR 0x000b000c
 437
 438#define SM502_uC_SRAM_PROG 0x00dc0000 /* only readable in RESET */
 439#define SM502_uC_SRAM_DATA 0x00dc3000
 440
367#endif /* SM502REG_H */ 441#endif /* SM502REG_H */