Fri Dec 9 10:08:47 2011 UTC ()
add AMD ucode MSRs


(cegger)
diff -r1.53 -r1.54 src/sys/arch/x86/include/specialreg.h
cvs diff -r1.53 -r1.54 src/sys/arch/x86/include/specialreg.h (expand / switch to unified diff)

--- src/sys/arch/x86/include/specialreg.h 2011/10/03 17:31:35 1.53
+++ src/sys/arch/x86/include/specialreg.h 2011/12/09 10:08:47 1.54
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: specialreg.h,v 1.53 2011/10/03 17:31:35 njoly Exp $ */ 1/* $NetBSD: specialreg.h,v 1.54 2011/12/09 10:08:47 cegger Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1991 The Regents of the University of California. 4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * Redistribution and use in source and binary forms, with or without 7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions 8 * modification, are permitted provided that the following conditions
9 * are met: 9 * are met:
10 * 1. Redistributions of source code must retain the above copyright 10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer. 11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright 12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the 13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution. 14 * documentation and/or other materials provided with the distribution.
@@ -493,26 +493,28 @@ @@ -493,26 +493,28 @@
493#define DC_CFG_ERRATA_261 0x01000000 493#define DC_CFG_ERRATA_261 0x01000000
494 494
495#define MSR_BU_CFG 0xc0011023 495#define MSR_BU_CFG 0xc0011023
496#define BU_CFG_ERRATA_298 0x0000000000000002ULL 496#define BU_CFG_ERRATA_298 0x0000000000000002ULL
497#define BU_CFG_ERRATA_254 0x0000000000200000ULL 497#define BU_CFG_ERRATA_254 0x0000000000200000ULL
498#define BU_CFG_ERRATA_309 0x0000000000800000ULL 498#define BU_CFG_ERRATA_309 0x0000000000800000ULL
499#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 499#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
500#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 500#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
501#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 501#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
502 502
503/* AMD Family10h MSRs */ 503/* AMD Family10h MSRs */
504#define MSR_OSVW_ID_LENGTH 0xc0010140 504#define MSR_OSVW_ID_LENGTH 0xc0010140
505#define MSR_OSVW_STATUS 0xc0010141 505#define MSR_OSVW_STATUS 0xc0010141
 506#define MSR_UCODE_AMD_PATCHLEVEL 0x0000008b
 507#define MSR_UCODE_AMD_PATCHLOADER 0xc0010020
506 508
507/* X86 MSRs */ 509/* X86 MSRs */
508#define MSR_RDTSCP_AUX 0xc0000103 510#define MSR_RDTSCP_AUX 0xc0000103
509 511
510/* 512/*
511 * Constants related to MTRRs 513 * Constants related to MTRRs
512 */ 514 */
513#define MTRR_N64K 8 /* numbers of fixed-size entries */ 515#define MTRR_N64K 8 /* numbers of fixed-size entries */
514#define MTRR_N16K 16 516#define MTRR_N16K 16
515#define MTRR_N4K 64 517#define MTRR_N4K 64
516 518
517/* 519/*
518 * the following four 3-byte registers control the non-cacheable regions. 520 * the following four 3-byte registers control the non-cacheable regions.