Fri Dec 23 08:09:08 2011 UTC ()
add more mipsNN_cp0_config{3,4,5,6,7}_{read,write}.
Add mips3_cp0_random_read().
Add L3 encoding for RMI.


(matt)
diff -r1.78.36.1.2.30 -r1.78.36.1.2.31 src/sys/arch/mips/include/locore.h
cvs diff -r1.78.36.1.2.30 -r1.78.36.1.2.31 src/sys/arch/mips/include/locore.h (expand / switch to unified diff)

--- src/sys/arch/mips/include/locore.h 2011/05/26 19:21:55 1.78.36.1.2.30
+++ src/sys/arch/mips/include/locore.h 2011/12/23 08:09:08 1.78.36.1.2.31
@@ -136,42 +136,56 @@ uint32_t tx3900_cp0_config_read(void); @@ -136,42 +136,56 @@ uint32_t tx3900_cp0_config_read(void);
136#endif 136#endif
137 137
138#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 138#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
139uint32_t mips3_cp0_compare_read(void); 139uint32_t mips3_cp0_compare_read(void);
140void mips3_cp0_compare_write(uint32_t); 140void mips3_cp0_compare_write(uint32_t);
141 141
142uint32_t mips3_cp0_config_read(void); 142uint32_t mips3_cp0_config_read(void);
143void mips3_cp0_config_write(uint32_t); 143void mips3_cp0_config_write(uint32_t);
144 144
145#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0 145#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2 + MIPS64_RMIXL + MIPS64R2_RMIXL) > 0
146uint32_t mipsNN_cp0_config1_read(void); 146uint32_t mipsNN_cp0_config1_read(void);
147void mipsNN_cp0_config1_write(uint32_t); 147void mipsNN_cp0_config1_write(uint32_t);
148uint32_t mipsNN_cp0_config2_read(void); 148uint32_t mipsNN_cp0_config2_read(void);
 149void mipsNN_cp0_config2_write(uint32_t);
149uint32_t mipsNN_cp0_config3_read(void); 150uint32_t mipsNN_cp0_config3_read(void);
 151void mipsNN_cp0_config3_write(uint32_t);
 152uint32_t mipsNN_cp0_config4_read(void);
 153void mipsNN_cp0_config4_write(uint32_t);
 154uint32_t mipsNN_cp0_config5_read(void);
 155void mipsNN_cp0_config5_write(uint32_t);
 156uint32_t mipsNN_cp0_config6_read(void);
 157void mipsNN_cp0_config6_write(uint32_t);
 158uint32_t mipsNN_cp0_config7_read(void);
 159void mipsNN_cp0_config7_write(uint32_t);
 160uint64_t mips64_cp0_config7_read(void);
 161void mips64_cp0_config7_write(uint32_t);
150 162
151uintptr_t mipsNN_cp0_watchlo_read(u_int); 163uintptr_t mipsNN_cp0_watchlo_read(u_int);
152void mipsNN_cp0_watchlo_write(u_int, uintptr_t); 164void mipsNN_cp0_watchlo_write(u_int, uintptr_t);
153uint32_t mipsNN_cp0_watchhi_read(u_int); 165uint32_t mipsNN_cp0_watchhi_read(u_int);
154void mipsNN_cp0_watchhi_write(u_int, uint32_t); 166void mipsNN_cp0_watchhi_write(u_int, uint32_t);
155 167
156#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0 168#if (MIPS32R2 + MIPS64R2 + MIPS64R2_RMIXL) > 0
157void mipsNN_cp0_hwrena_write(uint32_t); 169void mipsNN_cp0_hwrena_write(uint32_t);
158void mipsNN_cp0_userlocal_write(void *); 170void mipsNN_cp0_userlocal_write(void *);
159#endif 171#endif
160#endif 172#endif
161 173
162uint32_t mips3_cp0_count_read(void); 174uint32_t mips3_cp0_count_read(void);
163void mips3_cp0_count_write(uint32_t); 175void mips3_cp0_count_write(uint32_t);
164 176
 177uint32_t mips3_cp0_random_read(void);
 178
165uint32_t mips3_cp0_wired_read(void); 179uint32_t mips3_cp0_wired_read(void);
166void mips3_cp0_wired_write(uint32_t); 180void mips3_cp0_wired_write(uint32_t);
167void mips3_cp0_pg_mask_write(uint32_t); 181void mips3_cp0_pg_mask_write(uint32_t);
168 182
169#if defined(__GNUC__) && !defined(__mips_o32) 183#if defined(__GNUC__) && !defined(__mips_o32)
170static inline uint64_t 184static inline uint64_t
171mips3_ld(const volatile uint64_t *va) 185mips3_ld(const volatile uint64_t *va)
172{ 186{
173 uint64_t rv; 187 uint64_t rv;
174#if defined(__mips_o32) 188#if defined(__mips_o32)
175 uint32_t sr; 189 uint32_t sr;
176 190
177 sr = mips_cp0_status_read(); 191 sr = mips_cp0_status_read();
@@ -550,44 +564,48 @@ struct pridtab { @@ -550,44 +564,48 @@ struct pridtab {
550#define MIPS_CP0FL_HWRENA __BIT(15) 564#define MIPS_CP0FL_HWRENA __BIT(15)
551 565
552/* 566/*
553 * cpu_cidflags defines, by company 567 * cpu_cidflags defines, by company
554 */ 568 */
555/* 569/*
556 * RMI company-specific cpu_cidflags 570 * RMI company-specific cpu_cidflags
557 */ 571 */
558#define MIPS_CIDFL_RMI_TYPE __BITS(2,0) 572#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
559# define CIDFL_RMI_TYPE_XLR 0 573# define CIDFL_RMI_TYPE_XLR 0
560# define CIDFL_RMI_TYPE_XLS 1 574# define CIDFL_RMI_TYPE_XLS 1
561# define CIDFL_RMI_TYPE_XLP 2 575# define CIDFL_RMI_TYPE_XLP 2
562#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3) 576#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)
563# define MIPS_CIDFL_RMI_THREADS_SHIFT 3 
564#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7) 577#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)
565# define MIPS_CIDFL_RMI_CORES_SHIFT 7 
566# define LOG2_1 0 578# define LOG2_1 0
567# define LOG2_2 1 579# define LOG2_2 1
568# define LOG2_4 2 580# define LOG2_4 2
569# define LOG2_8 3 581# define LOG2_8 3
570# define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \ 582# define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \
571 ((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \ 583 (__SHIFTIN(LOG2_ ## ncores, MIPS_CIDFL_RMI_CORES_MASK) \
572 |(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT)) 584 |__SHIFTIN(LOG2_ ## nthreads, MIPS_CIDFL_RMI_THREADS_MASK))
573# define MIPS_CIDFL_RMI_NTHREADS(cidfl) \ 585# define MIPS_CIDFL_RMI_NTHREADS(cidfl) \
574 (1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \ 586 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_THREADS_MASK))
575 >> MIPS_CIDFL_RMI_THREADS_SHIFT)) 
576# define MIPS_CIDFL_RMI_NCORES(cidfl) \ 587# define MIPS_CIDFL_RMI_NCORES(cidfl) \
577 (1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \ 588 (1 << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_CORES_MASK))
578 >> MIPS_CIDFL_RMI_CORES_SHIFT)) 
579#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11) 589#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11)
580# define MIPS_CIDFL_RMI_L2SZ_SHIFT 11 
581# define RMI_L2SZ_256KB 0 590# define RMI_L2SZ_256KB 0
582# define RMI_L2SZ_512KB 1 591# define RMI_L2SZ_512KB 1
583# define RMI_L2SZ_1MB 2 592# define RMI_L2SZ_1MB 2
584# define RMI_L2SZ_2MB 3 593# define RMI_L2SZ_2MB 3
585# define RMI_L2SZ_4MB 4 594# define RMI_L2SZ_4MB 4
586# define MIPS_CIDFL_RMI_L2(l2sz) \ 595# define MIPS_CIDFL_RMI_L2(l2sz) \
587 (RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT) 596 __SHIFTIN(RMI_L2SZ_ ## l2sz, MIPS_CIDFL_RMI_L2SZ_MASK)
588# define MIPS_CIDFL_RMI_L2SZ(cidfl) \ 597# define MIPS_CIDFL_RMI_L2SZ(cidfl) \
589 ((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \ 598 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L2SZ_MASK))
590 >> MIPS_CIDFL_RMI_L2SZ_SHIFT)) 599#define MIPS_CIDFL_RMI_L3SZ_MASK __BITS(18,15)
 600# define RMI_L3SZ_256KB 0
 601# define RMI_L3SZ_512KB 1
 602# define RMI_L3SZ_1MB 2
 603# define RMI_L3SZ_2MB 3
 604# define RMI_L3SZ_4MB 4
 605# define MIPS_CIDFL_RMI_L3(l3sz) \
 606 __SHIFTIN(RMI_L3SZ_ ## l3sz, MIPS_CIDFL_RMI_L3SZ_MASK)
 607# define MIPS_CIDFL_RMI_L3SZ(cidfl) \
 608 ((256*1024) << __SHIFTOUT((cidfl), MIPS_CIDFL_RMI_L3SZ_MASK))
591 609
592#endif /* _KERNEL */ 610#endif /* _KERNEL */
593#endif /* _MIPS_LOCORE_H */ 611#endif /* _MIPS_LOCORE_H */