Sun Dec 25 11:51:16 2011 UTC ()
Fix TLB-miss.  Don't overwrite t0 before use.


(kiyohara)
diff -r1.5 -r1.6 src/sys/arch/mips/mips/bds_emul.S
cvs diff -r1.5 -r1.6 src/sys/arch/mips/mips/bds_emul.S (expand / switch to unified diff)

--- src/sys/arch/mips/mips/bds_emul.S 2011/08/16 06:55:11 1.5
+++ src/sys/arch/mips/mips/bds_emul.S 2011/12/25 11:51:15 1.6
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: bds_emul.S,v 1.5 2011/08/16 06:55:11 matt Exp $ */ 1/* $NetBSD: bds_emul.S,v 1.6 2011/12/25 11:51:15 kiyohara Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 1992, 1993 4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved. 5 * The Regents of the University of California. All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to Berkeley by 7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell. 8 * Ralph Campbell.
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -431,28 +431,28 @@ bcemul_special_op: @@ -431,28 +431,28 @@ bcemul_special_op:
431 jr ra; nop # 071 * 431 jr ra; nop # 071 *
432 jr ra; dsrlv t0, v0, v1 # 072 DSRL 432 jr ra; dsrlv t0, v0, v1 # 072 DSRL
433 jr ra; dsrav t0, v0, v1 # 073 DSRA 433 jr ra; dsrav t0, v0, v1 # 073 DSRA
434 jr ra; dsllv t0, v0, v1 # 074 DSLL32 434 jr ra; dsllv t0, v0, v1 # 074 DSLL32
435 jr ra; nop # 075 * 435 jr ra; nop # 075 *
436 jr ra; dsrlv t0, v0, v1 # 076 DSRL32 436 jr ra; dsrlv t0, v0, v1 # 076 DSRL32
437 jr ra; dsrav t0, v0, v1 # 077 DSRA32 437 jr ra; dsrav t0, v0, v1 # 077 DSRA32
438 .set pop  438 .set pop
439 439
440bcemul_special: 440bcemul_special:
441 andi t0, a0, 0x3f # get special code 441 andi t0, a0, 0x3f # get special code
442 sll t1, t0, 3 # calculate index in specialop 442 sll t1, t0, 3 # calculate index in specialop
443 sll t0, PTR_SCALESHIFT 443 sll t0, PTR_SCALESHIFT
444 PTR_LA t0, bcemul_special_op(t1) 
445 PTR_L t9, bcemul_specialtbl(t0) 444 PTR_L t9, bcemul_specialtbl(t0)
 445 PTR_LA t0, bcemul_special_op(t1)
446 jr t9 446 jr t9
447 447
448bcemul_special_3op_prologue: 448bcemul_special_3op_prologue:
449 move t9, t0 449 move t9, t0
450 srl t0, a0, 21-REG_SCALESHIFT # rs (source1) 450 srl t0, a0, 21-REG_SCALESHIFT # rs (source1)
451 srl t1, a0, 16-REG_SCALESHIFT # rt (source2) 451 srl t1, a0, 16-REG_SCALESHIFT # rt (source2)
452 srl t2, a0, 11-REG_SCALESHIFT # rd (dest) 452 srl t2, a0, 11-REG_SCALESHIFT # rd (dest)
453 andi t0, REG_REGMASK 453 andi t0, REG_REGMASK
454 andi t1, REG_REGMASK 454 andi t1, REG_REGMASK
455 andi t2, REG_REGMASK 455 andi t2, REG_REGMASK
456 PTR_ADDU t0, a1 456 PTR_ADDU t0, a1
457 PTR_ADDU t1, a1 457 PTR_ADDU t1, a1
458 PTR_ADDU t2, a1 458 PTR_ADDU t2, a1