Tue Dec 27 19:59:24 2011 UTC ()
When filling out the physical extent, make sure to probe NOR base/limit pairs.


(matt)
diff -r1.1.2.39 -r1.1.2.40 src/sys/arch/evbmips/rmixl/machdep.c
cvs diff -r1.1.2.39 -r1.1.2.40 src/sys/arch/evbmips/rmixl/machdep.c (expand / switch to unified diff)

--- src/sys/arch/evbmips/rmixl/machdep.c 2011/12/24 01:44:44 1.1.2.39
+++ src/sys/arch/evbmips/rmixl/machdep.c 2011/12/27 19:59:24 1.1.2.40
@@ -1059,26 +1059,51 @@ rmixlp_physaddr_srio_mem_init(struct ext @@ -1059,26 +1059,51 @@ rmixlp_physaddr_srio_mem_init(struct ext
1059 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_LIMIT)); 1059 rmixlp_read_4(RMIXLP_SBC_PCITAG, RMIXLP_SBC_SRIO_MEM_LIMIT));
1060 1060
1061 if (xlimit < xbase || xbase == 0) 1061 if (xlimit < xbase || xbase == 0)
1062 return; /* not enabled */ 1062 return; /* not enabled */
1063 1063
1064 uint64_t xsize = RMIXLP_SBC_SRIO_MEM_SIZE(xbase, xlimit); 1064 uint64_t xsize = RMIXLP_SBC_SRIO_MEM_SIZE(xbase, xlimit);
1065 1065
1066 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__, 1066 DPRINTF("%s: %s: %#"PRIx64":%"PRIu64" MB\n", __func__,
1067 "srio-mem", xbase, xsize >> 20); 1067 "srio-mem", xbase, xsize >> 20);
1068 1068
1069 rmixl_physaddr_add(ext, "sriomem", &rcp->rc_srio_mem, xbase, xsize); 1069 rmixl_physaddr_add(ext, "sriomem", &rcp->rc_srio_mem, xbase, xsize);
1070} 1070}
1071 1071
 1072static void
 1073rmixlp_physaddr_nor_init(struct extent *ext)
 1074{
 1075 struct rmixl_config * const rcp = &rmixl_configuration;
 1076 for (size_t i = 0; i < RMIXLP_NOR_NCS; i++) {
 1077 uint64_t xbase = RMIXLP_NOR_CS_ADDRESS_TO_PA(
 1078 rmixlp_read_4(RMIXLP_NOR_PCITAG,
 1079 RMIXLP_NOR_CS_BASEADDRESSn(i)));
 1080 uint64_t xlimit = RMIXLP_NOR_CS_ADDRESS_TO_PA(
 1081 rmixlp_read_4(RMIXLP_NOR_PCITAG,
 1082 RMIXLP_NOR_CS_BASELIMITn(i)));
 1083
 1084 if (xlimit < xbase || xbase == 0)
 1085 continue; /* not enabled */
 1086
 1087 uint64_t xsize = RMIXLP_NOR_CS_SIZE(xbase, xlimit);
 1088
 1089 DPRINTF("%s: %s %zu: %#"PRIx64":%"PRIu64" MB\n", __func__,
 1090 "nor", i, xbase, xsize >> 20);
 1091
 1092 rmixl_physaddr_add(ext, "nor", &rcp->rc_pci_link_io[i],
 1093 xbase, xsize);
 1094 }
 1095}
 1096
1072static uint64_t 1097static uint64_t
1073rmixlp_physaddr_dram_init(struct extent *ext) 1098rmixlp_physaddr_dram_init(struct extent *ext)
1074{ 1099{
1075 uint64_t memsize = 0; 1100 uint64_t memsize = 0;
1076 /* 1101 /*
1077 * grab regions per DRAM BARs 1102 * grab regions per DRAM BARs
1078 */ 1103 */
1079 phys_ram_seg_t *mp = mem_clusters; 1104 phys_ram_seg_t *mp = mem_clusters;
1080 for (u_int i = 0; i < RMIXLP_SBC_NDRAM; i++) { 1105 for (u_int i = 0; i < RMIXLP_SBC_NDRAM; i++) {
1081 uint64_t xbase = 1106 uint64_t xbase =
1082 RMIXLP_SBC_DRAM_TO_PA( 1107 RMIXLP_SBC_DRAM_TO_PA(
1083 rmixlp_read_4(RMIXLP_SBC_PCITAG, 1108 rmixlp_read_4(RMIXLP_SBC_PCITAG,
1084 RMIXLP_SBC_DRAM_BASEn(i))); 1109 RMIXLP_SBC_DRAM_BASEn(i)));
@@ -1170,26 +1195,27 @@ rmixl_physaddr_init(void) @@ -1170,26 +1195,27 @@ rmixl_physaddr_init(void)
1170 EX_NOWAIT | EX_NOCOALESCE); 1195 EX_NOWAIT | EX_NOCOALESCE);
1171 1196
1172 if (ext == NULL) 1197 if (ext == NULL)
1173 panic("%s: extent_create failed", __func__); 1198 panic("%s: extent_create failed", __func__);
1174 1199
1175 if (is_xlp_p) { 1200 if (is_xlp_p) {
1176#if (MIPS64_XLP) > 0 1201#if (MIPS64_XLP) > 0
1177 memsize = rmixlp_physaddr_dram_init(ext); 1202 memsize = rmixlp_physaddr_dram_init(ext);
1178 rmixlp_physaddr_pcie_cfg_init(ext); 1203 rmixlp_physaddr_pcie_cfg_init(ext);
1179 rmixlp_physaddr_pcie_ecfg_init(ext); 1204 rmixlp_physaddr_pcie_ecfg_init(ext);
1180 rmixlp_physaddr_pcie_mem_init(ext); 1205 rmixlp_physaddr_pcie_mem_init(ext);
1181 rmixlp_physaddr_pcie_io_init(ext); 1206 rmixlp_physaddr_pcie_io_init(ext);
1182 rmixlp_physaddr_srio_mem_init(ext); 1207 rmixlp_physaddr_srio_mem_init(ext);
 1208 rmixlp_physaddr_nor_init(ext);
1183#else 1209#else
1184 memsize = 0; 1210 memsize = 0;
1185#endif /* MIPS64_XLP */ 1211#endif /* MIPS64_XLP */
1186 } else { 1212 } else {
1187#if (MIPS64_XLR + MIPS64_XLS) > 0 1213#if (MIPS64_XLR + MIPS64_XLS) > 0
1188 memsize = rmixl_physaddr_dram_init(ext); 1214 memsize = rmixl_physaddr_dram_init(ext);
1189 1215
1190 /* 1216 /*
1191 * get chip-dependent physaddr regions 1217 * get chip-dependent physaddr regions
1192 */ 1218 */
1193 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) { 1219 switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) {
1194 case CIDFL_RMI_TYPE_XLR: 1220 case CIDFL_RMI_TYPE_XLR:
1195#if NRMIXL_PCIX 1221#if NRMIXL_PCIX