| @@ -1,421 +1,421 @@ | | | @@ -1,421 +1,421 @@ |
1 | /* $NetBSD: cpu.h,v 1.67 2012/01/20 06:50:00 skrll Exp $ */ | | 1 | /* $NetBSD: cpu.h,v 1.68 2012/01/20 06:51:19 skrll Exp $ */ |
2 | | | 2 | |
3 | /* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */ | | 3 | /* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */ |
4 | | | 4 | |
5 | /* | | 5 | /* |
6 | * Copyright (c) 2000-2004 Michael Shalayeff | | 6 | * Copyright (c) 2000-2004 Michael Shalayeff |
7 | * All rights reserved. | | 7 | * All rights reserved. |
8 | * | | 8 | * |
9 | * Redistribution and use in source and binary forms, with or without | | 9 | * Redistribution and use in source and binary forms, with or without |
10 | * modification, are permitted provided that the following conditions | | 10 | * modification, are permitted provided that the following conditions |
11 | * are met: | | 11 | * are met: |
12 | * 1. Redistributions of source code must retain the above copyright | | 12 | * 1. Redistributions of source code must retain the above copyright |
13 | * notice, this list of conditions and the following disclaimer. | | 13 | * notice, this list of conditions and the following disclaimer. |
14 | * 2. Redistributions in binary form must reproduce the above copyright | | 14 | * 2. Redistributions in binary form must reproduce the above copyright |
15 | * notice, this list of conditions and the following disclaimer in the | | 15 | * notice, this list of conditions and the following disclaimer in the |
16 | * documentation and/or other materials provided with the distribution. | | 16 | * documentation and/or other materials provided with the distribution. |
17 | * | | 17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | | 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | | 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. | | 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
21 | * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, | | 21 | * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, |
22 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | | 22 | * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
23 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | | 23 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
24 | * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | | 24 | * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | | 25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
26 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | | 26 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
27 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | | 27 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
28 | * THE POSSIBILITY OF SUCH DAMAGE. | | 28 | * THE POSSIBILITY OF SUCH DAMAGE. |
29 | */ | | 29 | */ |
30 | /* | | 30 | /* |
31 | * Copyright (c) 1988-1994, The University of Utah and | | 31 | * Copyright (c) 1988-1994, The University of Utah and |
32 | * the Computer Systems Laboratory at the University of Utah (CSL). | | 32 | * the Computer Systems Laboratory at the University of Utah (CSL). |
33 | * All rights reserved. | | 33 | * All rights reserved. |
34 | * | | 34 | * |
35 | * Permission to use, copy, modify and distribute this software is hereby | | 35 | * Permission to use, copy, modify and distribute this software is hereby |
36 | * granted provided that (1) source code retains these copyright, permission, | | 36 | * granted provided that (1) source code retains these copyright, permission, |
37 | * and disclaimer notices, and (2) redistributions including binaries | | 37 | * and disclaimer notices, and (2) redistributions including binaries |
38 | * reproduce the notices in supporting documentation, and (3) all advertising | | 38 | * reproduce the notices in supporting documentation, and (3) all advertising |
39 | * materials mentioning features or use of this software display the following | | 39 | * materials mentioning features or use of this software display the following |
40 | * acknowledgement: ``This product includes software developed by the | | 40 | * acknowledgement: ``This product includes software developed by the |
41 | * Computer Systems Laboratory at the University of Utah.'' | | 41 | * Computer Systems Laboratory at the University of Utah.'' |
42 | * | | 42 | * |
43 | * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS | | 43 | * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS |
44 | * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF | | 44 | * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF |
45 | * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | | 45 | * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
46 | * | | 46 | * |
47 | * CSL requests users of this software to return to csl-dist@cs.utah.edu any | | 47 | * CSL requests users of this software to return to csl-dist@cs.utah.edu any |
48 | * improvements that they make and grant CSL redistribution rights. | | 48 | * improvements that they make and grant CSL redistribution rights. |
49 | * | | 49 | * |
50 | * Utah $Hdr: cpu.h 1.19 94/12/16$ | | 50 | * Utah $Hdr: cpu.h 1.19 94/12/16$ |
51 | */ | | 51 | */ |
52 | | | 52 | |
53 | #ifndef _MACHINE_CPU_H_ | | 53 | #ifndef _MACHINE_CPU_H_ |
54 | #define _MACHINE_CPU_H_ | | 54 | #define _MACHINE_CPU_H_ |
55 | | | 55 | |
56 | #ifdef _KERNEL_OPT | | 56 | #ifdef _KERNEL_OPT |
57 | #include "opt_cputype.h" | | 57 | #include "opt_cputype.h" |
58 | #endif | | 58 | #endif |
59 | | | 59 | |
60 | #include <machine/trap.h> | | 60 | #include <machine/trap.h> |
61 | #include <machine/frame.h> | | 61 | #include <machine/frame.h> |
62 | #include <machine/reg.h> | | 62 | #include <machine/reg.h> |
63 | | | 63 | |
64 | #ifndef _LOCORE | | 64 | #ifndef _LOCORE |
65 | | | 65 | |
66 | /* types */ | | 66 | /* types */ |
67 | enum hppa_cpu_type { | | 67 | enum hppa_cpu_type { |
68 | hpc_unknown, | | 68 | hpc_unknown, |
69 | hpcx, /* PA7000 (x) PA 1.0 */ | | 69 | hpcx, /* PA7000 (x) PA 1.0 */ |
70 | hpcxs, /* PA7000 (s) PA 1.1a */ | | 70 | hpcxs, /* PA7000 (s) PA 1.1a */ |
71 | hpcxt, /* PA7100 (t) PA 1.1b */ | | 71 | hpcxt, /* PA7100 (t) PA 1.1b */ |
72 | hpcxl, /* PA7100LC (l) PA 1.1c */ | | 72 | hpcxl, /* PA7100LC (l) PA 1.1c */ |
73 | hpcxtp, /* PA7200 (t') PA 1.1d */ | | 73 | hpcxtp, /* PA7200 (t') PA 1.1d */ |
74 | hpcxl2, /* PA7300LC (l2) PA 1.1e */ | | 74 | hpcxl2, /* PA7300LC (l2) PA 1.1e */ |
75 | hpcxu, /* PA8000 (u) PA 2.0 */ | | 75 | hpcxu, /* PA8000 (u) PA 2.0 */ |
76 | hpcxup, /* PA8200 (u+) PA 2.0 */ | | 76 | hpcxup, /* PA8200 (u+) PA 2.0 */ |
77 | hpcxw, /* PA8500 (w) PA 2.0 */ | | 77 | hpcxw, /* PA8500 (w) PA 2.0 */ |
78 | hpcxwp, /* PA8600 (w+) PA 2.0 */ | | 78 | hpcxwp, /* PA8600 (w+) PA 2.0 */ |
79 | hpcxw2, /* PA8700 (piranha) PA 2.0 */ | | 79 | hpcxw2, /* PA8700 (piranha) PA 2.0 */ |
80 | mako /* PA8800 (mako) PA 2.0 */ | | 80 | mako /* PA8800 (mako) PA 2.0 */ |
81 | }; | | 81 | }; |
82 | | | 82 | |
83 | /* | | 83 | /* |
84 | * A CPU description. | | 84 | * A CPU description. |
85 | */ | | 85 | */ |
86 | struct hppa_cpu_info { | | 86 | struct hppa_cpu_info { |
87 | /* The official name of the chip. */ | | 87 | /* The official name of the chip. */ |
88 | const char *hci_chip_name; | | 88 | const char *hci_chip_name; |
89 | | | 89 | |
90 | /* The nickname for the chip. */ | | 90 | /* The nickname for the chip. */ |
91 | const char *hci_chip_nickname; | | 91 | const char *hci_chip_nickname; |
92 | | | 92 | |
93 | /* The type and PA-RISC specification of the chip. */ | | 93 | /* The type and PA-RISC specification of the chip. */ |
94 | const char hci_chip_type[8]; | | 94 | const char hci_chip_type[8]; |
95 | enum hppa_cpu_type hci_cputype; | | 95 | enum hppa_cpu_type hci_cputype; |
96 | int hci_cpuversion; | | 96 | int hci_cpuversion; |
97 | int hci_features; /* CPU types and features */ | | 97 | int hci_features; /* CPU types and features */ |
98 | #define HPPA_FTRS_TLBU 0x00000001 | | 98 | #define HPPA_FTRS_TLBU 0x00000001 |
99 | #define HPPA_FTRS_BTLBU 0x00000002 | | 99 | #define HPPA_FTRS_BTLBU 0x00000002 |
100 | #define HPPA_FTRS_HVT 0x00000004 | | 100 | #define HPPA_FTRS_HVT 0x00000004 |
101 | #define HPPA_FTRS_W32B 0x00000008 | | 101 | #define HPPA_FTRS_W32B 0x00000008 |
102 | | | 102 | |
103 | const char *hci_chip_spec; | | 103 | const char *hci_chip_spec; |
104 | | | 104 | |
105 | int (*desidhash)(void); | | 105 | int (*desidhash)(void); |
106 | const u_int *itlbh, *dtlbh, *itlbnah, *dtlbnah, *tlbdh; | | 106 | const u_int *itlbh, *dtlbh, *itlbnah, *dtlbnah, *tlbdh; |
107 | int (*dbtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); | | 107 | int (*dbtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); |
108 | int (*ibtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); | | 108 | int (*ibtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); |
109 | int (*btlbprg)(int); | | 109 | int (*btlbprg)(int); |
110 | int (*hptinit)(vaddr_t, vsize_t); | | 110 | int (*hptinit)(vaddr_t, vsize_t); |
111 | }; | | 111 | }; |
112 | | | 112 | |
113 | #ifdef _KERNEL | | 113 | #ifdef _KERNEL |
114 | extern const struct hppa_cpu_info *hppa_cpu_info; | | 114 | extern const struct hppa_cpu_info *hppa_cpu_info; |
115 | extern int cpu_modelno; | | 115 | extern int cpu_modelno; |
116 | extern int cpu_revision; | | 116 | extern int cpu_revision; |
117 | #endif | | 117 | #endif |
118 | #endif | | 118 | #endif |
119 | | | 119 | |
120 | /* | | 120 | /* |
121 | * COPR/SFUs | | 121 | * COPR/SFUs |
122 | */ | | 122 | */ |
123 | #define HPPA_FPUS 0xc0 | | 123 | #define HPPA_FPUS 0xc0 |
124 | #define HPPA_PMSFUS 0x20 /* ??? */ | | 124 | #define HPPA_PMSFUS 0x20 /* ??? */ |
125 | | | 125 | |
126 | /* | | 126 | /* |
127 | * Exported definitions unique to hp700/PA-RISC cpu support. | | 127 | * Exported definitions unique to hp700/PA-RISC cpu support. |
128 | */ | | 128 | */ |
129 | | | 129 | |
130 | /* | | 130 | /* |
131 | * COPR/SFUs | | 131 | * COPR/SFUs |
132 | */ | | 132 | */ |
133 | #define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11) | | 133 | #define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11) |
134 | #define HPPA_FPU_OP(w) ((w) >> 26) | | 134 | #define HPPA_FPU_OP(w) ((w) >> 26) |
135 | #define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */ | | 135 | #define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */ |
136 | #define HPPA_FPU_ILL 0x80 /* software-only */ | | 136 | #define HPPA_FPU_ILL 0x80 /* software-only */ |
137 | #define HPPA_FPU_I 0x01 | | 137 | #define HPPA_FPU_I 0x01 |
138 | #define HPPA_FPU_U 0x02 | | 138 | #define HPPA_FPU_U 0x02 |
139 | #define HPPA_FPU_O 0x04 | | 139 | #define HPPA_FPU_O 0x04 |
140 | #define HPPA_FPU_Z 0x08 | | 140 | #define HPPA_FPU_Z 0x08 |
141 | #define HPPA_FPU_V 0x10 | | 141 | #define HPPA_FPU_V 0x10 |
142 | #define HPPA_FPU_D 0x20 | | 142 | #define HPPA_FPU_D 0x20 |
143 | #define HPPA_FPU_T 0x40 | | 143 | #define HPPA_FPU_T 0x40 |
144 | #define HPPA_FPU_XMASK 0x7f | | 144 | #define HPPA_FPU_XMASK 0x7f |
145 | #define HPPA_FPU_T_POS 25 | | 145 | #define HPPA_FPU_T_POS 25 |
146 | #define HPPA_FPU_RM 0x00000600 | | 146 | #define HPPA_FPU_RM 0x00000600 |
147 | #define HPPA_FPU_CQ 0x00fff800 | | 147 | #define HPPA_FPU_CQ 0x00fff800 |
148 | #define HPPA_FPU_C 0x04000000 | | 148 | #define HPPA_FPU_C 0x04000000 |
149 | #define HPPA_FPU_FLSH 27 | | 149 | #define HPPA_FPU_FLSH 27 |
150 | #define HPPA_FPU_INIT (0) | | 150 | #define HPPA_FPU_INIT (0) |
151 | #define HPPA_FPU_FORK(s) ((s) & ~((uint64_t)(HPPA_FPU_XMASK) << 32)) | | 151 | #define HPPA_FPU_FORK(s) ((s) & ~((uint64_t)(HPPA_FPU_XMASK) << 32)) |
152 | | | 152 | |
153 | /* | | 153 | /* |
154 | * definitions of cpu-dependent requirements | | 154 | * definitions of cpu-dependent requirements |
155 | * referenced in generic code | | 155 | * referenced in generic code |
156 | */ | | 156 | */ |
157 | #if defined(HP8000_CPU) || defined(HP8200_CPU) || \ | | 157 | #if defined(HP8000_CPU) || defined(HP8200_CPU) || \ |
158 | defined(HP8500_CPU) || defined(HP8600_CPU) | | 158 | defined(HP8500_CPU) || defined(HP8600_CPU) |
159 | | | 159 | |
160 | /* PA2.0 aliases */ | | 160 | /* PA2.0 aliases */ |
161 | #define HPPA_PGALIAS 0x00400000 | | 161 | #define HPPA_PGALIAS 0x00400000 |
162 | #define HPPA_PGAMASK 0xffc00000 /* PA bits 0-9 not used in index */ | | 162 | #define HPPA_PGAMASK 0xffc00000 /* PA bits 0-9 not used in index */ |
163 | #define HPPA_PGAOFF 0x003fffff | | 163 | #define HPPA_PGAOFF 0x003fffff |
164 | | | 164 | |
165 | #else | | 165 | #else |
166 | | | 166 | |
167 | /* PA1.x aliases */ | | 167 | /* PA1.x aliases */ |
168 | #define HPPA_PGALIAS 0x00100000 | | 168 | #define HPPA_PGALIAS 0x00100000 |
169 | #define HPPA_PGAMASK 0xfff00000 /* PA bits 0-11 not used in index */ | | 169 | #define HPPA_PGAMASK 0xfff00000 /* PA bits 0-11 not used in index */ |
170 | #define HPPA_PGAOFF 0x000fffff | | 170 | #define HPPA_PGAOFF 0x000fffff |
171 | | | 171 | |
172 | #endif | | 172 | #endif |
173 | | | 173 | |
174 | #define HPPA_SPAMASK 0xf0f0f000 /* PA bits 0-3,8-11,16-19 not used */ | | 174 | #define HPPA_SPAMASK 0xf0f0f000 /* PA bits 0-3,8-11,16-19 not used */ |
175 | | | 175 | |
176 | #define HPPA_IOSPACE 0xf0000000 | | 176 | #define HPPA_IOSPACE 0xf0000000 |
177 | #define HPPA_IOLEN 0x10000000 | | 177 | #define HPPA_IOLEN 0x10000000 |
178 | #define HPPA_PDC_LOW 0xef000000 | | 178 | #define HPPA_PDC_LOW 0xef000000 |
179 | #define HPPA_PDC_HIGH 0xf1000000 | | 179 | #define HPPA_PDC_HIGH 0xf1000000 |
180 | #define HPPA_IOBCAST 0xfffc0000 | | 180 | #define HPPA_IOBCAST 0xfffc0000 |
181 | #define HPPA_LBCAST 0xfffc0000 | | 181 | #define HPPA_LBCAST 0xfffc0000 |
182 | #define HPPA_GBCAST 0xfffe0000 | | 182 | #define HPPA_GBCAST 0xfffe0000 |
183 | #define HPPA_FPA 0xfff80000 | | 183 | #define HPPA_FPA 0xfff80000 |
184 | #define HPPA_FLEX_DATA 0xfff80001 | | 184 | #define HPPA_FLEX_DATA 0xfff80001 |
185 | #define HPPA_DMA_ENABLE 0x00000001 | | 185 | #define HPPA_DMA_ENABLE 0x00000001 |
186 | #define HPPA_SPA_ENABLE 0x00000020 | | 186 | #define HPPA_SPA_ENABLE 0x00000020 |
187 | #define HPPA_NMODSPBUS 64 | | 187 | #define HPPA_NMODSPBUS 64 |
188 | | | 188 | |
189 | #ifdef MULTIPROCESSOR | | 189 | #ifdef MULTIPROCESSOR |
190 | | | 190 | |
191 | #define GET_CURCPU(r) mfctl CR_CURCPU, r | | 191 | #define GET_CURCPU(r) mfctl CR_CURCPU, r |
192 | #define GET_CURCPU_SPACE(s, r) GET_CURCPU(r) | | 192 | #define GET_CURCPU_SPACE(s, r) GET_CURCPU(r) |
193 | #define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r | | 193 | #define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r |
194 | #define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r | | 194 | #define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r |
195 | | | 195 | |
196 | #define SET_CURLWP(r,t) mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) | | 196 | #define SET_CURLWP(r,t) mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) |
197 | | | 197 | |
198 | #else /* MULTIPROCESSOR */ | | 198 | #else /* MULTIPROCESSOR */ |
199 | | | 199 | |
200 | #define GET_CURCPU(r) mfctl CR_CURLWP, r ! ldw L_CPU(r), r | | 200 | #define GET_CURCPU(r) mfctl CR_CURLWP, r ! ldw L_CPU(r), r |
201 | #define GET_CURCPU_SPACE(s, r) mfctl CR_CURLWP, r ! ldw L_CPU(s, r), r | | 201 | #define GET_CURCPU_SPACE(s, r) mfctl CR_CURLWP, r ! ldw L_CPU(s, r), r |
202 | #define GET_CURLWP(r) mfctl CR_CURLWP, r | | 202 | #define GET_CURLWP(r) mfctl CR_CURLWP, r |
203 | #define GET_CURLWP_SPACE(s, r) GET_CURLWP(r) | | 203 | #define GET_CURLWP_SPACE(s, r) GET_CURLWP(r) |
204 | | | 204 | |
205 | #define SET_CURLWP(r,t) mtctl r, CR_CURLWP | | 205 | #define SET_CURLWP(r,t) mtctl r, CR_CURLWP |
206 | | | 206 | |
207 | #endif /* MULTIPROCESSOR */ | | 207 | #endif /* MULTIPROCESSOR */ |
208 | | | 208 | |
209 | #ifndef _LOCORE | | 209 | #ifndef _LOCORE |
210 | #ifdef _KERNEL | | 210 | #ifdef _KERNEL |
211 | | | 211 | |
212 | /* | | 212 | /* |
213 | * External definitions unique to PA-RISC cpu support. | | 213 | * External definitions unique to PA-RISC cpu support. |
214 | * These are the "public" declarations - those needed in | | 214 | * These are the "public" declarations - those needed in |
215 | * machine-independent source code. The "private" ones | | 215 | * machine-independent source code. The "private" ones |
216 | * are in machdep.h. | | 216 | * are in machdep.h. |
217 | * | | 217 | * |
218 | * Note that the name of this file is NOT meant to imply | | 218 | * Note that the name of this file is NOT meant to imply |
219 | * that it has anything to do with PA-RISC CPU stuff. | | 219 | * that it has anything to do with PA-RISC CPU stuff. |
220 | * The name "cpu" is historical, and used in the common | | 220 | * The name "cpu" is historical, and used in the common |
221 | * code to identify machine-dependent functions, etc. | | 221 | * code to identify machine-dependent functions, etc. |
222 | */ | | 222 | */ |
223 | | | 223 | |
224 | /* clockframe describes the system before we took an interrupt. */ | | 224 | /* clockframe describes the system before we took an interrupt. */ |
225 | struct clockframe { | | 225 | struct clockframe { |
226 | int cf_flags; | | 226 | int cf_flags; |
227 | int cf_spl; | | 227 | int cf_spl; |
228 | u_int cf_pc; | | 228 | u_int cf_pc; |
229 | }; | | 229 | }; |
230 | #define CLKF_PC(framep) ((framep)->cf_pc) | | 230 | #define CLKF_PC(framep) ((framep)->cf_pc) |
231 | #define CLKF_INTR(framep) ((framep)->cf_flags & TFF_INTR) | | 231 | #define CLKF_INTR(framep) ((framep)->cf_flags & TFF_INTR) |
232 | #define CLKF_USERMODE(framep) ((framep)->cf_flags & T_USER) | | 232 | #define CLKF_USERMODE(framep) ((framep)->cf_flags & T_USER) |
233 | | | 233 | |
234 | int clock_intr(void *); | | 234 | int clock_intr(void *); |
235 | | | 235 | |
236 | /* | | 236 | /* |
237 | * LWP_PC: the program counter for the given lwp. | | 237 | * LWP_PC: the program counter for the given lwp. |
238 | */ | | 238 | */ |
239 | #define LWP_PC(l) ((l)->l_md.md_regs->tf_iioq_head) | | 239 | #define LWP_PC(l) ((l)->l_md.md_regs->tf_iioq_head) |
240 | | | 240 | |
241 | #define cpu_signotify(l) (setsoftast(l)) | | 241 | #define cpu_signotify(l) (setsoftast(l)) |
242 | #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast(l)) | | 242 | #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast(l)) |
243 | | | 243 | |
244 | #endif /* _KERNEL */ | | 244 | #endif /* _KERNEL */ |
245 | | | 245 | |
246 | #if defined(_KERNEL) || defined(_KMEMUSER) | | 246 | #if defined(_KERNEL) || defined(_KMEMUSER) |
247 | | | 247 | |
248 | #include <sys/cpu_data.h> | | 248 | #include <sys/cpu_data.h> |
249 | | | 249 | |
250 | /* | | 250 | /* |
251 | * Note that the alignment of ci_trap_save is important since we want to keep | | 251 | * Note that the alignment of ci_trap_save is important since we want to keep |
252 | * it within a single cache line. As a result, it must be kept as the first | | 252 | * it within a single cache line. As a result, it must be kept as the first |
253 | * entry within the cpu_info struct. | | 253 | * entry within the cpu_info struct. |
254 | */ | | 254 | */ |
255 | struct cpu_info { | | 255 | struct cpu_info { |
256 | /* Keep this first to simplify the trap handlers */ | | 256 | /* Keep this first to simplify the trap handlers */ |
257 | register_t ci_trapsave[16];/* the "phys" part of frame */ | | 257 | register_t ci_trapsave[16];/* the "phys" part of frame */ |
258 | | | 258 | |
259 | struct cpu_data ci_data; /* MI per-cpu data */ | | 259 | struct cpu_data ci_data; /* MI per-cpu data */ |
260 | | | 260 | |
261 | #ifndef _KMEMUSER | | 261 | #ifndef _KMEMUSER |
262 | int ci_cpuid; /* CPU index (see cpus[] array) */ | | 262 | int ci_cpuid; /* CPU index (see cpus[] array) */ |
263 | int ci_mtx_count; | | 263 | int ci_mtx_count; |
264 | int ci_mtx_oldspl; | | 264 | int ci_mtx_oldspl; |
265 | int ci_want_resched; | | 265 | int ci_want_resched; |
266 | | | 266 | |
267 | volatile int ci_cpl; | | 267 | volatile int ci_cpl; |
268 | volatile int ci_ipending; /* The pending interrupts. */ | | 268 | volatile int ci_ipending; /* The pending interrupts. */ |
269 | u_int ci_intr_depth; /* Nonzero iff running an interrupt. */ | | 269 | u_int ci_intr_depth; /* Nonzero iff running an interrupt. */ |
270 | | | 270 | |
271 | hppa_hpa_t ci_hpa; | | 271 | hppa_hpa_t ci_hpa; |
272 | register_t ci_psw; /* Processor Status Word. */ | | 272 | register_t ci_psw; /* Processor Status Word. */ |
273 | paddr_t ci_fpu_state; /* LWP FPU state address, or zero. */ | | 273 | paddr_t ci_fpu_state; /* LWP FPU state address, or zero. */ |
274 | u_long ci_itmr; | | 274 | u_long ci_itmr; |
275 | | | 275 | |
276 | #if defined(MULTIPROCESSOR) | | 276 | #if defined(MULTIPROCESSOR) |
277 | struct lwp *ci_curlwp; /* CPU owner */ | | 277 | struct lwp *ci_curlwp; /* CPU owner */ |
278 | paddr_t ci_stack; /* stack for spin up */ | | 278 | paddr_t ci_stack; /* stack for spin up */ |
279 | volatile int ci_flags; /* CPU status flags */ | | 279 | volatile int ci_flags; /* CPU status flags */ |
280 | #define CPUF_PRIMARY 0x0001 /* ... is monarch/primary */ | | 280 | #define CPUF_PRIMARY 0x0001 /* ... is monarch/primary */ |
281 | #define CPUF_RUNNING 0x0002 /* ... is running. */ | | 281 | #define CPUF_RUNNING 0x0002 /* ... is running. */ |
282 | | | 282 | |
283 | #endif | | 283 | #endif |
284 | | | 284 | |
285 | #endif /* !_KMEMUSER */ | | 285 | #endif /* !_KMEMUSER */ |
286 | } __aligned(64); | | 286 | } __aligned(64); |
287 | | | 287 | |
288 | #endif /* _KERNEL || _KMEMUSER */ | | 288 | #endif /* _KERNEL || _KMEMUSER */ |
289 | | | 289 | |
290 | #if defined(_KERNEL) | | 290 | #if defined(_KERNEL) |
291 | | | 291 | |
292 | /* | | 292 | /* |
293 | * definitions of cpu-dependent requirements | | 293 | * definitions of cpu-dependent requirements |
294 | * referenced in generic code | | 294 | * referenced in generic code |
295 | */ | | 295 | */ |
296 | | | 296 | |
297 | #define cpu_proc_fork(p1, p2) | | 297 | #define cpu_proc_fork(p1, p2) |
298 | | | 298 | |
299 | #ifdef MULTIPROCESSOR | | 299 | #ifdef MULTIPROCESSOR |
300 | | | 300 | |
301 | /* Number of CPUs in the system */ | | 301 | /* Number of CPUs in the system */ |
302 | extern int hppa_ncpu; | | 302 | extern int hppa_ncpu; |
303 | | | 303 | |
304 | #define HPPA_MAXCPUS 4 | | 304 | #define HPPA_MAXCPUS 4 |
305 | #define cpu_number() (curcpu()->ci_cpuid) | | 305 | #define cpu_number() (curcpu()->ci_cpuid) |
306 | | | 306 | |
307 | #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) | | 307 | #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) |
308 | #define CPU_INFO_ITERATOR int | | 308 | #define CPU_INFO_ITERATOR int |
309 | #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = &cpus[0]; cii < hppa_ncpu; cii++, ci++ | | 309 | #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = &cpus[0]; cii < hppa_ncpu; cii++, ci++ |
310 | | | 310 | |
311 | void cpu_boot_secondary_processors(void); | | 311 | void cpu_boot_secondary_processors(void); |
312 | | | 312 | |
313 | static __inline struct cpu_info * | | 313 | static __inline struct cpu_info * |
314 | hppa_curcpu(void) | | 314 | hppa_curcpu(void) |
315 | { | | 315 | { |
316 | struct cpu_info *ci; | | 316 | struct cpu_info *ci; |
317 | | | 317 | |
318 | __asm volatile("mfctl %1, %0" : "=r" (ci): "i" (CR_CURCPU)); | | 318 | __asm volatile("mfctl %1, %0" : "=r" (ci): "i" (CR_CURCPU)); |
319 | | | 319 | |
320 | return ci; | | 320 | return ci; |
321 | } | | 321 | } |
322 | | | 322 | |
323 | #define curcpu() hppa_curcpu() | | 323 | #define curcpu() hppa_curcpu() |
324 | | | 324 | |
325 | #else /* MULTIPROCESSOR */ | | 325 | #else /* MULTIPROCESSOR */ |
326 | | | 326 | |
327 | #define HPPA_MAXCPUS 1 | | 327 | #define HPPA_MAXCPUS 1 |
328 | #define curcpu() (&cpus[0]) | | 328 | #define curcpu() (&cpus[0]) |
329 | #define cpu_number() 0 | | 329 | #define cpu_number() 0 |
330 | | | 330 | |
331 | static __inline struct lwp * | | 331 | static __inline struct lwp * |
332 | hppa_curlwp(void) | | 332 | hppa_curlwp(void) |
333 | { | | 333 | { |
334 | struct lwp *l; | | 334 | struct lwp *l; |
335 | | | 335 | |
336 | __asm volatile("mfctl %1, %0" : "=r" (l): "i" (CR_CURLWP)); | | 336 | __asm volatile("mfctl %1, %0" : "=r" (l): "i" (CR_CURLWP)); |
337 | | | 337 | |
338 | return l; | | 338 | return l; |
339 | } | | 339 | } |
340 | | | 340 | |
341 | #define curlwp hppa_curlwp() | | 341 | #define curlwp hppa_curlwp() |
342 | | | 342 | |
343 | #endif /* MULTIPROCESSOR */ | | 343 | #endif /* MULTIPROCESSOR */ |
344 | | | 344 | |
345 | extern struct cpu_info cpus[HPPA_MAXCPUS]; | | 345 | extern struct cpu_info cpus[HPPA_MAXCPUS]; |
346 | | | 346 | |
347 | #define DELAY(x) delay(x) | | 347 | #define DELAY(x) delay(x) |
348 | | | 348 | |
349 | static __inline paddr_t | | 349 | static __inline paddr_t |
350 | kvtop(const void *va) | | 350 | kvtop(const void *va) |
351 | { | | 351 | { |
352 | paddr_t pa; | | 352 | paddr_t pa; |
353 | | | 353 | |
354 | __asm volatile ("lpa %%r0(%1), %0" : "=r" (pa) : "r" (va)); | | 354 | __asm volatile ("lpa %%r0(%1), %0" : "=r" (pa) : "r" (va)); |
355 | return pa; | | 355 | return pa; |
356 | } | | 356 | } |
357 | | | 357 | |
358 | extern int (*cpu_desidhash)(void); | | 358 | extern int (*cpu_desidhash)(void); |
359 | | | 359 | |
360 | static __inline bool | | 360 | static __inline bool |
361 | hppa_cpu_ispa20_p(void) | | 361 | hppa_cpu_ispa20_p(void) |
362 | { | | 362 | { |
363 | | | 363 | |
364 | return (hppa_cpu_info->hci_features & HPPA_FTRS_W32B) != 0; | | 364 | return (hppa_cpu_info->hci_features & HPPA_FTRS_W32B) != 0; |
365 | } | | 365 | } |
366 | | | 366 | |
367 | static __inline bool | | 367 | static __inline bool |
368 | hppa_cpu_hastlbu_p(void) | | 368 | hppa_cpu_hastlbu_p(void) |
369 | { | | 369 | { |
370 | | | 370 | |
371 | return (hppa_cpu_info->hci_features & HPPA_FTRS_TLBU) != 0; | | 371 | return (hppa_cpu_info->hci_features & HPPA_FTRS_TLBU) != 0; |
372 | } | | 372 | } |
373 | | | 373 | |
374 | void delay(u_int); | | 374 | void delay(u_int); |
375 | void hppa_init(paddr_t, void *); | | 375 | void hppa_init(paddr_t, void *); |
376 | void trap(int, struct trapframe *); | | 376 | void trap(int, struct trapframe *); |
377 | void hppa_ras(struct lwp *); | | 377 | void hppa_ras(struct lwp *); |
378 | int spcopy(pa_space_t, const void *, pa_space_t, void *, size_t); | | 378 | int spcopy(pa_space_t, const void *, pa_space_t, void *, size_t); |
379 | int spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t, | | 379 | int spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t, |
380 | size_t *); | | 380 | size_t *); |
381 | int copy_on_fault(void); | | 381 | int copy_on_fault(void); |
382 | void lwp_trampoline(void); | | 382 | void lwp_trampoline(void); |
383 | int cpu_dumpsize(void); | | 383 | int cpu_dumpsize(void); |
384 | int cpu_dump(void); | | 384 | int cpu_dump(void); |
385 | | | 385 | |
386 | #ifdef MULTIPROCESSOR | | 386 | #ifdef MULTIPROCESSOR |
387 | void cpu_boot_secondary_processors(void); | | 387 | void cpu_boot_secondary_processors(void); |
388 | void cpu_hw_init(void); | | 388 | void cpu_hw_init(void); |
389 | void cpu_hatch(void); | | 389 | void cpu_hatch(void); |
390 | #endif | | 390 | #endif |
391 | #endif /* _KERNEL */ | | 391 | #endif /* _KERNEL */ |
392 | | | 392 | |
393 | /* | | 393 | /* |
394 | * Boot arguments stuff | | 394 | * Boot arguments stuff |
395 | */ | | 395 | */ |
396 | | | 396 | |
397 | #define BOOTARG_LEN (PAGE_SIZE) | | 397 | #define BOOTARG_LEN (PAGE_SIZE) |
398 | #define BOOTARG_OFF (0x10000) | | 398 | #define BOOTARG_OFF (0x10000) |
399 | | | 399 | |
400 | /* | | 400 | /* |
401 | * CTL_MACHDEP definitions. | | 401 | * CTL_MACHDEP definitions. |
402 | */ | | 402 | */ |
403 | #define CPU_CONSDEV 1 /* dev_t: console terminal device */ | | 403 | #define CPU_CONSDEV 1 /* dev_t: console terminal device */ |
404 | #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ | | 404 | #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ |
405 | #define CPU_LCD_BLINK 3 /* int: twiddle heartbeat LED/LCD */ | | 405 | #define CPU_LCD_BLINK 3 /* int: twiddle heartbeat LED/LCD */ |
406 | #define CPU_MAXID 4 /* number of valid machdep ids */ | | 406 | #define CPU_MAXID 4 /* number of valid machdep ids */ |
407 | | | 407 | |
408 | #ifdef _KERNEL | | 408 | #ifdef _KERNEL |
409 | #include <sys/queue.h> | | 409 | #include <sys/queue.h> |
410 | | | 410 | |
411 | struct blink_lcd { | | 411 | struct blink_lcd { |
412 | void (*bl_func)(void *, int); | | 412 | void (*bl_func)(void *, int); |
413 | void *bl_arg; | | 413 | void *bl_arg; |
414 | SLIST_ENTRY(blink_lcd) bl_next; | | 414 | SLIST_ENTRY(blink_lcd) bl_next; |
415 | }; | | 415 | }; |
416 | | | 416 | |
417 | extern void blink_lcd_register(struct blink_lcd *); | | 417 | extern void blink_lcd_register(struct blink_lcd *); |
418 | #endif /* _KERNEL */ | | 418 | #endif /* _KERNEL */ |
419 | #endif /* !_LOCORE */ | | 419 | #endif /* !_LOCORE */ |
420 | | | 420 | |
421 | #endif /* _MACHINE_CPU_H_ */ | | 421 | #endif /* _MACHINE_CPU_H_ */ |