 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.175.2.1 2012/02/23 18:37:12 riz Exp $	*/
+/*	$NetBSD: machdep.c,v 1.175.2.2 2012/03/05 20:18:01 sborrill Exp $	*/
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
  *     The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
  * Simulation Facility, NASA Ames Research Center.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Coyote Point Systems, Inc. which was written under contract to Coyote
  * Point by Jed Davis and Devon O'Dell.
 @@ -101,27 +101,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.175.2.1 2012/02/23 18:37:12 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.175.2.2 2012/03/05 20:18:01 sborrill Exp $");
 /* #define XENDEBUG_LOW  */
 #include "opt_modular.h"
 #include "opt_user_ldt.h"
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_cpureset_delay.h"
 #include "opt_mtrr.h"
 #include "opt_realmem.h"
 #include "opt_xen.h"
 #ifndef XEN
 #include "opt_physmem.h"
 @@ -404,43 +404,73 @@ cpu_startup(void)
 	cpu_init_tss(&cpu_info_primary);
 #if !defined(XEN)
 	ltr(cpu_info_primary.ci_tss_sel);
 #endif /* !defined(XEN) */
 	x86_startup();
+}
 #ifdef XEN
 /* used in assembly */
 void hypervisor_callback(void);
 void failsafe_callback(void);
 void x86_64_switch_context(struct pcb *);
 void x86_64_tls_switch(struct lwp *);
 void
 x86_64_switch_context(struct pcb *new)
+{
 	struct cpu_info *ci;
 	ci = curcpu();
 	HYPERVISOR_stack_switch(GSEL(GDATA_SEL, SEL_KPL), new->pcb_rsp0);
 	struct physdev_op physop;
 	physop.cmd = PHYSDEVOP_SET_IOPL;
 	physop.u.set_iopl.iopl = new->pcb_iopl;
 	HYPERVISOR_physdev_op(&physop);
 	if (new->pcb_fpcpu != ci) {
 void
 x86_64_tls_switch(struct lwp *l)
+{
 	struct cpu_info *ci = curcpu();
 	struct pcb *pcb = lwp_getpcb(l);
 	struct trapframe *tf = l->l_md.md_regs;
 	/*
 	 * Raise the IPL to IPL_HIGH.
 	 * FPU IPIs can alter the LWP's saved cr0.  Dropping the priority
 	 * is deferred until mi_switch(), when cpu_switchto() returns.
 	 */
 	(void)splhigh();
 	/*
 	 * If our floating point registers are on a different CPU,
 	 * set CR0_TS so we'll trap rather than reuse bogus state.
 	 */
 	if (l != ci->ci_fpcurlwp) {
 		HYPERVISOR_fpu_taskswitch(1);
+	}
-#endif
+	/* Update TLS segment pointers */
 	if (pcb->pcb_flags & PCB_COMPAT32) {
 		update_descriptor(&curcpu()->ci_gdt[GUFS_SEL], &pcb->pcb_fs);
 		update_descriptor(&curcpu()->ci_gdt[GUGS_SEL], &pcb->pcb_gs);
 		setfs(tf->tf_fs);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, tf->tf_gs);
 	} else {
 		setfs(0);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, 0);
 		HYPERVISOR_set_segment_base(SEGBASE_FS, pcb->pcb_fs);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER, pcb->pcb_gs);
+	}
+}
 #endif /* XEN */
 /*
  * Set up proc0's TSS and LDT.
  */
 void
 x86_64_proc0_tss_ldt_init(void)
+{
 	struct lwp *l = &lwp0;
 	struct pcb *pcb = lwp_getpcb(l);
 	pcb->pcb_flags = 0;
 	pcb->pcb_fs = 0;
 	pcb->pcb_gs = 0;
 @@ -2287,48 +2317,26 @@ cpu_fsgs_reload(struct lwp *l, int fssel
 		setusergs(gssel);
 #else
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, gssel);
 #endif
 		tf->tf_fs = fssel;
 		tf->tf_gs = gssel;
 		kpreempt_enable();
 	} else {
 		tf->tf_fs = fssel;
 		tf->tf_gs = gssel;
+	}
+}
 #ifdef XEN
 void x86_64_tls_switch(struct lwp *);
 void
 x86_64_tls_switch(struct lwp *l)
 	struct pcb *pcb = lwp_getpcb(l);
 	struct trapframe *tf = l->l_md.md_regs;
 	if (pcb->pcb_flags & PCB_COMPAT32) {
 		update_descriptor(&curcpu()->ci_gdt[GUFS_SEL], &pcb->pcb_fs);
 		update_descriptor(&curcpu()->ci_gdt[GUGS_SEL], &pcb->pcb_gs);
 		setfs(tf->tf_fs);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, tf->tf_gs);
 	} else {
 		setfs(0);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, 0);
 		HYPERVISOR_set_segment_base(SEGBASE_FS, pcb->pcb_fs);
 		HYPERVISOR_set_segment_base(SEGBASE_GS_USER, pcb->pcb_gs);
 #endif
 #ifdef __HAVE_DIRECT_MAP
 bool
 mm_md_direct_mapped_io(void *addr, paddr_t *paddr)
+{
 	vaddr_t va = (vaddr_t)addr;
 	if (va >= PMAP_DIRECT_BASE && va < PMAP_DIRECT_END) {
 		*paddr = PMAP_DIRECT_UNMAP(va);
 		return true;
+	}
 	return false;
+}

 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.S,v 1.95 2011/03/18 15:18:16 joerg Exp $	*/
+/*	$NetBSD: locore.S,v 1.95.10.1 2012/03/05 20:18:01 sborrill Exp $	*/
 /*
  * Copyright-o-rama!
  */
 /*
  * Copyright (c) 2006 Manuel Bouyer.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -119,27 +119,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)locore.s	7.3 (Berkeley) 5/13/91
  */
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.95 2011/03/18 15:18:16 joerg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.95.10.1 2012/03/05 20:18:01 sborrill Exp $");
 #include "opt_compat_oldboot.h"
 #include "opt_ddb.h"
 #include "opt_modular.h"
 #include "opt_multiboot.h"
 #include "opt_realmem.h"
 #include "opt_vm86.h"
 #include "opt_xen.h"
 #include "npx.h"
 #include "assym.h"
 #include "lapic.h"
 #include "ioapic.h"
 @@ -989,83 +989,89 @@ ENTRY(cpu_switchto)
 	 * non-interlocked mutex release.
 	 */
 	movl	%edi,%ecx
 	xchgl	%ecx,CPUVAR(CURLWP)
 	/* Skip the rest if returning to a pinned LWP. */
 	testl	%edx,%edx
 	jnz	4f
 #ifdef XEN
 	pushl	%edi
 	call	_C_LABEL(i386_switch_context)
 	addl	$4,%esp
-#else /* XEN */
+#else /* !XEN */
 	/* Switch ring0 esp */
 	movl	PCB_ESP0(%ebx),%eax
 	movl	%eax,CPUVAR(ESP0)
 #endif /* !XEN */
 	/* Don't bother with the rest if switching to a system process. */
 	testl	$LW_SYSTEM,L_FLAG(%edi)
 	jnz	4f
 #ifndef XEN
 	/* Restore thread-private %fs/%gs descriptors. */
 	movl	CPUVAR(GDT),%ecx
 	movl	PCB_FSD(%ebx), %eax
 	movl	PCB_FSD+4(%ebx), %edx
 	movl	%eax, (GUFS_SEL*8)(%ecx)
 	movl	%edx, (GUFS_SEL*8+4)(%ecx)
 	movl	PCB_GSD(%ebx), %eax
 	movl	PCB_GSD+4(%ebx), %edx
 	movl	%eax, (GUGS_SEL*8)(%ecx)
 	movl	%edx, (GUGS_SEL*8+4)(%ecx)
-#endif /* XEN */
+#endif /* !XEN */
 	/* Switch I/O bitmap */
 	movl	PCB_IOMAP(%ebx),%eax
 	orl	%eax,%eax
 	jnz	.Lcopy_iobitmap
 	movl	$(IOMAP_INVALOFF << 16),CPUVAR(IOBASE)
 .Liobitmap_done:
 	/* Is this process using RAS (restartable atomic sequences)? */
 	movl	L_PROC(%edi),%eax
 	cmpl	$0,P_RASLIST(%eax)
 	jne	5f
 	/*
 	 * Restore cr0 (including FPU state).  Raise the IPL to IPL_HIGH.
 	 * FPU IPIs can alter the LWP's saved cr0.  Dropping the priority
 	 * is deferred until mi_switch(), when cpu_switchto() returns.
 	 */
 :
-#ifndef XEN
+#ifdef XEN
 	pushl	%edi
 	call	_C_LABEL(i386_tls_switch)
 	addl	$4,%esp
 #else /* !XEN */
 	movl	$IPL_HIGH,CPUVAR(ILEVEL)
 	movl	PCB_CR0(%ebx),%ecx		/* has CR0_TS clear */
 	movl	%cr0,%edx
 	/*
 	 * If our floating point registers are on a different CPU,
 	 * set CR0_TS so we'll trap rather than reuse bogus state.
 	 */
 	cmpl	CPUVAR(FPCURLWP),%edi
 	je	3f
 	orl	$CR0_TS,%ecx
 	/* Reloading CR0 is very expensive - avoid if possible. */
 :	cmpl	%edx,%ecx
 	je	4f
 	movl	%ecx,%cr0
-#endif /* XEN */
+#endif /* !XEN */
 	/* Return to the new LWP, returning 'oldlwp' in %eax. */
 :	movl	%esi,%eax
 	popl	%edi
 	popl	%esi
 	popl	%ebx
 	ret
 	/* Check for restartable atomic sequences (RAS). */
 :	movl	L_MD_REGS(%edi),%ecx
 	pushl	TF_EIP(%ecx)
 	pushl	%eax
 	call	_C_LABEL(ras_lookup)

 @@ -1,14 +1,14 @@
-/*	$NetBSD: machdep.c,v 1.717.2.3 2012/02/27 20:29:36 riz Exp $	*/
+/*	$NetBSD: machdep.c,v 1.717.2.4 2012/03/05 20:18:02 sborrill Exp $	*/
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2004, 2006, 2008, 2009
  *     The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Charles M. Hannum, by Jason R. Thorpe of the Numerical Aerospace
  * Simulation Facility NASA Ames Research Center, by Julio M. Merino Vidal,
  * and by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
 @@ -57,27 +57,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)machdep.c	7.4 (Berkeley) 6/3/91
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.717.2.3 2012/02/27 20:29:36 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.717.2.4 2012/03/05 20:18:02 sborrill Exp $");
 #include "opt_beep.h"
 #include "opt_compat_ibcs2.h"
 #include "opt_compat_freebsd.h"
 #include "opt_compat_netbsd.h"
 #include "opt_compat_svr4.h"
 #include "opt_cpureset_delay.h"
 #include "opt_ddb.h"
 #include "opt_ipkdb.h"
 #include "opt_kgdb.h"
 #include "opt_mtrr.h"
 #include "opt_modular.h"
 #include "opt_multiboot.h"
 @@ -520,61 +520,84 @@ i386_proc0_tss_ldt_init(void)
 	HYPERVISOR_fpu_taskswitch(1);
 	XENPRINTF(("lwp tss sp %p ss %04x/%04x\n",
 	    (void *)pcb->pcb_esp0,
 	    GSEL(GDATA_SEL, SEL_KPL),
 	    IDXSEL(GSEL(GDATA_SEL, SEL_KPL))));
 	HYPERVISOR_stack_switch(GSEL(GDATA_SEL, SEL_KPL), pcb->pcb_esp0);
 #endif
+}
 #ifdef XEN
 /* Shim for curcpu() until %fs is ready */
 extern struct cpu_info	* (*xpq_cpu)(void);
 /* used in assembly */
 void i386_switch_context(lwp_t *);
 void i386_tls_switch(lwp_t *);
 /*
  * Switch context:
  * - honor CR0_TS in saved CR0 and request DNA exception on FPU use
  * - switch stack pointer for user->kernel transition
  */
 void
 i386_switch_context(lwp_t *l)
+{
 	struct cpu_info *ci;
 	struct pcb *pcb;
 	struct physdev_op physop;
 	pcb = lwp_getpcb(l);
 	ci = curcpu();
 	if (pcb->pcb_fpcpu != ci) {
 		HYPERVISOR_fpu_taskswitch(1);
 	HYPERVISOR_stack_switch(GSEL(GDATA_SEL, SEL_KPL), pcb->pcb_esp0);
 	physop.cmd = PHYSDEVOP_SET_IOPL;
 	physop.u.set_iopl.iopl = pcb->pcb_iopl;
 	HYPERVISOR_physdev_op(&physop);
+}
 void
 i386_tls_switch(lwp_t *l)
+{
 	struct cpu_info *ci = curcpu();
 	struct pcb *pcb = lwp_getpcb(l);
 	/*
          * Raise the IPL to IPL_HIGH.
 	 * FPU IPIs can alter the LWP's saved cr0.  Dropping the priority
 	 * is deferred until mi_switch(), when cpu_switchto() returns.
 	 */
 	(void)splhigh();
         /*
 	 * If our floating point registers are on a different CPU,
 	 * set CR0_TS so we'll trap rather than reuse bogus state.
 	 */
 	if (l != ci->ci_fpcurlwp) {
 		HYPERVISOR_fpu_taskswitch(1);
+	}
 	/* Update TLS segment pointers */
 	update_descriptor(&ci->ci_gdt[GUFS_SEL],
 			  (union descriptor *) &pcb->pcb_fsd);
 	update_descriptor(&ci->ci_gdt[GUGS_SEL],
 			  (union descriptor *) &pcb->pcb_gsd);
 	/* setup curcpu() to use %fs now */
 	/* XXX: find a way to do this, just once */
 	if (__predict_false(xpq_cpu != x86_curcpu)) {
 		xpq_cpu = x86_curcpu;
+	}
 	physop.cmd = PHYSDEVOP_SET_IOPL;
 	physop.u.set_iopl.iopl = pcb->pcb_iopl;
 	HYPERVISOR_physdev_op(&physop);
+}
 #endif /* XEN */
 #ifndef XEN
 /*
  * Set up TSS and I/O bitmap.
  */
 void
 cpu_init_tss(struct cpu_info *ci)
+{
 	struct i386tss *tss = &ci->ci_tss;
 	tss->tss_iobase = IOMAP_INVALOFF << 16;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpu.h,v 1.47.2.1 2012/02/22 18:56:47 riz Exp $	*/
+/*	$NetBSD: cpu.h,v 1.47.2.2 2012/03/05 20:18:02 sborrill Exp $	*/
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
  * All rights reserved.
+ *
  * This code is derived from software contributed to Berkeley by
  * William Jolitz.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -394,27 +394,26 @@ void 	cpu_probe(struct cpu_info *);
 void	cpu_identify(struct cpu_info *);
 /* cpu_topology.c */
 void	x86_cpu_topology(struct cpu_info *);
 /* vm_machdep.c */
 void	cpu_proc_fork(struct proc *, struct proc *);
 /* locore.s */
 struct region_descriptor;
 void	lgdt(struct region_descriptor *);
 #ifdef XEN
 void	lgdt_finish(void);
 void	i386_switch_context(lwp_t *);
 #endif
 struct pcb;
 void	savectx(struct pcb *);
 void	lwp_trampoline(void);
 void	child_trampoline(void);
 #ifdef XEN
 void	startrtclock(void);
 void	xen_delay(unsigned int);
 void	xen_initclocks(void);
 void	xen_suspendclocks(struct cpu_info *);
 void	xen_resumeclocks(struct cpu_info *);
 #else

 @@ -1,14 +1,14 @@
-/*	$NetBSD: specialreg.h,v 1.55 2011/12/15 09:38:21 abs Exp $	*/
+/*	$NetBSD: specialreg.h,v 1.55.2.1 2012/03/05 20:18:03 sborrill Exp $	*/
 /*-
  * Copyright (c) 1991 The Regents of the University of California.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -297,27 +297,27 @@
 			"\34OSXSAVE\35AVX\36F16C\37B30\40RAZ"
 #define CPUID2FAMILY(cpuid)	(((cpuid) >> 8) & 0xf)
 #define CPUID2MODEL(cpuid)	(((cpuid) >> 4) & 0xf)
 #define CPUID2STEPPING(cpuid)	((cpuid) & 0xf)
 /* Extended family and model are defined on amd64 processors */
 #define CPUID2EXTFAMILY(cpuid)	(((cpuid) >> 20) & 0xff)
 #define CPUID2EXTMODEL(cpuid)	(((cpuid) >> 16) & 0xf)
 /* Blacklists of CPUID flags - used to mask certain features */
 #ifdef XEN
 /* Not on Xen */
-#define CPUID_FEAT_BLACKLIST	 (CPUID_PGE|CPUID_PSE|CPUID_MTRR|CPUID_FXSR)
+#define CPUID_FEAT_BLACKLIST	 (CPUID_PGE|CPUID_PSE|CPUID_MTRR)
 #else
 #define CPUID_FEAT_BLACKLIST	 0
 #endif /* XEN */
 /*
  * Model-specific registers for the i386 family
  */
 #define MSR_P5_MC_ADDR		0x000	/* P5 only */
 #define MSR_P5_MC_TYPE		0x001	/* P5 only */
 #define MSR_TSC			0x010
 #define	MSR_CESR		0x011	/* P5 only (trap on P6) */
 #define	MSR_CTR0		0x012	/* P5 only (trap on P6) */
 #define	MSR_CTR1		0x013	/* P5 only (trap on P6) */

 @@ -1,14 +1,14 @@
-/*	$NetBSD: x86_xpmap.c,v 1.38.2.2 2012/02/23 21:17:25 riz Exp $	*/
+/*	$NetBSD: x86_xpmap.c,v 1.38.2.3 2012/03/05 20:18:03 sborrill Exp $	*/
 /*
  * Copyright (c) 2006 Mathieu Ropert <mro@adviseo.fr>
+ *
  * Permission to use, copy, modify, and distribute this software for any
  * purpose with or without fee is hereby granted, provided that the above
  * copyright notice and this permission notice appear in all copies.
+ *
  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 @@ -59,70 +59,64 @@
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.38.2.2 2012/02/23 21:17:25 riz Exp $");
+__KERNEL_RCSID(0, "$NetBSD: x86_xpmap.c,v 1.38.2.3 2012/03/05 20:18:03 sborrill Exp $");
 #include "opt_xen.h"
 #include "opt_ddb.h"
 #include "ksyms.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mutex.h>
 #include <sys/cpu.h>
 #include <uvm/uvm.h>
-#include <machine/pmap.h>
+#include <x86/pmap.h>
 #include <machine/gdt.h>
 #include <xen/xenfunc.h>
 #include <dev/isa/isareg.h>
 #include <machine/isa_machdep.h>
 #undef	XENDEBUG
 /* #define XENDEBUG_SYNC */
 /* #define	XENDEBUG_LOW */
 #ifdef XENDEBUG
 #define	XENPRINTF(x) printf x
 #define	XENPRINTK(x) printk x
 #define	XENPRINTK2(x) /* printk x */
 static char XBUF[256];
 #else
 #define	XENPRINTF(x)
 #define	XENPRINTK(x)
 #define	XENPRINTK2(x)
 #endif
 #define	PRINTF(x) printf x
 #define	PRINTK(x) printk x
 /* on x86_64 kernel runs in ring 3 */
 #ifdef __x86_64__
 #define PG_k PG_u
 #else
 #define PG_k 0
 #endif
 volatile shared_info_t *HYPERVISOR_shared_info;
 /* Xen requires the start_info struct to be page aligned */
 union start_info_union start_info_union __aligned(PAGE_SIZE);
 unsigned long *xpmap_phys_to_machine_mapping;
 kmutex_t pte_lock;
 void xen_failsafe_handler(void);
 #define HYPERVISOR_mmu_update_self(req, count, success_count) \
 	HYPERVISOR_mmu_update((req), (count), (success_count), DOMID_SELF)
 void
 xen_failsafe_handler(void)
 @@ -360,33 +354,34 @@ xpq_queue_invlpg(vaddr_t va)
 	xpq_flush_queue();
 	XENPRINTK2(("xpq_queue_invlpg %#" PRIxVADDR "\n", va));
 	op.cmd = MMUEXT_INVLPG_LOCAL;
 	op.arg1.linear_addr = (va & ~PAGE_MASK);
 	if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0)
 		panic("xpq_queue_invlpg");
+}
 void
 xen_mcast_invlpg(vaddr_t va, uint32_t cpumask)
+{
 	mmuext_op_t op;
 	u_long xcpumask = cpumask;
 	/* Flush pending page updates */
 	xpq_flush_queue();
 	op.cmd = MMUEXT_INVLPG_MULTI;
 	op.arg1.linear_addr = va;
-	op.arg2.vcpumask = &cpumask;
+	op.arg2.vcpumask = &xcpumask;
 	if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) {
 		panic("xpq_queue_invlpg_all");
+	}
 	return;
+}
 void
 xen_bcast_invlpg(vaddr_t va)
+{
 	mmuext_op_t op;
 @@ -398,32 +393,33 @@ xen_bcast_invlpg(vaddr_t va)
 	if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) {
 		panic("xpq_queue_invlpg_all");
+	}
 	return;
+}
 /* This is a synchronous call. */
 void
 xen_mcast_tlbflush(uint32_t cpumask)
+{
 	mmuext_op_t op;
 	u_long xcpumask = cpumask;
 	/* Flush pending page updates */
 	xpq_flush_queue();
 	op.cmd = MMUEXT_TLB_FLUSH_MULTI;
-	op.arg2.vcpumask = &cpumask;
+	op.arg2.vcpumask = &xcpumask;
 	if (HYPERVISOR_mmuext_op(&op, 1, NULL, DOMID_SELF) < 0) {
 		panic("xpq_queue_invlpg_all");
+	}
 	return;
+}
 /* This is a synchronous call. */
 void
 xen_bcast_tlbflush(void)
+{
 	mmuext_op_t op;