 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.s,v 1.338.8.1 2012/03/05 20:59:25 sborrill Exp $	*/
+/*	$NetBSD: locore.s,v 1.338.8.2 2012/03/21 16:10:21 riz Exp $	*/
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
  * Copyright (c) 1996-2002 Eduardo Horvath
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College.
  *	All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.
  *	All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
 @@ -481,27 +481,27 @@ _C_LABEL(trapbase):
 	HARDINT4U(9)			! 049 = level 9 interrupt
 	HARDINT4U(10)			! 04a = level 10 interrupt
 	HARDINT4U(11)			! 04b = level 11 interrupt
 	ZS_INTERRUPT4U			! 04c = level 12 (zs) interrupt
 	HARDINT4U(13)			! 04d = level 13 interrupt
 	HARDINT4U(14)			! 04e = level 14 interrupt
 	HARDINT4U(15)			! 04f = nonmaskable interrupt
 	UTRAP(0x050); UTRAP(0x051); UTRAP(0x052); UTRAP(0x053); UTRAP(0x054); UTRAP(0x055)
 	UTRAP(0x056); UTRAP(0x057); UTRAP(0x058); UTRAP(0x059); UTRAP(0x05a); UTRAP(0x05b)
 	UTRAP(0x05c); UTRAP(0x05d); UTRAP(0x05e); UTRAP(0x05f)
 	VTRAP(0x060, interrupt_vector); ! 060 = interrupt vector
 	TRAP(T_PA_WATCHPT)		! 061 = physical address data watchpoint
 	TRAP(T_VA_WATCHPT)		! 062 = virtual address data watchpoint
-	UTRAP(T_ECCERR)			! We'll implement this one later
+	TRAP(T_ECCERR)			! 063 = corrected ECC error
 ufast_IMMU_miss:			! 064 = fast instr access MMU miss
 	ldxa	[%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, instr_miss
 #endif
 	ldxa	[%g0] ASI_IMMU, %g1	! Load IMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag:data into %g4:%g5
 	brgez,pn %g5, instr_miss	! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bne,pn %xcc, instr_miss		! Got right tag?
 	 nop
 	CLRTT
 	stxa	%g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
 @@ -717,27 +717,27 @@ kdatafault:
 	HARDINT4U(9)			! 049 = level 9 interrupt
 	HARDINT4U(10)			! 04a = level 10 interrupt
 	HARDINT4U(11)			! 04b = level 11 interrupt
 	ZS_INTERRUPT4U			! 04c = level 12 (zs) interrupt
 	HARDINT4U(13)			! 04d = level 13 interrupt
 	HARDINT4U(14)			! 04e = level 14 interrupt
 	HARDINT4U(15)			! 04f = nonmaskable interrupt
 	UTRAP(0x050); UTRAP(0x051); UTRAP(0x052); UTRAP(0x053); UTRAP(0x054); UTRAP(0x055)
 	UTRAP(0x056); UTRAP(0x057); UTRAP(0x058); UTRAP(0x059); UTRAP(0x05a); UTRAP(0x05b)
 	UTRAP(0x05c); UTRAP(0x05d); UTRAP(0x05e); UTRAP(0x05f)
 	VTRAP(0x060, interrupt_vector); ! 060 = interrupt vector
 	TRAP(T_PA_WATCHPT)		! 061 = physical address data watchpoint
 	TRAP(T_VA_WATCHPT)		! 062 = virtual address data watchpoint
-	UTRAP(T_ECCERR)			! We'll implement this one later
+	TRAP(T_ECCERR)			! 063 = corrected ECC error
 kfast_IMMU_miss:			! 064 = fast instr access MMU miss
 	ldxa	[%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, instr_miss
 #endif
 	ldxa	[%g0] ASI_IMMU, %g1	! Load IMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag:data into %g4:%g5
 	brgez,pn %g5, instr_miss	! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bne,pn %xcc, instr_miss		! Got right tag?
 	 nop
 	CLRTT
 	stxa	%g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping

 @@ -1,14 +1,14 @@
-/*	$NetBSD: trap.c,v 1.168 2011/07/30 19:29:12 martin Exp $ */
+/*	$NetBSD: trap.c,v 1.168.8.1 2012/03/21 16:10:21 riz Exp $ */
 /*
  * Copyright (c) 1996-2002 Eduardo Horvath.  All rights reserved.
  * Copyright (c) 1996
  *	The President and Fellows of Harvard College. All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
 @@ -40,27 +40,27 @@
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  *	@(#)trap.c	8.4 (Berkeley) 9/23/93
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.168 2011/07/30 19:29:12 martin Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.168.8.1 2012/03/21 16:10:21 riz Exp $");
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
 #include "opt_compat_svr4.h"
 #include "opt_compat_netbsd32.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/pool.h>
 #include <sys/proc.h>
 #include <sys/ras.h>
 #include <sys/sa.h>
 #include <sys/savar.h>
 @@ -84,26 +84,28 @@ __KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.1
 #ifdef DDB
 #include <machine/db_machdep.h>
 #else
 #include <machine/frame.h>
 #endif
 #ifdef COMPAT_SVR4
 #include <machine/svr4_machdep.h>
 #endif
 #ifdef COMPAT_SVR4_32
 #include <machine/svr4_32_machdep.h>
 #endif
 #include <sparc64/sparc64/cache.h>
 #include <sparc/fpu/fpu_extern.h>
 #ifndef offsetof
 #define	offsetof(s, f) ((size_t)&((s *)0)->f)
 #endif
 #ifdef TRAPSTATS
 /* trapstats */
 int protfix = 0;
 int udmiss = 0;	/* Number of normal/nucleus data/text miss/protection faults */
 int udhit = 0;
 int udprot = 0;
 int utmiss = 0;
 @@ -149,26 +151,30 @@ int	trapdebug = 0/*|TDB_SYSCALL|TDB_STOP
 #endif
 #ifdef DDB
 #if 1
 #define DEBUGGER(t,f)	do { kdb_trap(t,f); } while (0)
 #else
 #define DEBUGGER(t,f)	Debugger()
 #endif
 #else
 #define DEBUGGER(t,f)
 #define Debugger()
 #endif
 struct evcnt ecc_corrected =
         EVCNT_INITIALIZER(EVCNT_TYPE_MISC,0,"ECC","corrected");
 EVCNT_ATTACH_STATIC(ecc_corrected);
 /*
  * Initial FPU state is all registers == all 1s, everything else == all 0s.
  * This makes every floating point register a signalling NaN, with sign bit
  * set, no matter how it is interpreted.  Appendix N of the Sparc V8 document
  * seems to imply that we should do this, and it does make sense.
  */
 const struct fpstate64 initfpstate __aligned(SPARC64_BLOCK_SIZE) = {
 	.fs_regs =
 	{ ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
 	  ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
 	  ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0,
 	  ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0, ~0 },
 	.fs_qsize = 0
 @@ -361,26 +367,27 @@ const char *trap_type[] = {
 };
 #define	N_TRAP_TYPES	(sizeof trap_type / sizeof *trap_type)
 void trap(struct trapframe64 *, unsigned int, vaddr_t, long);
 void data_access_fault(struct trapframe64 *, unsigned int, vaddr_t, vaddr_t,
 	vaddr_t, u_long);
 void data_access_error(struct trapframe64 *, unsigned int, vaddr_t, u_long,
 	vaddr_t, u_long);
 void text_access_fault(struct trapframe64 *tf, unsigned int type, vaddr_t pc,
 	u_long sfsr);
 void text_access_error(struct trapframe64 *, unsigned int, vaddr_t, u_long,
 	vaddr_t, u_long);
 void ecc_corrected_error(unsigned int type, vaddr_t pc);
 #ifdef DEBUG
 void print_trapframe(struct trapframe64 *);
 void
 print_trapframe(struct trapframe64 *tf)
+{
 	printf("Trapframe %p:\ttstate: %lx\tpc: %lx\tnpc: %lx\n",
 	       tf, (u_long)tf->tf_tstate, (u_long)tf->tf_pc, (u_long)tf->tf_npc);
 	printf("fault: %p\ty: %x\t",
 	       (void *)(u_long)tf->tf_fault, (int)tf->tf_y);
 	printf("pil: %d\toldpil: %d\ttt: %x\tGlobals:\n",
 @@ -530,26 +537,29 @@ trap(struct trapframe64 *tf, unsigned in
 					fplwp = NULL;
+				}
 				rstintr();
 				/* If we have an allocated fpstate, load it */
 				if (newfplwp->l_md.md_fpstate != NULL) {
 					fplwp = newfplwp;
 					loadfpstate(fplwp->l_md.md_fpstate);
 				} else
 					fplwp = NULL;
+			}
 			/* Enable the FPU */
 			tf->tf_tstate |= TSTATE_PEF;
 			return;
 		} else if (type == T_ECCERR) {
 			ecc_corrected_error(type, pc);
 			return;
+		}
 		goto dopanic;
+	}
 	l = curlwp;
 	p = l->l_proc;
 	LWP_CACHE_CREDS(l, p);
 	sticks = p->p_sticks;
 	pcb = lwp_getpcb(l);
 	l->l_md.md_tf = tf;	/* for ptrace/signals */
 	sig = 0;
 	switch (type) {
 @@ -845,26 +855,29 @@ badtrap:
 		l->l_proc->p_md.md_flags |= MDP_FIXALIGN;
 		ADVANCE;
 		break;
 	case T_INTOF:
 		uprintf("T_INTOF\n");		/* XXX */
 		ADVANCE;
 		sig = SIGFPE;
 		KSI_INIT_TRAP(&ksi);
 		ksi.ksi_trap = type;
 		ksi.ksi_code = FPE_INTOVF;
 		ksi.ksi_addr = (void *)pc;
 		break;
 	case T_ECCERR:
 		ecc_corrected_error(type, pc);
 		break;
+	}
 	if (sig != 0) {
 		ksi.ksi_signo = sig;
 		trapsignal(l, &ksi);
+	}
 	userret(l, pc, sticks);
 	share_fpu(l, tf);
 #undef ADVANCE
 #ifdef DEBUG
 	if (trapdebug & (TDB_FOLLOW | TDB_TRAP)) {
 		printf("trap: done\n");
 		/* if (type != T_BREAKPOINT) Debugger(); */
+	}
 @@ -1612,13 +1625,58 @@ text_access_error(struct trapframe64 *tf
 out:
 	if ((tstate & TSTATE_PRIV) == 0) {
 		userret(l, pc, sticks);
 		share_fpu(l, tf);
+	}
 #ifdef DEBUG
 	if (trapdebug & (TDB_TXTFLT | TDB_FOLLOW))
 		printf("text_access_error: done\n");
 	if (trapdebug & TDB_FRAME) {
 		print_trapframe(tf);
+	}
 #endif
+}
 /*
  * Handle an ECC corrected event.
  */
 void
 ecc_corrected_error(unsigned int type, vaddr_t pc)
+{
 	uint64_t eeer, afar, afsr;
 	char buf[128];
 	int s;
 	/* Clear the error */
 	eeer = ldxa(0, ASI_ERROR_EN_REG);
 	s = intr_disable();
 	stxa(0, ASI_ERROR_EN_REG,
 	    eeer & ~(P_EER_NCEEN | P_EER_CEEN));
 	membar_Sync();
 	intr_restore(s);
 	/* Flush the caches in order ensure no corrupt data got installed. */
 	blast_dcache();
 	blast_icache();
 #if 0
 	/* Ensure the caches are still turned on (should be). */
 	cache_enable(PCPU_GET(impl));
 #endif
 	/* Grab the current AFSR/AFAR, and clear the error from the AFSR. */
 	afar = ldxa(0, ASI_AFAR);
 	afsr = ldxa(0, ASI_AFSR);
 	s = intr_disable();
 	stxa(0, ASI_AFSR, ldxa(0, ASI_AFSR));
 	membar_Sync();
 	intr_restore(s);
 	ecc_corrected.ev_count++;
 	snprintb(buf, sizeof(buf), AFSR_BITS, afsr);
 	printf("corrected ECC error: pc %p afsr %"PRIx64" (%s) addr %"PRIx64"\n", (void *)pc, afsr, buf, afar);
 	/* Turn (non-)correctable error reporting back on. */
 	s = intr_disable();
 	stxa(0, ASI_ERROR_EN_REG, eeer);
 	membar_Sync();
 	intr_restore(s);
+}