| @@ -1,14 +1,14 @@ | | | @@ -1,14 +1,14 @@ |
1 | /* $NetBSD: ohci_pci.c,v 1.48 2012/01/30 19:41:22 drochner Exp $ */ | | 1 | /* $NetBSD: ohci_pci.c,v 1.49 2012/04/05 04:04:05 macallan Exp $ */ |
2 | | | 2 | |
3 | /* | | 3 | /* |
4 | * Copyright (c) 1998 The NetBSD Foundation, Inc. | | 4 | * Copyright (c) 1998 The NetBSD Foundation, Inc. |
5 | * All rights reserved. | | 5 | * All rights reserved. |
6 | * | | 6 | * |
7 | * This code is derived from software contributed to The NetBSD Foundation | | 7 | * This code is derived from software contributed to The NetBSD Foundation |
8 | * by Lennart Augustsson (lennart@augustsson.net) at | | 8 | * by Lennart Augustsson (lennart@augustsson.net) at |
9 | * Carlstedt Research & Technology. | | 9 | * Carlstedt Research & Technology. |
10 | * | | 10 | * |
11 | * Redistribution and use in source and binary forms, with or without | | 11 | * Redistribution and use in source and binary forms, with or without |
12 | * modification, are permitted provided that the following conditions | | 12 | * modification, are permitted provided that the following conditions |
13 | * are met: | | 13 | * are met: |
14 | * 1. Redistributions of source code must retain the above copyright | | 14 | * 1. Redistributions of source code must retain the above copyright |
| @@ -21,27 +21,27 @@ | | | @@ -21,27 +21,27 @@ |
21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | | 21 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR | | 22 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS | | 23 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | | 24 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | | 25 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | | 26 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | | 27 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | | 28 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | | 29 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | * POSSIBILITY OF SUCH DAMAGE. | | 30 | * POSSIBILITY OF SUCH DAMAGE. |
31 | */ | | 31 | */ |
32 | | | 32 | |
33 | #include <sys/cdefs.h> | | 33 | #include <sys/cdefs.h> |
34 | __KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.48 2012/01/30 19:41:22 drochner Exp $"); | | 34 | __KERNEL_RCSID(0, "$NetBSD: ohci_pci.c,v 1.49 2012/04/05 04:04:05 macallan Exp $"); |
35 | | | 35 | |
36 | #include "ehci.h" | | 36 | #include "ehci.h" |
37 | | | 37 | |
38 | #include <sys/param.h> | | 38 | #include <sys/param.h> |
39 | #include <sys/systm.h> | | 39 | #include <sys/systm.h> |
40 | #include <sys/kernel.h> | | 40 | #include <sys/kernel.h> |
41 | #include <sys/device.h> | | 41 | #include <sys/device.h> |
42 | #include <sys/proc.h> | | 42 | #include <sys/proc.h> |
43 | #include <sys/queue.h> | | 43 | #include <sys/queue.h> |
44 | | | 44 | |
45 | #include <sys/bus.h> | | 45 | #include <sys/bus.h> |
46 | | | 46 | |
47 | #include <dev/pci/pcivar.h> | | 47 | #include <dev/pci/pcivar.h> |
| @@ -86,44 +86,53 @@ ohci_pci_attach(device_t parent, device_ | | | @@ -86,44 +86,53 @@ ohci_pci_attach(device_t parent, device_ |
86 | pci_chipset_tag_t pc = pa->pa_pc; | | 86 | pci_chipset_tag_t pc = pa->pa_pc; |
87 | pcitag_t tag = pa->pa_tag; | | 87 | pcitag_t tag = pa->pa_tag; |
88 | char const *intrstr; | | 88 | char const *intrstr; |
89 | pci_intr_handle_t ih; | | 89 | pci_intr_handle_t ih; |
90 | pcireg_t csr; | | 90 | pcireg_t csr; |
91 | usbd_status r; | | 91 | usbd_status r; |
92 | const char *vendor; | | 92 | const char *vendor; |
93 | | | 93 | |
94 | sc->sc.sc_dev = self; | | 94 | sc->sc.sc_dev = self; |
95 | sc->sc.sc_bus.hci_private = sc; | | 95 | sc->sc.sc_bus.hci_private = sc; |
96 | | | 96 | |
97 | pci_aprint_devinfo(pa, "USB Controller"); | | 97 | pci_aprint_devinfo(pa, "USB Controller"); |
98 | | | 98 | |
| | | 99 | /* check if memory space access is enabled */ |
| | | 100 | csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); |
| | | 101 | #ifdef DEBUG |
| | | 102 | printf("csr: %08x\n", csr); |
| | | 103 | #endif |
| | | 104 | if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) { |
| | | 105 | aprint_error_dev(self, "memory access is disabled\n"); |
| | | 106 | return; |
| | | 107 | } |
| | | 108 | |
99 | /* Map I/O registers */ | | 109 | /* Map I/O registers */ |
100 | if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, | | 110 | if (pci_mapreg_map(pa, PCI_CBMEM, PCI_MAPREG_TYPE_MEM, 0, |
101 | &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { | | 111 | &sc->sc.iot, &sc->sc.ioh, NULL, &sc->sc.sc_size)) { |
102 | sc->sc.sc_size = 0; | | 112 | sc->sc.sc_size = 0; |
103 | aprint_error_dev(self, "can't map mem space\n"); | | 113 | aprint_error_dev(self, "can't map mem space\n"); |
104 | return; | | 114 | return; |
105 | } | | 115 | } |
106 | | | 116 | |
107 | /* Disable interrupts, so we don't get any spurious ones. */ | | 117 | /* Disable interrupts, so we don't get any spurious ones. */ |
108 | bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, | | 118 | bus_space_write_4(sc->sc.iot, sc->sc.ioh, OHCI_INTERRUPT_DISABLE, |
109 | OHCI_ALL_INTRS); | | 119 | OHCI_ALL_INTRS); |
110 | | | 120 | |
111 | sc->sc_pc = pc; | | 121 | sc->sc_pc = pc; |
112 | sc->sc_tag = tag; | | 122 | sc->sc_tag = tag; |
113 | sc->sc.sc_bus.dmatag = pa->pa_dmat; | | 123 | sc->sc.sc_bus.dmatag = pa->pa_dmat; |
114 | | | 124 | |
115 | /* Enable the device. */ | | 125 | /* Enable the device. */ |
116 | csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); | | | |
117 | pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, | | 126 | pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, |
118 | csr | PCI_COMMAND_MASTER_ENABLE); | | 127 | csr | PCI_COMMAND_MASTER_ENABLE); |
119 | | | 128 | |
120 | /* Map and establish the interrupt. */ | | 129 | /* Map and establish the interrupt. */ |
121 | if (pci_intr_map(pa, &ih)) { | | 130 | if (pci_intr_map(pa, &ih)) { |
122 | aprint_error_dev(self, "couldn't map interrupt\n"); | | 131 | aprint_error_dev(self, "couldn't map interrupt\n"); |
123 | goto fail; | | 132 | goto fail; |
124 | } | | 133 | } |
125 | | | 134 | |
126 | /* | | 135 | /* |
127 | * Allocate IRQ | | 136 | * Allocate IRQ |
128 | */ | | 137 | */ |
129 | intrstr = pci_intr_string(pc, ih); | | 138 | intrstr = pci_intr_string(pc, ih); |