 @@ -1,14 +1,14 @@
-/*	$NetBSD: locore.S,v 1.58 2012/01/03 06:11:21 skrll Exp $	*/
+/*	$NetBSD: locore.S,v 1.59 2012/04/05 19:42:13 skrll Exp $	*/
 /*	$OpenBSD: locore.S,v 1.158 2008/07/28 19:08:46 miod Exp $	*/
 /*
  * Copyright (c) 1998-2004 Michael Shalayeff
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -69,29 +69,26 @@
 #include <machine/psl.h>
 #include <machine/trap.h>
 #include <machine/iomod.h>
 #include <machine/pdc.h>
 #include <machine/intr.h>
 #include <machine/frame.h>
 #include <machine/reg.h>
 #include "assym.h"
 /* Some aliases for the macros in assym.h. */
 #define	TRAPFRAME_SIZEOF	trapframe_SIZEOF
 #define	ccr	cr10
 #define	rctr	cr0
 /*
  * Very crude debugging macros that write to com1.
  */
 #if 1
 #define	COM1_TX_REG	(0xffd00000 + 0x5000 + 0x800)
 #else
 #define	COM1_TX_REG	(0xf0823000 + 0x800)
 #endif
 #define _DEBUG_PUTCHAR(reg1, reg2)		! \
 	ldil	L%COM1_TX_REG, %reg1		! \
 	stb	%reg2, R%COM1_TX_REG(%sr1, %reg1) ! \
 	ldil	L%10000000, %reg1		! \
 @@ -234,27 +231,27 @@ L$start_zero_tf:
 	ldil	L%lwp0, %t2
 	stw	%t3, R%lwp0+L_PCB(%t2)		/* XXXuvm_lwp_getuarea */
 	ldo	NBPG(%t3), %t1
 	stw	%t1, R%lwp0+L_MD_REGS(%t2)
 	ldil	L%TFF_LAST, %t1
 	stw	%t1, TF_FLAGS-TRAPFRAME_SIZEOF(%sp)
 	stw	%t3, TF_CR30-TRAPFRAME_SIZEOF(%sp)
 	/*
 	 * disable all coprocessors
 	 */
-	mtctl	%r0, %ccr
+	mtctl	%r0, CR_CCR
 #ifdef MULTIPROCESSOR
 #define	PZ_MEM_RENDEZ		0x10
 #define	PZ_MEM_RENDEZ_HI	0x28
 	/* Setup SMP rendezvous address. */
 	ldil	L%hw_cpu_spinup_trampoline, %r1
 	ldo	R%hw_cpu_spinup_trampoline(%r1), %r1
 	stw	%r1, PZ_MEM_RENDEZ(%r0)
 	stw	%r0, PZ_MEM_RENDEZ_HI(%r0)
 #endif
 @@ -436,27 +433,27 @@ LEAF_ENTRY_NOPROFILE(hw_cpu_spinup_tramp
 #endif
 	mtsp	%r0, %sr0
 	mtsp	%r0, %sr1
 	mtsp	%r0, %sr2
 	mtsp	%r0, %sr3
 	mtsp	%r0, %sr4
 	mtsp	%r0, %sr5
 	mtsp	%r0, %sr6
 	mtsp	%r0, %sr7
 	/*
 	 * disable all coprocessors
 	 */
-	mtctl   %r0, %ccr
+	mtctl   %r0, CR_CCR
 	/*
 	 * to keep the spl() routines consistent we need to put the correct
 	 * spl level into eiem, and reset any pending interrupts
 	 */
 	ldi	-1, %r1
 	mtctl	%r0, %eiem		/* disable interrupts */
 	mtctl	%r1, %eirr
 	/*
 	 * load address of interrupt vector table
 	 */
 	ldil	L%ivaaddr, %t2
 @@ -1044,33 +1041,33 @@ noras:
 	 */
 ALTENTRY(hppa_fpu_nop1)
 	b,n	switch_return
 	/*
 	 * We do have a hardware FPU.  If the LWP
 	 * that we just switched to has its state in the
 	 * FPU, enable the FPU, else disable it, so if
 	 * the LWP does try to use the coprocessor
 	 * we'll get an assist emulation trap to swap
 	 * states.
 	 */
 	GET_CURCPU(%t1)
-	mfctl	%ccr, %r1
+	mfctl	CR_CCR, %r1
 	mfctl	CR_FPPADDR, %t2
 	ldw	CI_FPU_STATE(%t1), %t1
 	depi	0, 25, 2, %r1		; disables the FPU
 	comb,<>,n %t1, %t2, 0		; nullify if LWPs different
 	depi	3, 25, 2, %r1		; enables the FPU
-	mtctl	%r1, %ccr
+	mtctl	%r1, CR_CCR
 switch_return:
 	copy	%arg0, %ret0
 	ldw	HPPA_FRAME_CRP(%r3), %rp
 	bv	0(%rp)
 	ldwm	-(HPPA_FRAME_SIZE+16*4)(%sp), %r3
 EXIT(cpu_switchto)
 /*
  * This is the first code run in a new LWP after
  * cpu_switchto() has switched to it for the first time.
+ *

 @@ -1,14 +1,14 @@
-/*	$NetBSD: trap.S,v 1.63 2012/02/26 08:28:57 skrll Exp $	*/
+/*	$NetBSD: trap.S,v 1.64 2012/04/05 19:42:14 skrll Exp $	*/
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Matthew Fredette.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
 @@ -503,27 +503,27 @@ syscall_return:
 #if pbably_not_worth_it
 	ldw	TF_CR12(%sr3, %t3), %t1
 	ldw	TF_CR13(%sr3, %t3), %t2
 	mtctl	%t1, %pidr3
 	mtctl	%t2, %pidr4
 #endif
 	ldw	TF_CR27(%sr3, %t3), %t1
 	ldw	TF_CR30(%sr3, %t3), %t2
 	mtctl	%t1, CR_TLS
 	mtctl	%t2, CR_FPPADDR
 	ldw	TF_CR0(%sr3, %t3), %t1
-	mtctl	%t1, %rctr
+	mtctl	%t1, CR_RCTR
 	GET_CURCPU_SPACE(%sr3, %t3)
 	/*
 	 * Clear the system mask, this puts us back into physical mode.  Reload
 	 * the trapframe pointer with the correspondent PA value.  %sp will be
 	 * left in virtual until restored from trapframe, since we don't use it
 	 * anyway.
 	 */
 	ssm	0, %r0
 	ldo	CI_TRAPSAVE(%t3), %t3
 	nop ! nop ! nop ! nop ! nop ! nop
 	rsm	RESET_PSW, %r0
 @@ -929,27 +929,27 @@ LEAF_ENTRY_NOPROFILE(TLABEL(emu))
 	/*
 	 * As an optimization, hppa_fpu_bootstrap replaces this branch inst-
 	 * ruction with a nop if there is a hardware FPU.
+	 *
 	 * Otherwise, this is the branch to emulate an FPU coprocessor.
 	 */
 ALTENTRY(hppa_fpu_nop0)
 	b,n	L$emulate_fpu
 	/*
 	 * We have a hardware FPU.  If it is enabled,  branch to emulate the
 	 * instruction.
 	 */
-	mfctl	%ccr, %arg0
+	mfctl	CR_CCR, %arg0
 	extru,= %arg0, 25, 2, %r1
 	b,n	L$emulate_fpu
 	/*
 	 * The hardware FPU is disabled, so we need to swap in the FPU state of
 	 * the LWP whose uspace physical address in CR_UPADDR.  We may also
 	 * need to swap out the FPU state of any LWP whose uspace physical
 	 * address is in curcpu()->ci_fpu_state.
 	 */
 	/*
 	 * So far, the CTRAP() macro has saved %r1 in %tr7, and the dispatching
 	 * above has saved %arg0 in tr2.  Save the other registers that we want
 @@ -1045,30 +1045,30 @@ ALTENTRY(hppa_fpu_swap)
 	/*
 	 * Note that this function must work in physical mode as well as virtual
 	 * mode, because it can be called by a trap handler.  This also further
 	 * restricts the registers we can use.  We can only use %arg0, %arg1,
 	 * and %r1.
 	 */
 	/*
 	 * Assuming that out and in aren't both NULL, we will have to run co-
 	 * processor instructions, so we'd better enable it.
+	 *
 	 * Also, branch if there's no FPU state to swap out.
 	 */
-	mfctl	%ccr, %r1
+	mfctl	CR_CCR, %r1
 	depi	3, 25, 2, %r1
 	comb,=	%r0, %arg0, L$fpu_swap_in
-	mtctl	%r1, %ccr
+	mtctl	%r1,CR_CCR
 	/*
 	 * Swap out the current FPU state.
 	 */
 	fstds,ma %fr0 , 8(%arg0)	/* fr0 must be saved first */
 	fstds,ma %fr1 , 8(%arg0)
 	fstds,ma %fr2 , 8(%arg0)
 	fstds,ma %fr3 , 8(%arg0)
 	fstds,ma %fr4 , 8(%arg0)
 	fstds,ma %fr5 , 8(%arg0)
 	fstds,ma %fr6 , 8(%arg0)
 	fstds,ma %fr7 , 8(%arg0)
 	fstds,ma %fr8 , 8(%arg0)
 @@ -1176,30 +1176,30 @@ L$fpu_swap_in:
 L$fpu_swap_done:
 	/* Increment the switch count and return. */
 	ldil	L%fpu_csw, %r1
 	ldw	R%fpu_csw(%r1), %arg0
 	ldo	1(%arg0), %arg0
 	bv	%r0(%rp)
 	stw	%arg0, R%fpu_csw(%r1)
 L$fpu_no_swap_in:
 	/* We didn't swap any FPU state in, so disable the FPU. */
-	mfctl	%ccr, %r1
+	mfctl	CR_CCR, %r1
 	depi	0, 25, 2, %r1
 	b	L$fpu_swap_done
-	mtctl	%r1, %ccr
+	mtctl	%r1, CR_CCR
 EXIT(hppa_fpu_swapout)
 	/* Construct the virtual address tag. */
 	/* NB: it is legal for off and t to be the same. */
 #define VTAG(sp,off,t) \
 	shd	%r0, off, 1, t		/* t[1..15] = off[0..14] */	! \
 	dep	sp, 31, 16, t		/* put in the space id */	! \
 	depi	1, 0, 1, t		/* and set the valid bit */
 #if 0
 	BSS(dtlb_c, 8)
 	BSS(tlbd_c, 8)
 	BSS(itlb_c, 8)
 @@ -2043,47 +2043,47 @@ L$trap_have_stack:
 	mfctl	%isr, %t1
 	mfctl	%ior, %t2
 	stw	%t1, CI_TRAPSAVE + TF_CR20(%t3)	/* use ,bc */
 	stw	%t2, CI_TRAPSAVE + TF_CR21(%t3)
 	/* save the interruption instruction register */
 	mfctl	%iir, %t2
 	stw	%t2, CI_TRAPSAVE + TF_CR19(%t3)
 	/* save the trap type and flags */
 	stw	%r1, CI_TRAPSAVE + TF_FLAGS(%t3)
 	/* gotta get it before R is up */
-	mfctl	%rctr, %t1
+	mfctl	CR_RCTR, %t1
 	copy	%sp, %t3
 	ldo	HPPA_FRAME_SIZE+TRAPFRAME_SIZEOF(%sp), %sp
 #if defined(DDB) || defined(KGDB)
 	/*
 	 * Match the offset from %sp for the trapframe with syscall_entry
 	 */
 	ldo	HPPA_FRAME_MAXARGS+HPPA_FRAME_SIZE-1(%sp),%sp
 	depi	0, 31, 6, %sp
 #endif
 	rfir
 	nop ! nop ! nop ! nop ! nop ! nop ! nop ! nop
 trapnowvirt:
 	/*
 	 * %t3 contains the virtual address of the trapframe
 	 * %sp is loaded w/ the right VA (we did not need it being physical)
 	 */
-	mfctl	%ccr, %t2
+	mfctl	CR_CCR, %t2
 	stw	%t1, TF_CR0(%sr3, %t3)
 	stw	%t2, TF_CR10(%sr3, %t3)
 	mfsp	%sr0, %t1
 	mfsp	%sr1, %t2
 	stw	%t1, TF_SR0(%sr3, %t3)
 	stw	%t2, TF_SR1(%sr3, %t3)
 	mfsp	%sr2, %t1
 	mfsp	%sr4, %t2
 	stw	%t1, TF_SR2(%sr3, %t3)
 	stw	%t2, TF_SR4(%sr3, %t3)