Sun Sep 16 07:26:31 2012 UTC ()
Fix gcc bugid 51408 for arm.


(msaitoh)
diff -r1.3 -r1.4 src/external/gpl3/gcc/dist/gcc/ChangeLog
diff -r1.1.1.1 -r1.2 src/external/gpl3/gcc/dist/gcc/config/arm/arm.md
cvs diff -r1.3 -r1.4 src/external/gpl3/gcc/dist/gcc/ChangeLog (switch to unified diff)

--- src/external/gpl3/gcc/dist/gcc/ChangeLog 2012/06/17 13:43:30 1.3
+++ src/external/gpl3/gcc/dist/gcc/ChangeLog 2012/09/16 07:26:30 1.4
@@ -1,999 +1,1009 @@ @@ -1,999 +1,1009 @@
 12011-12-09 Kazu Hirata <kazu@codesourcery.com>
 2
 3 Backport from mainline:
 4
 5 2011-12-05 Kazu Hirata <kazu@codesourcery.com>
 6
 7 PR target/51408
 8 * config/arm/arm.md (*minmax_arithsi): Always require the else
 9 clause in the MINUS case.
 10
12011-10-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 112011-10-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2 12
3 PR target/50691 13 PR target/50691
4 * config/pa/pa.c (emit_move_sequence): Legitimize TLS symbol references. 14 * config/pa/pa.c (emit_move_sequence): Legitimize TLS symbol references.
5 * config/pa/pa.h (LEGITIMATE_CONSTANT_P): Return false for 15 * config/pa/pa.h (LEGITIMATE_CONSTANT_P): Return false for
6 TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC symbol references. 16 TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC symbol references.
7 17
82011-06-17 Hans-Peter Nilsson <hp@axis.com> 182011-06-17 Hans-Peter Nilsson <hp@axis.com>
9 19
10 Backport from mainline 20 Backport from mainline
11 2011-06-17 Hans-Peter Nilsson <hp@axis.com> 21 2011-06-17 Hans-Peter Nilsson <hp@axis.com>
12 22
13 PR rtl-optimization/48542 23 PR rtl-optimization/48542
14 * reload.c (find_equiv_reg): Stop looking when finding a 24 * reload.c (find_equiv_reg): Stop looking when finding a
15 setjmp-type call. 25 setjmp-type call.
16 * reload1.c (reload_as_needed): Invalidate all reload 26 * reload1.c (reload_as_needed): Invalidate all reload
17 registers when crossing a setjmp-type call. 27 registers when crossing a setjmp-type call.
18 28
192011-04-28 Release Manager 292011-04-28 Release Manager
20 30
21 * GCC 4.5.3 released. 31 * GCC 4.5.3 released.
22 32
232011-04-21 Richard Guenther <rguenther@suse.de> 332011-04-21 Richard Guenther <rguenther@suse.de>
24 34
25 PR middle-end/48712 35 PR middle-end/48712
26 Backport from 4.6 branch 36 Backport from 4.6 branch
27 2011-03-07 Zdenek Dvorak <ook@ucw.cz> 37 2011-03-07 Zdenek Dvorak <ook@ucw.cz>
28 38
29 PR bootstrap/48000 39 PR bootstrap/48000
30 * cfgloopmanip.c (fix_bb_placements): Return immediately 40 * cfgloopmanip.c (fix_bb_placements): Return immediately
31 if FROM is BASE_LOOP's header. 41 if FROM is BASE_LOOP's header.
32 42
332011-04-20 Richard Guenther <rguenther@suse.de> 432011-04-20 Richard Guenther <rguenther@suse.de>
34 44
35 Backport from 4.6 branch 45 Backport from 4.6 branch
36 2011-04-19 Bernd Schmidt <bernds@codesourcery.com> 46 2011-04-19 Bernd Schmidt <bernds@codesourcery.com>
37 47
38 PR fortran/47976 48 PR fortran/47976
39 * reload1.c (inc_for_reload): Return void. All callers changed. 49 * reload1.c (inc_for_reload): Return void. All callers changed.
40 (emit_input_reload_insns): Don't try to delete previous output 50 (emit_input_reload_insns): Don't try to delete previous output
41 reloads to a register, or record spill_reg_store for autoincs. 51 reloads to a register, or record spill_reg_store for autoincs.
42 52
432011-04-19 Richard Guenther <rguenther@suse.de> 532011-04-19 Richard Guenther <rguenther@suse.de>
44 54
45 Backported from 4.6 branch 55 Backported from 4.6 branch
46 2011-03-29 Jakub Jelinek <jakub@redhat.com> 56 2011-03-29 Jakub Jelinek <jakub@redhat.com>
47 57
48 PR preprocessor/48248 58 PR preprocessor/48248
49 * c-ppoutput.c (print): Add src_file field. 59 * c-ppoutput.c (print): Add src_file field.
50 (init_pp_output): Initialize it. 60 (init_pp_output): Initialize it.
51 (maybe_print_line): Don't optimize by adding up to 8 newlines 61 (maybe_print_line): Don't optimize by adding up to 8 newlines
52 if map->to_file and print.src_file are different file. 62 if map->to_file and print.src_file are different file.
53 (print_line): Update print.src_file. 63 (print_line): Update print.src_file.
54 64
55 2011-04-18 Richard Guenther <rguenther@suse.de> 65 2011-04-18 Richard Guenther <rguenther@suse.de>
56 66
57 PR preprocessor/48248 67 PR preprocessor/48248
58 * c-ppoutput.c (maybe_print_line): Avoid changing -P behavior. 68 * c-ppoutput.c (maybe_print_line): Avoid changing -P behavior.
59 69
602011-04-19 Richard Guenther <rguenther@suse.de> 702011-04-19 Richard Guenther <rguenther@suse.de>
61 71
62 PR tree-optimization/46188 72 PR tree-optimization/46188
63 Backported from 4.6 branch 73 Backported from 4.6 branch
64 2010-05-26 Jan Hubicka <jh@suse.cz> 74 2010-05-26 Jan Hubicka <jh@suse.cz>
65 75
66 * cgraphunit.c (clone_of_p): Remove. 76 * cgraphunit.c (clone_of_p): Remove.
67 (verify_cgraph_node): Do not verify clones. 77 (verify_cgraph_node): Do not verify clones.
68 (cgraph_materialize_all_clones): Do no redirection here. 78 (cgraph_materialize_all_clones): Do no redirection here.
69 * ipa-inline.c (inline_transform): Do redirection here. 79 * ipa-inline.c (inline_transform): Do redirection here.
70 80
712011-04-18 Eric Botcazou <ebotcazou@adacore.com> 812011-04-18 Eric Botcazou <ebotcazou@adacore.com>
72 82
73 * dwarf2out.c (is_redundant_typedef): Add 'inline' to prototype. 83 * dwarf2out.c (is_redundant_typedef): Add 'inline' to prototype.
74 84
752011-04-18 Richard Guenther <rguenther@suse.de> 852011-04-18 Richard Guenther <rguenther@suse.de>
76 86
77 Backported from 4.6 branch 87 Backported from 4.6 branch
78 2011-01-19 Jakub Jelinek <jakub@redhat.com> 88 2011-01-19 Jakub Jelinek <jakub@redhat.com>
79 89
80 PR tree-optimization/47290 90 PR tree-optimization/47290
81 * tree-eh.c (infinite_empty_loop_p): New function. 91 * tree-eh.c (infinite_empty_loop_p): New function.
82 (cleanup_empty_eh): Use it. 92 (cleanup_empty_eh): Use it.
83 93
84 2010-05-29 Jan Hubicka <jh@suse.cz> 94 2010-05-29 Jan Hubicka <jh@suse.cz>
85 95
86 PR tree-optimization/46364 96 PR tree-optimization/46364
87 * cgraphunit.c (cgraph_materialize_clone): Only remove calles, refs 97 * cgraphunit.c (cgraph_materialize_clone): Only remove calles, refs
88 and body; 98 and body;
89 not the whole node for masters of materialized clones. 99 not the whole node for masters of materialized clones.
90 100
912011-04-18 Richard Guenther <rguenther@suse.de> 1012011-04-18 Richard Guenther <rguenther@suse.de>
92 102
93 Backported from 4.6 branch 103 Backported from 4.6 branch
94 2011-03-05 Zdenek Dvorak <ook@ucw.cz> 104 2011-03-05 Zdenek Dvorak <ook@ucw.cz>
95 105
96 PR rtl-optimization/47899 106 PR rtl-optimization/47899
97 * cfgloopmanip.c (fix_bb_placements): Fix first argument 107 * cfgloopmanip.c (fix_bb_placements): Fix first argument
98 to flow_loop_nested_p when moving the loop upward. 108 to flow_loop_nested_p when moving the loop upward.
99 109
100 2011-03-15 Richard Guenther <rguenther@suse.de> 110 2011-03-15 Richard Guenther <rguenther@suse.de>
101  111
102 PR middle-end/48031 112 PR middle-end/48031
103 * fold-const.c (fold_indirect_ref_1): Do not create new variable-sized 113 * fold-const.c (fold_indirect_ref_1): Do not create new variable-sized
104 or variable-indexed array accesses when in gimple form. 114 or variable-indexed array accesses when in gimple form.
105 115
1062011-04-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 1162011-04-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
107 117
108 * config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of 118 * config/pa/pa.h (REGISTER_MOVE_COST): Increase to 18 cost of
109 move from floating point to shift amount register. 119 move from floating point to shift amount register.
110 120
111 Backport from mainline: 121 Backport from mainline:
112 2011-04-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 122 2011-04-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
113 123
114 PR target/48366 124 PR target/48366
115 * config/pa/pa.c (emit_move_sequence): Remove secondary reload 125 * config/pa/pa.c (emit_move_sequence): Remove secondary reload
116 support for floating point to shift amount amount register copies. 126 support for floating point to shift amount amount register copies.
117 (pa_secondary_reload): Return GENERAL_REGS for floating point/shift 127 (pa_secondary_reload): Return GENERAL_REGS for floating point/shift
118 amount register copies. 128 amount register copies.
119 * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount 129 * config/pa/pa32-regs.h (HARD_REGNO_MODE_OK): For shift amount
120 register, return false if mode isn't a scalar integer mode. 130 register, return false if mode isn't a scalar integer mode.
121 * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise. 131 * config/pa/pa64-regs.h (HARD_REGNO_MODE_OK): Likewise.
122 132
1232011-04-16 Jakub Jelinek <jakub@redhat.com> 1332011-04-16 Jakub Jelinek <jakub@redhat.com>
124 134
125 Backported from 4.6 branch 135 Backported from 4.6 branch
126 2011-04-15 Jakub Jelinek <jakub@redhat.com> 136 2011-04-15 Jakub Jelinek <jakub@redhat.com>
127 137
128 PR target/48605 138 PR target/48605
129 * config/i386/sse.md (avx_insertps, sse4_1_insertps): If operands[2] 139 * config/i386/sse.md (avx_insertps, sse4_1_insertps): If operands[2]
130 is a MEM, offset it as needed based on top 2 bits in operands[3], 140 is a MEM, offset it as needed based on top 2 bits in operands[3],
131 change MEM mode to SFmode and mask those 2 bits away from operands[3]. 141 change MEM mode to SFmode and mask those 2 bits away from operands[3].
132 142
1332011-04-13 Nick Clifton <nickc@redhat.com> 1432011-04-13 Nick Clifton <nickc@redhat.com>
134 144
135 * config/rx/rx.md (movmemsi): Do not use this pattern when 145 * config/rx/rx.md (movmemsi): Do not use this pattern when
136 volatile pointers are involved. 146 volatile pointers are involved.
137 147
1382011-04-12 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 1482011-04-12 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
139 149
140 Backport from mainline: 150 Backport from mainline:
141 2011-02-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 151 2011-02-11 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
142 152
143 PR testsuite/47400 153 PR testsuite/47400
144 * doc/sourcebuild.texi (Require Support): Document 154 * doc/sourcebuild.texi (Require Support): Document
145 dg-require-ascii-locale. 155 dg-require-ascii-locale.
146 156
1472011-04-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 1572011-04-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
148 158
149 Backport from mainline: 159 Backport from mainline:
150 2011-04-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> 160 2011-04-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
151 PR target/48090 161 PR target/48090
152 * config/arm/arm.md (*arm_negdi2): Fix early clobber constraints. 162 * config/arm/arm.md (*arm_negdi2): Fix early clobber constraints.
153 163
1542011-04-12 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 1642011-04-12 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
155 165
156 Backport from mainline: 166 Backport from mainline:
157 2011-04-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 167 2011-04-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
158 168
159 * config/alpha/osf.h (MAX_OFILE_ALIGNMENT): Define. 169 * config/alpha/osf.h (MAX_OFILE_ALIGNMENT): Define.
160 170
1612011-04-09 Duncan Sands <baldrick@free.fr> 1712011-04-09 Duncan Sands <baldrick@free.fr>
162 172
163 * tree.c (array_type_nelts): Bail out if TYPE_MAX_VALUE not set. 173 * tree.c (array_type_nelts): Bail out if TYPE_MAX_VALUE not set.
164 174
1652011-04-07 Uros Bizjak <ubizjak@gmail.com> 1752011-04-07 Uros Bizjak <ubizjak@gmail.com>
166 176
167 * config/i386/sse.md (avx_cmps<ssemodesuffixf2c><mode>3): Add 177 * config/i386/sse.md (avx_cmps<ssemodesuffixf2c><mode>3): Add
168 missing output register constraint. 178 missing output register constraint.
169 (*vec_concatv2sf_avx): Fix wrong register constraint in 179 (*vec_concatv2sf_avx): Fix wrong register constraint in
170 alternative 3 of operand 1. 180 alternative 3 of operand 1.
171 (*vec_set<mode>_0_avx): Avoid combining registers from different 181 (*vec_set<mode>_0_avx): Avoid combining registers from different
172 units in a single alternative. 182 units in a single alternative.
173 (*vec_set<mode>_0_sse4_1): Ditto. 183 (*vec_set<mode>_0_sse4_1): Ditto.
174 (*vec_set<mode>_0_sse2): Ditto. 184 (*vec_set<mode>_0_sse2): Ditto.
175 (vec_set<mode>_0): Ditto. 185 (vec_set<mode>_0): Ditto.
176 (sse2_storehpd): Ditto. 186 (sse2_storehpd): Ditto.
177 (sse2_loadhpd): Ditto. 187 (sse2_loadhpd): Ditto.
178 (sse4_1_insertps): Use nonimmediate_operand for operand 2. 188 (sse4_1_insertps): Use nonimmediate_operand for operand 2.
179 * config/i386/predicates.md (sse_comparison_operator): Do not 189 * config/i386/predicates.md (sse_comparison_operator): Do not
180 define as special predicate. 190 define as special predicate.
181 191
1822011-04-07 Jakub Jelinek <jakub@redhat.com> 1922011-04-07 Jakub Jelinek <jakub@redhat.com>
183 193
184 Backported from mainline 194 Backported from mainline
185 2011-04-06 Jakub Jelinek <jakub@redhat.com> 195 2011-04-06 Jakub Jelinek <jakub@redhat.com>
186 196
187 PR debug/48466 197 PR debug/48466
188 * dwarf2out.c (based_loc_descr): If drap_reg is INVALID_REGNUM, use 198 * dwarf2out.c (based_loc_descr): If drap_reg is INVALID_REGNUM, use
189 as base_reg whatever register reg has been eliminated to, instead 199 as base_reg whatever register reg has been eliminated to, instead
190 of hardcoding STACK_POINTER_REGNUM. 200 of hardcoding STACK_POINTER_REGNUM.
191 201
192 2011-03-24 Jakub Jelinek <jakub@redhat.com> 202 2011-03-24 Jakub Jelinek <jakub@redhat.com>
193 203
194 PR debug/48204 204 PR debug/48204
195 * simplify-rtx.c (simplify_const_unary_operation): Call 205 * simplify-rtx.c (simplify_const_unary_operation): Call
196 real_convert when changing mode class with FLOAT_EXTEND. 206 real_convert when changing mode class with FLOAT_EXTEND.
197 207
198 2011-03-17 Jakub Jelinek <jakub@redhat.com> 208 2011-03-17 Jakub Jelinek <jakub@redhat.com>
199 209
200 PR rtl-optimization/48141 210 PR rtl-optimization/48141
201 * dse.c (record_store): If no positions are needed in an insn 211 * dse.c (record_store): If no positions are needed in an insn
202 that cannot be deleted, at least unchain it from active_local_stores. 212 that cannot be deleted, at least unchain it from active_local_stores.
203 213
204 2011-03-03 Jakub Jelinek <jakub@redhat.com> 214 2011-03-03 Jakub Jelinek <jakub@redhat.com>
205 215
206 PR c/47963 216 PR c/47963
207 * gimplify.c (omp_add_variable): Only call omp_notice_variable 217 * gimplify.c (omp_add_variable): Only call omp_notice_variable
208 on TYPE_SIZE_UNIT if it is a DECL. 218 on TYPE_SIZE_UNIT if it is a DECL.
209 219
210 2011-02-19 Jakub Jelinek <jakub@redhat.com> 220 2011-02-19 Jakub Jelinek <jakub@redhat.com>
211 221
212 PR c/47809 222 PR c/47809
213 * c-common.c (c_fully_fold_internal): Handle VIEW_CONVERT_EXPR. 223 * c-common.c (c_fully_fold_internal): Handle VIEW_CONVERT_EXPR.
214 224
215 2011-01-26 Jakub Jelinek <jakub@redhat.com> 225 2011-01-26 Jakub Jelinek <jakub@redhat.com>
216 226
217 PR c/47473 227 PR c/47473
218 * c-lex.c (interpret_float): If CPP_N_IMAGINARY, ensure 228 * c-lex.c (interpret_float): If CPP_N_IMAGINARY, ensure
219 EXCESS_PRECISION_EXPR is created with COMPLEX_TYPE instead of 229 EXCESS_PRECISION_EXPR is created with COMPLEX_TYPE instead of
220 REAL_TYPE. 230 REAL_TYPE.
221 231
2222011-04-07 Jakub Jelinek <jakub@redhat.com> 2322011-04-07 Jakub Jelinek <jakub@redhat.com>
223 233
224 PR tree-optimization/47391 234 PR tree-optimization/47391
225 * tree-ssa-ccp.c (get_symbol_constant_value): Don't optimize 235 * tree-ssa-ccp.c (get_symbol_constant_value): Don't optimize
226 if sym is volatile. 236 if sym is volatile.
227 237
228 Backported from mainline 238 Backported from mainline
229 2010-07-01 Richard Guenther <rguenther@suse.de> 239 2010-07-01 Richard Guenther <rguenther@suse.de>
230 240
231 * omp-low.c (scan_omp_1_op): Don't change type of INTEGER_CSTs 241 * omp-low.c (scan_omp_1_op): Don't change type of INTEGER_CSTs
232 directly. 242 directly.
233 243
2342011-04-07 Andrey Belevantsev <abel@ispras.ru> 2442011-04-07 Andrey Belevantsev <abel@ispras.ru>
235 245
236 Backport from mainline 246 Backport from mainline
237 2011-03-26 Andrey Belevantsev <abel@ispras.ru> 247 2011-03-26 Andrey Belevantsev <abel@ispras.ru>
238 248
239 PR rtl-optimization/48144 249 PR rtl-optimization/48144
240 * sel-sched-ir.c (merge_history_vect): Factor out from ... 250 * sel-sched-ir.c (merge_history_vect): Factor out from ...
241 (merge_expr_data): ... here. 251 (merge_expr_data): ... here.
242 (av_set_intersect): Rename to av_set_code_motion_filter. 252 (av_set_intersect): Rename to av_set_code_motion_filter.
243 Update all callers. Call merge_history_vect when an expression 253 Update all callers. Call merge_history_vect when an expression
244 is found in both sets. 254 is found in both sets.
245 * sel-sched-ir.h (av_set_code_motion_filter): Add prototype. 255 * sel-sched-ir.h (av_set_code_motion_filter): Add prototype.
246 256
2472011-04-07 Andrey Belevantsev <abel@ispras.ru> 2572011-04-07 Andrey Belevantsev <abel@ispras.ru>
248 258
249 Backport from mainline 259 Backport from mainline
250 2011-01-13 Andrey Belevantsev <abel@ispras.ru> 260 2011-01-13 Andrey Belevantsev <abel@ispras.ru>
251 261
252 PR rtl-optimization/45352 262 PR rtl-optimization/45352
253 * sel-sched.c: Update copyright years. 263 * sel-sched.c: Update copyright years.
254 (reset_sched_cycles_in_current_ebb): Also recheck the DFA state 264 (reset_sched_cycles_in_current_ebb): Also recheck the DFA state
255 in the advancing loop when we have issued issue_rate insns. 265 in the advancing loop when we have issued issue_rate insns.
256 266
257 Backport from mainline 267 Backport from mainline
258 2010-12-22 Andrey Belevantsev <abel@ispras.ru> 268 2010-12-22 Andrey Belevantsev <abel@ispras.ru>
259 269
260 PR rtl-optimization/45352 270 PR rtl-optimization/45352
261 PR rtl-optimization/46521 271 PR rtl-optimization/46521
262 PR rtl-optimization/46522 272 PR rtl-optimization/46522
263 * sel-sched.c (reset_sched_cycles_in_current_ebb): Recheck the DFA state 273 * sel-sched.c (reset_sched_cycles_in_current_ebb): Recheck the DFA state
264 on the last iteration of the advancing loop. 274 on the last iteration of the advancing loop.
265 (sel_sched_region_1): Propagate the rescheduling bit to the next block 275 (sel_sched_region_1): Propagate the rescheduling bit to the next block
266 also for empty blocks. 276 also for empty blocks.
267 277
268 Backport from mainline 278 Backport from mainline
269 2010-11-08 Andrey Belevantsev <abel@ispras.ru> 279 2010-11-08 Andrey Belevantsev <abel@ispras.ru>
270 280
271 PR rtl-optimization/45352 281 PR rtl-optimization/45352
272 * sel-sched.c (find_best_expr): Do not set pneed_stall when 282 * sel-sched.c (find_best_expr): Do not set pneed_stall when
273 the variable_issue hook is not implemented. 283 the variable_issue hook is not implemented.
274 (fill_insns): Remove dead variable stall_iterations. 284 (fill_insns): Remove dead variable stall_iterations.
275 (init_seqno_1): Force EBB start for resetting sched cycles on any 285 (init_seqno_1): Force EBB start for resetting sched cycles on any
276 successor blocks of the rescheduled region. 286 successor blocks of the rescheduled region.
277 (sel_sched_region_1): Use bitmap_bit_p instead of bitmap_clear_bit. 287 (sel_sched_region_1): Use bitmap_bit_p instead of bitmap_clear_bit.
278 (reset_sched_cycles_in_current_ebb): Add debug printing. 288 (reset_sched_cycles_in_current_ebb): Add debug printing.
279 New variable issued_insns. Advance state when we have issued 289 New variable issued_insns. Advance state when we have issued
280 issue_rate insns. 290 issue_rate insns.
281 291
2822011-04-07 Andrey Belevantsev <abel@ispras.ru> 2922011-04-07 Andrey Belevantsev <abel@ispras.ru>
283 293
284 Backport from mainline 294 Backport from mainline
285 2010-12-24 Alexander Monakov <amonakov@ispras.ru> 295 2010-12-24 Alexander Monakov <amonakov@ispras.ru>
286 296
287 PR rtl-optimization/47036 297 PR rtl-optimization/47036
288 * sel-sched-ir.c (fallthru_bb_of_jump): Remove special support for 298 * sel-sched-ir.c (fallthru_bb_of_jump): Remove special support for
289 unconditional jumps. 299 unconditional jumps.
290 * sel-sched.c (moveup_expr): Ditto. 300 * sel-sched.c (moveup_expr): Ditto.
291 301
2922011-04-07 Andrey Belevantsev <abel@ispras.ru> 3022011-04-07 Andrey Belevantsev <abel@ispras.ru>
293 303
294 Backport from mainline 304 Backport from mainline
295 2010-12-15 Alexander Monakov <amonakov@ispras.ru> 305 2010-12-15 Alexander Monakov <amonakov@ispras.ru>
296 306
297 PR rtl-optimization/46649 307 PR rtl-optimization/46649
298 * sel-sched-ir.c (purge_empty_blocks): Unconditionally skip the first 308 * sel-sched-ir.c (purge_empty_blocks): Unconditionally skip the first
299 basic block in the region. 309 basic block in the region.
300 310
3012011-04-07 Andrey Belevantsev <abel@ispras.ru> 3112011-04-07 Andrey Belevantsev <abel@ispras.ru>
302 312
303 Backport from mainline 313 Backport from mainline
304 2010-12-14 Alexander Monakov <amonakov@ispras.ru> 314 2010-12-14 Alexander Monakov <amonakov@ispras.ru>
305 315
306 PR rtl-optimization/46875 316 PR rtl-optimization/46875
307 * sched-vis.c (print_pattern): Dump "sequence" for ADDR_VECs. 317 * sched-vis.c (print_pattern): Dump "sequence" for ADDR_VECs.
308 * sel-sched-ir.c (bb_has_removable_jump_to_p): Forbid table jumps. 318 * sel-sched-ir.c (bb_has_removable_jump_to_p): Forbid table jumps.
309 319
3102011-04-07 Andrey Belevantsev <abel@ispras.ru> 3202011-04-07 Andrey Belevantsev <abel@ispras.ru>
311 321
312 Backport from mainline 322 Backport from mainline
313 2010-12-07 Andrey Belevantsev <abel@ispras.ru> 323 2010-12-07 Andrey Belevantsev <abel@ispras.ru>
314 PR target/43603 324 PR target/43603
315 * haifa-sched.c (sched_create_recovery_edges): Update 325 * haifa-sched.c (sched_create_recovery_edges): Update
316 dominator info. 326 dominator info.
317 * sel-sched-ir.c (maybe_tidy_empty_bb): Update dominator info 327 * sel-sched-ir.c (maybe_tidy_empty_bb): Update dominator info
318 after deleting an empty block. 328 after deleting an empty block.
319 (tidy_control_flow): Also verify dominators. 329 (tidy_control_flow): Also verify dominators.
320 (sel_remove_bb): Update dominator info after removing a block. 330 (sel_remove_bb): Update dominator info after removing a block.
321 (sel_redirect_edge_and_branch_force): Assert that no unreachable 331 (sel_redirect_edge_and_branch_force): Assert that no unreachable
322 blocks will be created. Update dominator info. 332 blocks will be created. Update dominator info.
323 (sel_redirect_edge_and_branch): Update dominator info when 333 (sel_redirect_edge_and_branch): Update dominator info when
324 basic blocks do not become unreachable. 334 basic blocks do not become unreachable.
325 (sel_remove_loop_preheader): Update dominator info. 335 (sel_remove_loop_preheader): Update dominator info.
326 336
327 2010-10-14 Andrey Belevantsev <abel@ispras.ru> 337 2010-10-14 Andrey Belevantsev <abel@ispras.ru>
328 338
329 * sel-sched-ir.c (maybe_tidy_empty_bb): Simplify comment. 339 * sel-sched-ir.c (maybe_tidy_empty_bb): Simplify comment.
330 (tidy_control_flow): Tidy vertical space. 340 (tidy_control_flow): Tidy vertical space.
331 (sel_remove_bb): New variable idx. Use it to remember the basic 341 (sel_remove_bb): New variable idx. Use it to remember the basic
332 block index before deleting the block. 342 block index before deleting the block.
333 (sel_remove_empty_bb): Remove dead code, simplify and insert to ... 343 (sel_remove_empty_bb): Remove dead code, simplify and insert to ...
334 (sel_merge_blocks): ... here. 344 (sel_merge_blocks): ... here.
335 * sel-sched-ir.h (sel_remove_empty_bb): Remove prototype. 345 * sel-sched-ir.h (sel_remove_empty_bb): Remove prototype.
336 346
3372011-04-07 Andrey Belevantsev <abel@ispras.ru> 3472011-04-07 Andrey Belevantsev <abel@ispras.ru>
338 348
339 Backport from mainline 349 Backport from mainline
340 2010-12-03 Alexander Monakov <amonakov@ispras.ru> 350 2010-12-03 Alexander Monakov <amonakov@ispras.ru>
341 351
342 PR rtl-optimization/45354 352 PR rtl-optimization/45354
343 * sel-sched-ir.c (jump_leads_only_to_bb_p): Rename to ... 353 * sel-sched-ir.c (jump_leads_only_to_bb_p): Rename to ...
344 (bb_has_removable_jump_to_p): This. Update all callers. Make static. 354 (bb_has_removable_jump_to_p): This. Update all callers. Make static.
345 Allow BBs ending with a conditional jump. Forbid EDGE_CROSSING jumps. 355 Allow BBs ending with a conditional jump. Forbid EDGE_CROSSING jumps.
346 * sel-sched-ir.h (jump_leads_only_to_bb_p): Delete prototype. 356 * sel-sched-ir.h (jump_leads_only_to_bb_p): Delete prototype.
347 357
3482011-04-07 Andrey Belevantsev <abel@ispras.ru> 3582011-04-07 Andrey Belevantsev <abel@ispras.ru>
349 359
350 Backport from mainline 360 Backport from mainline
351 2010-11-25 Alexander Monakov <amonakov@ispras.ru> 361 2010-11-25 Alexander Monakov <amonakov@ispras.ru>
352 362
353 PR rtl-optimization/46585 363 PR rtl-optimization/46585
354 * sel-sched-ir.c (return_regset_to_pool): Verify that RS is not NULL. 364 * sel-sched-ir.c (return_regset_to_pool): Verify that RS is not NULL.
355 (vinsn_init): Skip computation of dependencies for local NOPs. 365 (vinsn_init): Skip computation of dependencies for local NOPs.
356 (vinsn_delete): Don't try to free regsets for local NOPs. 366 (vinsn_delete): Don't try to free regsets for local NOPs.
357 (setup_nop_and_exit_insns): Change definition of nop_pattern. 367 (setup_nop_and_exit_insns): Change definition of nop_pattern.
358 368
3592011-04-07 Andrey Belevantsev <abel@ispras.ru> 3692011-04-07 Andrey Belevantsev <abel@ispras.ru>
360 370
361 Backport from mainline 371 Backport from mainline
362 2010-11-25 Alexander Monakov <amonakov@ispras.ru> 372 2010-11-25 Alexander Monakov <amonakov@ispras.ru>
363 373
364 PR rtl-optimization/46602 374 PR rtl-optimization/46602
365 * sel-sched-ir.c (maybe_tidy_empty_bb): Move checking ... 375 * sel-sched-ir.c (maybe_tidy_empty_bb): Move checking ...
366 (tidy_control_flow): Here. 376 (tidy_control_flow): Here.
367 377
3682011-04-07 Andrey Belevantsev <abel@ispras.ru> 3782011-04-07 Andrey Belevantsev <abel@ispras.ru>
369 379
370 Backport from mainline 380 Backport from mainline
371 2010-11-22 Alexander Monakov <amonakov@ispras.ru> 381 2010-11-22 Alexander Monakov <amonakov@ispras.ru>
372 382
373 PR rtl-optimization/45652 383 PR rtl-optimization/45652
374 * alias.c (get_reg_base_value): New. 384 * alias.c (get_reg_base_value): New.
375 * rtl.h (get_reg_base_value): Add prototype. 385 * rtl.h (get_reg_base_value): Add prototype.
376 * sel-sched.c (init_regs_for_mode): Use it. Don't use registers with 386 * sel-sched.c (init_regs_for_mode): Use it. Don't use registers with
377 non-null REG_BASE_VALUE for renaming. 387 non-null REG_BASE_VALUE for renaming.
378 388
3792011-04-07 Andrey Belevantsev <abel@ispras.ru> 3892011-04-07 Andrey Belevantsev <abel@ispras.ru>
380 390
381 Backport from mainline 391 Backport from mainline
382 2010-11-18 Alexander Monakov <amonakov@ispras.ru> 392 2010-11-18 Alexander Monakov <amonakov@ispras.ru>
383 393
384 PR middle-end/46518 394 PR middle-end/46518
385 * sel-sched-ir.c (init_expr): Use the correct type for 395 * sel-sched-ir.c (init_expr): Use the correct type for
386 target_available. 396 target_available.
387 * sel-sched.c (fill_vec_av_set): Use explicitly signed char type. 397 * sel-sched.c (fill_vec_av_set): Use explicitly signed char type.
388 398
3892011-04-07 Andrey Belevantsev <abel@ispras.ru> 3992011-04-07 Andrey Belevantsev <abel@ispras.ru>
390 400
391 Backport from mainline 401 Backport from mainline
392 2010-11-12 Alexander Monakov <amonakov@ispras.ru> 402 2010-11-12 Alexander Monakov <amonakov@ispras.ru>
393 403
394 PR rtl-optimization/46204 404 PR rtl-optimization/46204
395 sel-sched-ir.c (maybe_tidy_empty_bb): Remove second argument. 405 sel-sched-ir.c (maybe_tidy_empty_bb): Remove second argument.
396 pdate all callers. Do not recompute topological order. Adjust 406 pdate all callers. Do not recompute topological order. Adjust
397 allthrough edges following a degenerate conditional jump. 407 allthrough edges following a degenerate conditional jump.
398 408
3992011-04-07 Andrey Belevantsev <abel@ispras.ru> 4092011-04-07 Andrey Belevantsev <abel@ispras.ru>
400 410
401 Backport from mainline 411 Backport from mainline
402 2010-10-14 Andrey Belevantsev <abel@ispras.ru> 412 2010-10-14 Andrey Belevantsev <abel@ispras.ru>
403 413
404 PR rtl-optimization/45570 414 PR rtl-optimization/45570
405 * sel-sched-ir.c (cfg_preds_1): When walking out of the region, 415 * sel-sched-ir.c (cfg_preds_1): When walking out of the region,
406 assert that we are pipelining outer loops. Allow returning 416 assert that we are pipelining outer loops. Allow returning
407 zero predecessors. 417 zero predecessors.
408 418
4092011-04-06 Joseph Myers <joseph@codesourcery.com> 4192011-04-06 Joseph Myers <joseph@codesourcery.com>
410 420
411 * gcov-io.c: Use GCC Runtime Library Exception. 421 * gcov-io.c: Use GCC Runtime Library Exception.
412 422
4132011-03-30 H.J. Lu <hongjiu.lu@intel.com> 4232011-03-30 H.J. Lu <hongjiu.lu@intel.com>
414 424
415 Backport from mainline 425 Backport from mainline
416 2011-03-30 H.J. Lu <hongjiu.lu@intel.com> 426 2011-03-30 H.J. Lu <hongjiu.lu@intel.com>
417 427
418 PR target/48349 428 PR target/48349
419 * config/i386/i386.h (REG_CLASS_CONTENTS): Fix a typo in 429 * config/i386/i386.h (REG_CLASS_CONTENTS): Fix a typo in
420 FLOAT_SSE_REGS. 430 FLOAT_SSE_REGS.
421 431
4222011-03-29 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> 4322011-03-29 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
423 433
424 * config/s390/s390.c (s390_preferred_reload_class): Return NO_REGS 434 * config/s390/s390.c (s390_preferred_reload_class): Return NO_REGS
425 for invalid symbolic addresses. 435 for invalid symbolic addresses.
426 (s390_secondary_reload): Don't use s390_check_symref_alignment for 436 (s390_secondary_reload): Don't use s390_check_symref_alignment for
427 larl operands. 437 larl operands.
428 438
4292011-03-28 Richard Sandiford <richard.sandiford@linaro.org> 4392011-03-28 Richard Sandiford <richard.sandiford@linaro.org>
430 440
431 PR target/47553 441 PR target/47553
432 * config/arm/predicates.md (neon_lane_number): Accept 0..15. 442 * config/arm/predicates.md (neon_lane_number): Accept 0..15.
433 443
4342011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com> 4442011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com>
435 445
436 PR other/48254 446 PR other/48254
437 * doc/invoke.texi (-fipa-struct-reorg): Fix typo. 447 * doc/invoke.texi (-fipa-struct-reorg): Fix typo.
438 448
4392011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com> 4492011-03-23 Jonathan Wakely <jwakely.gcc@gmail.com>
440 450
441 PR other/48179 451 PR other/48179
442 PR other/48234 452 PR other/48234
443 * doc/extend.texi (Alignment): Move section to match order in TOC. 453 * doc/extend.texi (Alignment): Move section to match order in TOC.
444 * doc/invoke.texi (i386 and x86-64 Windows Options): Likewise. 454 * doc/invoke.texi (i386 and x86-64 Windows Options): Likewise.
445 455
4462011-03-18 H.J. Lu <hongjiu.lu@intel.com> 4562011-03-18 H.J. Lu <hongjiu.lu@intel.com>
447 457
448 Backport from mainline 458 Backport from mainline
449 2011-03-17 H.J. Lu <hongjiu.lu@intel.com> 459 2011-03-17 H.J. Lu <hongjiu.lu@intel.com>
450 460
451 PR target/48171 461 PR target/48171
452 * config/i386/i386.opt: Add Save to -mavx and -mfma. 462 * config/i386/i386.opt: Add Save to -mavx and -mfma.
453 463
4542011-03-16 Pat Haugen <pthaugen@us.ibm.com> 4642011-03-16 Pat Haugen <pthaugen@us.ibm.com>
455 465
456 PR target/47862 466 PR target/47862
457 * caller-save.c (insert_restore, insert_save): Use non-validate 467 * caller-save.c (insert_restore, insert_save): Use non-validate
458 form of adjust_address. 468 form of adjust_address.
459 469
4602011-03-16 Nick Clifton <nickc@redhat.com> 4702011-03-16 Nick Clifton <nickc@redhat.com>
461 471
462 * config/rx/rx.h (JUMP_ALIGN): Define. 472 * config/rx/rx.h (JUMP_ALIGN): Define.
463 (JUMP_ALIGN_MAX_SKIP, LABEL_ALIGN_AFTER_BARRIER, LOOP_ALIGN, 473 (JUMP_ALIGN_MAX_SKIP, LABEL_ALIGN_AFTER_BARRIER, LOOP_ALIGN,
464 (LABEL_ALIGN, LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP, 474 (LABEL_ALIGN, LABEL_ALIGN_AFTER_BARRIER_MAX_SKIP,
465 (LOOP_ALIGN_MAX_SKIP, LABEL_ALIGN_MAX_SKIP): Define. 475 (LOOP_ALIGN_MAX_SKIP, LABEL_ALIGN_MAX_SKIP): Define.
466 * config/rx/rx-protos.h (rx_align_for_label): Prototype. 476 * config/rx/rx-protos.h (rx_align_for_label): Prototype.
467 (rx_max_skip_for_label): Prototype. 477 (rx_max_skip_for_label): Prototype.
468 * config/rx/rx.md (abssi3): Use CC_ZSmode. 478 * config/rx/rx.md (abssi3): Use CC_ZSmode.
469 (andis3): Fix timings. 479 (andis3): Fix timings.
470 (peephole): Add peephole to combine zero- and sign- extending 480 (peephole): Add peephole to combine zero- and sign- extending
471 loads with arithmetic instructions. 481 loads with arithmetic instructions.
472 (bset): Fix timing. 482 (bset): Fix timing.
473 (bclr): Fix timing. 483 (bclr): Fix timing.
474 * config/rx/rx.c (rx_is_legitimate_address): Add checks for QImode 484 * config/rx/rx.c (rx_is_legitimate_address): Add checks for QImode
475 and HImode reg+int address. 485 and HImode reg+int address.
476 (rx_print_operand): Add support for %R. Fix generation of .B and 486 (rx_print_operand): Add support for %R. Fix generation of .B and
477 .W addressing modes. 487 .W addressing modes.
478 (rx_align_for_label): New function. 488 (rx_align_for_label): New function.
479 (rx_max_skip_for_label): New function. 489 (rx_max_skip_for_label): New function.
480 490
4812011-03-10 Jason Merrill <jason@redhat.com> 4912011-03-10 Jason Merrill <jason@redhat.com>
482 492
483 PR c++/48029 493 PR c++/48029
484 * stor-layout.c (layout_type): Don't set structural equality 494 * stor-layout.c (layout_type): Don't set structural equality
485 on arrays of incomplete type. 495 on arrays of incomplete type.
486 * tree.c (type_hash_eq): Handle comparing them properly. 496 * tree.c (type_hash_eq): Handle comparing them properly.
487 497
4882011-03-08 Richard Guenther <rguenther@suse.de> 4982011-03-08 Richard Guenther <rguenther@suse.de>
489 499
490 Backport from mainline 500 Backport from mainline
491 2011-02-10 Richard Guenther <rguenther@suse.de> 501 2011-02-10 Richard Guenther <rguenther@suse.de>
492 502
493 * tree-ssa-structalias.c (bitpos_of_field): Use BITS_PER_UNIT, not 8. 503 * tree-ssa-structalias.c (bitpos_of_field): Use BITS_PER_UNIT, not 8.
494 504
495 2010-10-18 Richard Guenther <rguenther@suse.de> 505 2010-10-18 Richard Guenther <rguenther@suse.de>
496 506
497 PR tree-optimization/45967 507 PR tree-optimization/45967
498 * tree-ssa-structalias.c (type_could_have_pointers): Remove. 508 * tree-ssa-structalias.c (type_could_have_pointers): Remove.
499 (could_have_pointers): Likewise. 509 (could_have_pointers): Likewise.
500 (handle_rhs_call, handle_const_call, handle_pure_call, 510 (handle_rhs_call, handle_const_call, handle_pure_call,
501 find_func_aliases, intra_create_variable_infos): Remove calls to them. 511 find_func_aliases, intra_create_variable_infos): Remove calls to them.
502 (struct fieldoff): Add must_have_pointers field. 512 (struct fieldoff): Add must_have_pointers field.
503 (type_must_have_pointers): New function. 513 (type_must_have_pointers): New function.
504 (field_must_have_pointers): Likewise. 514 (field_must_have_pointers): Likewise.
505 (push_fields_onto_fieldstack): Remove must_have_pointers_p argument. 515 (push_fields_onto_fieldstack): Remove must_have_pointers_p argument.
506 Adjust field merging. 516 Adjust field merging.
507 (create_function_info_for): May-have-pointers of varinfo is 517 (create_function_info_for): May-have-pointers of varinfo is
508 almost always true. 518 almost always true.
509 (create_variable_info_for_1): Likewise. 519 (create_variable_info_for_1): Likewise.
510 520
511 2010-10-12 Richard Guenther <rguenther@suse.de> 521 2010-10-12 Richard Guenther <rguenther@suse.de>
512 522
513 * tree-ssa-structalias.c (get_constraint_for_1): Constants 523 * tree-ssa-structalias.c (get_constraint_for_1): Constants
514 only point to nonlocal, not anything. 524 only point to nonlocal, not anything.
515 525
5162011-03-08 Richard Guenther <rguenther@suse.de> 5262011-03-08 Richard Guenther <rguenther@suse.de>
517 527
518 PR tree-optimization/47278 528 PR tree-optimization/47278
519 * tree.h (DECL_REPLACEABLE_P): Remove. 529 * tree.h (DECL_REPLACEABLE_P): Remove.
520 (decl_replaceable_p): Declare. 530 (decl_replaceable_p): Declare.
521 (decl_binds_to_current_def_p): Likewise. 531 (decl_binds_to_current_def_p): Likewise.
522 * varasm.c (decl_replaceable_p): New function. 532 * varasm.c (decl_replaceable_p): New function.
523 (decl_binds_to_current_def_p): Likewise. 533 (decl_binds_to_current_def_p): Likewise.
524 * cgraph.c (cgraph_function_body_availability): Use decl_replaceable_p. 534 * cgraph.c (cgraph_function_body_availability): Use decl_replaceable_p.
525 * tree-inline.c (inlinable_function_p): Likewise. 535 * tree-inline.c (inlinable_function_p): Likewise.
526 536
5272011-03-07 Pat Haugen <pthaugen@us.ibm.com> 5372011-03-07 Pat Haugen <pthaugen@us.ibm.com>
528 538
529 Backport from mainline 539 Backport from mainline
530 2011-03-07 Pat Haugen <pthaugen@us.ibm.com> 540 2011-03-07 Pat Haugen <pthaugen@us.ibm.com>
531 541
532 PR target/47862 542 PR target/47862
533 * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define. 543 * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Define.
534 544
5352011-03-07 Mingjie Xing <mingjie.xing@gmail.com> 5452011-03-07 Mingjie Xing <mingjie.xing@gmail.com>
536 546
537 * doc/cfg.texi: Remove "See" before @ref. 547 * doc/cfg.texi: Remove "See" before @ref.
538 * doc/invoke.texi: Likewise. 548 * doc/invoke.texi: Likewise.
539 549
5402011-03-03 Uros Bizjak <ubizjak@gmail.com> 5502011-03-03 Uros Bizjak <ubizjak@gmail.com>
541 551
542 * config/i386/sse.md (*avx_pmaddubsw128): Fix mode of VEC_SELECT RTX. 552 * config/i386/sse.md (*avx_pmaddubsw128): Fix mode of VEC_SELECT RTX.
543 (ssse3_pmaddubsw128): Ditto. 553 (ssse3_pmaddubsw128): Ditto.
544 (ssse3_pmaddubsw): Ditto. 554 (ssse3_pmaddubsw): Ditto.
545 555
5462011-03-03 Denis Chertykov <chertykov@gmail.com> 5562011-03-03 Denis Chertykov <chertykov@gmail.com>
547 557
548 Backport from mainline 558 Backport from mainline
549 2011-02-22 Georg-Johann Lay <avr@gjlay.de> 559 2011-02-22 Georg-Johann Lay <avr@gjlay.de>
550 560
551 PR target/42240 561 PR target/42240
552 * config/avr/avr.c (avr_cannot_modify_jumps_p): New function. 562 * config/avr/avr.c (avr_cannot_modify_jumps_p): New function.
553 (TARGET_CANNOT_MODIFY_JUMPS_P): Define. 563 (TARGET_CANNOT_MODIFY_JUMPS_P): Define.
554 564
5552011-03-03 Richard Guenther <rguenther@suse.de> 5652011-03-03 Richard Guenther <rguenther@suse.de>
556 566
557 * tree-vect-stmt.c (vectorizable_operation): Remove unused vars. 567 * tree-vect-stmt.c (vectorizable_operation): Remove unused vars.
558 568
5592011-03-02 Richard Guenther <rguenther@suse.de> 5692011-03-02 Richard Guenther <rguenther@suse.de>
560 570
561 Backport from mainline 571 Backport from mainline
562 2011-02-07 Richard Guenther <rguenther@suse.de> 572 2011-02-07 Richard Guenther <rguenther@suse.de>
563 573
564 PR tree-optimization/47615 574 PR tree-optimization/47615
565 * tree-ssa-sccvn.h (run_scc_vn): Take a vn-walk mode argument. 575 * tree-ssa-sccvn.h (run_scc_vn): Take a vn-walk mode argument.
566 * tree-ssa-sccvn.c (default_vn_walk_kind): New global. 576 * tree-ssa-sccvn.c (default_vn_walk_kind): New global.
567 (run_scc_vn): Initialize it. 577 (run_scc_vn): Initialize it.
568 (visit_reference_op_load): Use it. 578 (visit_reference_op_load): Use it.
569 * tree-ssa-pre.c (execute_pre): Use VN_WALK if in PRE. 579 * tree-ssa-pre.c (execute_pre): Use VN_WALK if in PRE.
570 580
5712011-03-01 Richard Guenther <rguenther@suse.de> 5812011-03-01 Richard Guenther <rguenther@suse.de>
572 582
573 Backport from mainline 583 Backport from mainline
574 2011-02-08 Richard Guenther <rguenther@suse.de> 584 2011-02-08 Richard Guenther <rguenther@suse.de>
575 585
576 PR middle-end/47639 586 PR middle-end/47639
577 * tree-vect-generic.c (expand_vector_operations_1): Update 587 * tree-vect-generic.c (expand_vector_operations_1): Update
578 stmts here ... 588 stmts here ...
579 (expand_vector_operations): ... not here. Cleanup EH info 589 (expand_vector_operations): ... not here. Cleanup EH info
580 and the CFG if required. 590 and the CFG if required.
581 591
5822011-03-01 Richard Guenther <rguenther@suse.de> 5922011-03-01 Richard Guenther <rguenther@suse.de>
583 593
584 Backport from mainline 594 Backport from mainline
585 2011-03-01 Richard Guenther <rguenther@suse.de> 595 2011-03-01 Richard Guenther <rguenther@suse.de>
586 596
587 PR tree-optimization/47890 597 PR tree-optimization/47890
588 * tree-vect-loop.c (get_initial_def_for_induction): Set 598 * tree-vect-loop.c (get_initial_def_for_induction): Set
589 related stmt properly. 599 related stmt properly.
590 600
591 2010-12-01 Richard Guenther <rguenther@suse.de> 601 2010-12-01 Richard Guenther <rguenther@suse.de>
592 602
593 PR tree-optimization/46723 603 PR tree-optimization/46723
594 * tree-vect-loop.c (get_initial_def_for_induction): Strip 604 * tree-vect-loop.c (get_initial_def_for_induction): Strip
595 conversions from the induction evolution and apply it to 605 conversions from the induction evolution and apply it to
596 the result instead. 606 the result instead.
597 * tree-vect-stmts.c (vect_get_vec_def_for_operand): Handle 607 * tree-vect-stmts.c (vect_get_vec_def_for_operand): Handle
598 assigns for induction defs. 608 assigns for induction defs.
599 609
6002011-02-28 Georg-Johann Lay <avr@gjlay.de> 6102011-02-28 Georg-Johann Lay <avr@gjlay.de>
601 611
602 PR target/45261 612 PR target/45261
603 * config/avr/avr.c (avr_option_override): Use error on bad options. 613 * config/avr/avr.c (avr_option_override): Use error on bad options.
604 (avr_help): New function. 614 (avr_help): New function.
605 (TARGET_HELP): Define. 615 (TARGET_HELP): Define.
606 616
6072011-02-26 Gerald Pfeifer <gerald@pfeifer.com> 6172011-02-26 Gerald Pfeifer <gerald@pfeifer.com>
608 618
609 * doc/invoke.texi (ARC Options): Use CPU instead of cpu. 619 * doc/invoke.texi (ARC Options): Use CPU instead of cpu.
610 (ARM Options): Ditto. 620 (ARM Options): Ditto.
611 (i386 and x86-64 Options): Ditto. 621 (i386 and x86-64 Options): Ditto.
612 (RX Options): Ditto. 622 (RX Options): Ditto.
613 (SPARC Options): Ditto. 623 (SPARC Options): Ditto.
614 624
6152011-02-26 Tijl Coosemans <tijl@coosemans.org> 6252011-02-26 Tijl Coosemans <tijl@coosemans.org>
616 626
617 * config.gcc (i386-*-freebsd*): Make i486 the default arch on 627 * config.gcc (i386-*-freebsd*): Make i486 the default arch on
618 FreeBSD 6 and later. Generally use cpu generic. 628 FreeBSD 6 and later. Generally use cpu generic.
619 629
6202011-02-25 Gerald Pfeifer <gerald@pfeifer.com> 6302011-02-25 Gerald Pfeifer <gerald@pfeifer.com>
621 631
622 * doc/cpp.texi (Obsolete Features): Add background on the 632 * doc/cpp.texi (Obsolete Features): Add background on the
623 origin of assertions. 633 origin of assertions.
624 Update copyright years. 634 Update copyright years.
625 635
6262011-02-25 Andriy Gapon <avg@freebsd.org> 6362011-02-25 Andriy Gapon <avg@freebsd.org>
627 637
628 PR target/45808 638 PR target/45808
629 * config/freebsd-spec.h (FBSD_LIB_SPEC): Handle the shared case. 639 * config/freebsd-spec.h (FBSD_LIB_SPEC): Handle the shared case.
630 Update copyright years. 640 Update copyright years.
631 641
6322011-02-21 Uros Bizjak <ubizjak@gmail.com> 6422011-02-21 Uros Bizjak <ubizjak@gmail.com>
633 643
634 PR target/47840 644 PR target/47840
635 * config/i386/avxintrin.h (_mm256_insert_epi32): Use _mm_insert_epi32. 645 * config/i386/avxintrin.h (_mm256_insert_epi32): Use _mm_insert_epi32.
636 (_mm256_insert_epi64): Use _mm_insert_epi64. 646 (_mm256_insert_epi64): Use _mm_insert_epi64.
637 647
6382011-02-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 6482011-02-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
639 649
640 * config.gcc (hppa[12]*-*-hpux11*): Set extra_parts. 650 * config.gcc (hppa[12]*-*-hpux11*): Set extra_parts.
641 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, 651 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
642 pthread_mutex_unlock, pthread_once): Reinstate pthread stubs. 652 pthread_mutex_unlock, pthread_once): Reinstate pthread stubs.
643 * config/pa/t-pa-hpux11: Add rules to build pthread stubs. 653 * config/pa/t-pa-hpux11: Add rules to build pthread stubs.
644 * config/pa/t-pa64: Likewise. 654 * config/pa/t-pa64: Likewise.
645 * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Define. 655 * config/pa/pa-hpux11.h (LINK_GCC_C_SEQUENCE_SPEC): Define.
646 656
6472011-02-17 Uros Bizjak <ubizjak@gmail.com> 6572011-02-17 Uros Bizjak <ubizjak@gmail.com>
648 658
649 PR target/43653 659 PR target/43653
650 * config/i386/i386.c (ix86_secondary_reload): Handle SSE 660 * config/i386/i386.c (ix86_secondary_reload): Handle SSE
651 input reload with PLUS RTX. 661 input reload with PLUS RTX.
652 662
6532011-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> 6632011-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
654 664
655 PR pch/14940 665 PR pch/14940
656 * config/alpha/host-osf.c: New file. 666 * config/alpha/host-osf.c: New file.
657 * config/alpha/x-osf: New file. 667 * config/alpha/x-osf: New file.
658 * config.host (alpha*-dec-osf*): Use it. 668 * config.host (alpha*-dec-osf*): Use it.
659 669
6602011-02-15 Tijl Coosemans <tijl@coosemans.org> 6702011-02-15 Tijl Coosemans <tijl@coosemans.org>
661 671
662 * config/i386/freebsd.h (SUBTARGET32_DEFAULT_CPU): Add. 672 * config/i386/freebsd.h (SUBTARGET32_DEFAULT_CPU): Add.
663 Update copyright years. 673 Update copyright years.
664 674
6652011-02-11 Bernd Schmidt <bernds@codesourcery.com> 6752011-02-11 Bernd Schmidt <bernds@codesourcery.com>
666 676
667 PR rtl-optimization/47166 677 PR rtl-optimization/47166
668 * reload1.c (emit_reload_insns): Disable the spill_reg_store 678 * reload1.c (emit_reload_insns): Disable the spill_reg_store
669 mechanism for PRE_MODIFY and POST_MODIFY. 679 mechanism for PRE_MODIFY and POST_MODIFY.
670 (inc_for_reload): For PRE_MODIFY, return the insn that sets the 680 (inc_for_reload): For PRE_MODIFY, return the insn that sets the
671 reloadreg. 681 reloadreg.
672 682
6732011-02-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 6832011-02-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
674 684
675 Backport from mainline: 685 Backport from mainline:
676 2011-02-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 686 2011-02-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
677 687
678 * config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts. 688 * config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts.
679 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, 689 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
680 pthread_mutex_unlock): Remove. 690 pthread_mutex_unlock): Remove.
681 * config/pa/t-pa-hpux11: Remove rules to build pthread stubs. 691 * config/pa/t-pa-hpux11: Remove rules to build pthread stubs.
682 * config/pa/t-pa64: Likewise. 692 * config/pa/t-pa64: Likewise.
683 * config/pa/pa64-hpux.h (LIB_SPEC): In static links, link against 693 * config/pa/pa64-hpux.h (LIB_SPEC): In static links, link against
684 shared libc if not linking against libpthread. 694 shared libc if not linking against libpthread.
685 * config/pa/pa-hpux11.h (LIB_SPEC): Likewise. 695 * config/pa/pa-hpux11.h (LIB_SPEC): Likewise.
686 696
6872011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com> 6972011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com>
688 698
689 Backport from mainline: 699 Backport from mainline:
690 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com> 700 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com>
691 701
692 PR target/47272 702 PR target/47272
693 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): 703 * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
694 Document using vector double with the load/store builtins, and 704 Document using vector double with the load/store builtins, and
695 that the load/store builtins always use Altivec instructions. 705 that the load/store builtins always use Altivec instructions.
696 706
697 * config/rs6000/vector.md (vector_altivec_load_<mode>): New insns 707 * config/rs6000/vector.md (vector_altivec_load_<mode>): New insns
698 to use altivec memory instructions, even on VSX. 708 to use altivec memory instructions, even on VSX.
699 (vector_altivec_store_<mode>): Ditto. 709 (vector_altivec_store_<mode>): Ditto.
700 710
701 * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New 711 * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New
702 function. 712 function.
703 713
704 * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add 714 * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
705 V2DF, V2DI support to load/store overloaded builtins. 715 V2DF, V2DI support to load/store overloaded builtins.
706 716
707 * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add 717 * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add
708 altivec load/store builtins for V2DF/V2DI types. 718 altivec load/store builtins for V2DF/V2DI types.
709 719
710 * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't 720 * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
711 set avoid indexed addresses on power6 if -maltivec. 721 set avoid indexed addresses on power6 if -maltivec.
712 (altivec_expand_ld_builtin): Add V2DF, V2DI support, use 722 (altivec_expand_ld_builtin): Add V2DF, V2DI support, use
713 vector_altivec_load/vector_altivec_store builtins. 723 vector_altivec_load/vector_altivec_store builtins.
714 (altivec_expand_st_builtin): Ditto. 724 (altivec_expand_st_builtin): Ditto.
715 (altivec_expand_builtin): Add VSX memory builtins. 725 (altivec_expand_builtin): Add VSX memory builtins.
716 (rs6000_init_builtins): Add V2DI types to internal types. 726 (rs6000_init_builtins): Add V2DI types to internal types.
717 (altivec_init_builtins): Add support for V2DF/V2DI altivec 727 (altivec_init_builtins): Add support for V2DF/V2DI altivec
718 load/store builtins. 728 load/store builtins.
719 (rs6000_address_for_altivec): Insure memory address is appropriate 729 (rs6000_address_for_altivec): Insure memory address is appropriate
720 for Altivec. 730 for Altivec.
721 731
722 * config/rs6000/vsx.md (vsx_load_<mode>): New expanders for 732 * config/rs6000/vsx.md (vsx_load_<mode>): New expanders for
723 vec_vsx_ld and vec_vsx_st. 733 vec_vsx_ld and vec_vsx_st.
724 (vsx_store_<mode>): Ditto. 734 (vsx_store_<mode>): Ditto.
725 735
726 * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type 736 * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type
727 variables to hold long long types for VSX vector memory builtins. 737 variables to hold long long types for VSX vector memory builtins.
728 (RS6000_BTI_unsigned_long_long): Ditto. 738 (RS6000_BTI_unsigned_long_long): Ditto.
729 (long_long_integer_type_internal_node): Ditti. 739 (long_long_integer_type_internal_node): Ditti.
730 (long_long_unsigned_type_internal_node): Ditti. 740 (long_long_unsigned_type_internal_node): Ditti.
731 741
732 * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC. 742 * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC.
733 (altivec_lvx_<mode>): Make altivec_lvx use a mode iterator. 743 (altivec_lvx_<mode>): Make altivec_lvx use a mode iterator.
734 (altivec_stvx_<mode>): Make altivec_stvx use a mode iterator. 744 (altivec_stvx_<mode>): Make altivec_stvx use a mode iterator.
735 745
736 * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin 746 * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin
737 short cuts. 747 short cuts.
738 (vec_vsx_st): Ditto. 748 (vec_vsx_st): Ditto.
739 749
740 Backport from mainline: 750 Backport from mainline:
741 2011-02-01 Michael Meissner <meissner@linux.vnet.ibm.com> 751 2011-02-01 Michael Meissner <meissner@linux.vnet.ibm.com>
742 752
743 PR target/47580 753 PR target/47580
744 * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use 754 * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use
745 gpc_reg_operand instead of vsx_register_operand to match rs6000.md 755 gpc_reg_operand instead of vsx_register_operand to match rs6000.md
746 generator functions. 756 generator functions.
747 (vsx_floatuns<VSi><mode>2): Ditto. 757 (vsx_floatuns<VSi><mode>2): Ditto.
748 (vsx_fix_trunc<mode><VSi>2): Ditto. 758 (vsx_fix_trunc<mode><VSi>2): Ditto.
749 (vsx_fixuns_trunc<mode><VSi>2): Ditto. 759 (vsx_fixuns_trunc<mode><VSi>2): Ditto.
750 760
7512011-02-02 Nick Clifton <nickc@redhat.com> 7612011-02-02 Nick Clifton <nickc@redhat.com>
752 762
753 Import these patches from the mainline: 763 Import these patches from the mainline:
754 2011-01-31 Nick Clifton <nickc@redhat.com> 764 2011-01-31 Nick Clifton <nickc@redhat.com>
755 765
756 * config/rx/rx.c (rx_get_stack_layout): Only save call clobbered 766 * config/rx/rx.c (rx_get_stack_layout): Only save call clobbered
757 registers inside interrupt handlers if the handler is not a leaf 767 registers inside interrupt handlers if the handler is not a leaf
758 function. 768 function.
759 769
760 2011-01-25 Nick Clifton <nickc@redhat.com> 770 2011-01-25 Nick Clifton <nickc@redhat.com>
761 771
762 * config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types. 772 * config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types.
763 * config/rx/rx.c (rx_function_value): Likewise. 773 * config/rx/rx.c (rx_function_value): Likewise.
764 (rx_promote_function_mode): Likewise. 774 (rx_promote_function_mode): Likewise.
765 (gen_safe_add): Place an outsized immediate value inside an UNSPEC 775 (gen_safe_add): Place an outsized immediate value inside an UNSPEC
766 in order to make it legitimate. 776 in order to make it legitimate.
767 * config/rx/rx.md (adddi3_internal): If the second operand is a 777 * config/rx/rx.md (adddi3_internal): If the second operand is a
768 MEM make sure that the first operand is the same as the result 778 MEM make sure that the first operand is the same as the result
769 register. 779 register.
770 (addsi3_unspec): Delete. 780 (addsi3_unspec): Delete.
771 (subdi3): Do not accept immediate operands. 781 (subdi3): Do not accept immediate operands.
772 (subdi3_internal): Likewise. 782 (subdi3_internal): Likewise.
773 783
774 2011-01-24 Richard Henderson <rth@redhat.com> 784 2011-01-24 Richard Henderson <rth@redhat.com>
775 785
776 * config/rx/predicates.md (rx_fp_comparison_operator): Don't accept 786 * config/rx/predicates.md (rx_fp_comparison_operator): Don't accept
777 compound unordered comparisons. 787 compound unordered comparisons.
778 * config/rx/rx.c (rx_split_fp_compare): Remove. 788 * config/rx/rx.c (rx_split_fp_compare): Remove.
779 * config/rx/rx-protos.h: Update. 789 * config/rx/rx-protos.h: Update.
780 * config/rx/rx.md (gcc_conds, rx_conds): Remove. 790 * config/rx/rx.md (gcc_conds, rx_conds): Remove.
781 (cbranchsf4): Don't call rx_split_fp_compare. 791 (cbranchsf4): Don't call rx_split_fp_compare.
782 (*cbranchsf4): Use rx_split_cbranch. 792 (*cbranchsf4): Use rx_split_cbranch.
783 (*cmpsf): Don't accept "i" constraint. 793 (*cmpsf): Don't accept "i" constraint.
784 (*conditional_branch): Only valid after reload. 794 (*conditional_branch): Only valid after reload.
785 (cstoresf4): Merge expander with insn. Don't call 795 (cstoresf4): Merge expander with insn. Don't call
786 rx_split_fp_compare. 796 rx_split_fp_compare.
787 797
788 2011-01-22 Nick Clifton <nickc@redhat.com> 798 2011-01-22 Nick Clifton <nickc@redhat.com>
789 799
790 * config/rx/rx.md (cstoresf4): Pass comparison operator to 800 * config/rx/rx.md (cstoresf4): Pass comparison operator to
791 rx_split_fp_compare. 801 rx_split_fp_compare.
792 802
793 2011-01-22 Nick Clifton <nickc@redhat.com> 803 2011-01-22 Nick Clifton <nickc@redhat.com>
794 804
795 * config/rx/rx.md (UNSPEC_CONST): New. 805 * config/rx/rx.md (UNSPEC_CONST): New.
796 (deallocate_and_return): Wrap the amount popped off the stack in 806 (deallocate_and_return): Wrap the amount popped off the stack in
797 an UNSPEC_CONST in order to stop it being rejected by 807 an UNSPEC_CONST in order to stop it being rejected by
798 -mmax-constant-size. 808 -mmax-constant-size.
799 (pop_and_return): Add a "(return)" rtx. 809 (pop_and_return): Add a "(return)" rtx.
800 (call): Drop the immediate operand. 810 (call): Drop the immediate operand.
801 (call_internal): Likewise. 811 (call_internal): Likewise.
802 (call_value): Likewise. 812 (call_value): Likewise.
803 (call_value_internal): Likewise. 813 (call_value_internal): Likewise.
804 (sibcall_internal): Likewise. 814 (sibcall_internal): Likewise.
805 (sibcall_value_internal): Likewise. 815 (sibcall_value_internal): Likewise.
806 (sibcall): Likewise. Generate an explicit call using 816 (sibcall): Likewise. Generate an explicit call using
807 sibcall_internal. 817 sibcall_internal.
808 (sibcall_value): Likewise. 818 (sibcall_value): Likewise.
809 (mov<>): FAIL if a constant operand is not legitimate. 819 (mov<>): FAIL if a constant operand is not legitimate.
810 (addsi3_unpsec): New pattern. 820 (addsi3_unpsec): New pattern.
811 821
812 * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC 822 * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC
813 CONSTs. 823 CONSTs.
814 (ok_for_max_constant): New function. 824 (ok_for_max_constant): New function.
815 (gen_safe_add): New function. 825 (gen_safe_add): New function.
816 (rx_expand_prologue): Use gen_safe_add. 826 (rx_expand_prologue): Use gen_safe_add.
817 (rx_expand_epilogue): Likewise. 827 (rx_expand_epilogue): Likewise.
818 (rx_is_legitimate_constant): Use ok_for_max_constant. Handle 828 (rx_is_legitimate_constant): Use ok_for_max_constant. Handle
819 UNSPEC CONSTs. 829 UNSPEC CONSTs.
820 830
821 2011-01-17 Richard Henderson <rth@redhat.com> 831 2011-01-17 Richard Henderson <rth@redhat.com>
822 832
823 * config/rx/predicates.md (rx_constshift_operand): Use match_test. 833 * config/rx/predicates.md (rx_constshift_operand): Use match_test.
824 (rx_restricted_mem_operand): New. 834 (rx_restricted_mem_operand): New.
825 (rx_shift_operand): Use register_operand. 835 (rx_shift_operand): Use register_operand.
826 (rx_source_operand, rx_compare_operand): Likewise. 836 (rx_source_operand, rx_compare_operand): Likewise.
827 * config/rx/rx.md (addsi3_flags): New expander. 837 * config/rx/rx.md (addsi3_flags): New expander.
828 (adddi3): Rewrite as expander. 838 (adddi3): Rewrite as expander.
829 (adc_internal, *adc_flags, adddi3_internal): New patterns. 839 (adc_internal, *adc_flags, adddi3_internal): New patterns.
830 (subsi3_flags): New expander. 840 (subsi3_flags): New expander.
831 (subdi3): Rewrite as expander. 841 (subdi3): Rewrite as expander.
832 (sbb_internal, *sbb_flags, subdi3_internal): New patterns. 842 (sbb_internal, *sbb_flags, subdi3_internal): New patterns.
833 843
834 * config/rx/rx.c (RX_BUILTIN_SAT): Remove. 844 * config/rx/rx.c (RX_BUILTIN_SAT): Remove.
835 (rx_init_builtins): Remove sat builtin. 845 (rx_init_builtins): Remove sat builtin.
836 (rx_expand_builtin): Likewise. 846 (rx_expand_builtin): Likewise.
837 * config/rx/rx.md (ssaddsi3): New. 847 * config/rx/rx.md (ssaddsi3): New.
838 (*sat): Rename from sat. Represent the CC_REG input. 848 (*sat): Rename from sat. Represent the CC_REG input.
839 849
840 * config/rx/predicates.md (rshift_operator): New. 850 * config/rx/predicates.md (rshift_operator): New.
841 * config/rx/rx.c (rx_expand_insv): Remove. 851 * config/rx/rx.c (rx_expand_insv): Remove.
842 * config/rx/rx-protos.h: Update. 852 * config/rx/rx-protos.h: Update.
843 * config/rx/rx.md (*bitset): Rename from bitset. Swap the ashift 853 * config/rx/rx.md (*bitset): Rename from bitset. Swap the ashift
844 operand to the canonical position. 854 operand to the canonical position.
845 (*bitset_in_memory, *bitinvert, *bitinvert_in_memory): Similarly. 855 (*bitset_in_memory, *bitinvert, *bitinvert_in_memory): Similarly.
846 (*bitclr, *bitclr_in_memory): Similarly. 856 (*bitclr, *bitclr_in_memory): Similarly.
847 (*insv_imm, rx_insv_reg, *insv_cond, *bmcc, *insv_cond_lt): New. 857 (*insv_imm, rx_insv_reg, *insv_cond, *bmcc, *insv_cond_lt): New.
848 (insv): Retain the zero_extract in the expansion. 858 (insv): Retain the zero_extract in the expansion.
849 859
850 * config/rx/rx.md (bswapsi2): Use = not + for output reload. 860 * config/rx/rx.md (bswapsi2): Use = not + for output reload.
851 (bswaphi2, bitinvert, revw): Likewise. 861 (bswaphi2, bitinvert, revw): Likewise.
852 862
853 * config/rx/rx.c (gen_rx_store_vector): Use VOIDmode for gen_rtx_SET. 863 * config/rx/rx.c (gen_rx_store_vector): Use VOIDmode for gen_rtx_SET.
854 (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise. 864 (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
855 * config/rx/rx.md (pop_and_return): Use VOIDmode for SET. 865 * config/rx/rx.md (pop_and_return): Use VOIDmode for SET.
856 (stack_push, stack_pushm, stack_pop, stack_popm): Likewise. 866 (stack_push, stack_pushm, stack_pop, stack_popm): Likewise.
857 (bitset, bitset_in_memory): Likewise. 867 (bitset, bitset_in_memory): Likewise.
858 (bitinvert, bitinvert_in_memory): Likewise. 868 (bitinvert, bitinvert_in_memory): Likewise.
859 (bitclr, bitclr_in_memory): Likewise. 869 (bitclr, bitclr_in_memory): Likewise.
860 (insv, sync_lock_test_and_setsi, movstr, rx_movstr): Likewise. 870 (insv, sync_lock_test_and_setsi, movstr, rx_movstr): Likewise.
861 (rx_strend, rx_cmpstrn): Likewise. 871 (rx_strend, rx_cmpstrn): Likewise.
862 (rx_setmem): Likewise. Make the source BLKmode to match the dest. 872 (rx_setmem): Likewise. Make the source BLKmode to match the dest.
863 (bitop peep2 patterns): Remove. 873 (bitop peep2 patterns): Remove.
864 874
865 * config/rx/rx.c (rx_match_ccmode): New. 875 * config/rx/rx.c (rx_match_ccmode): New.
866 * config/rx/rx-protos.h: Update. 876 * config/rx/rx-protos.h: Update.
867 * config/rx/rx.md (abssi2): Clobber, don't set flags. 877 * config/rx/rx.md (abssi2): Clobber, don't set flags.
868 (addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise. 878 (addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise.
869 (rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise. 879 (rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise.
870 (subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise. 880 (subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise.
871 (fix_truncsfsi2, floatsisf2): Likewise. 881 (fix_truncsfsi2, floatsisf2): Likewise.
872 (*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New. 882 (*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New.
873 (*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New. 883 (*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New.
874 (*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New. 884 (*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New.
875 (*subsi3_flags, *xorsi3_flags): New. 885 (*subsi3_flags, *xorsi3_flags): New.
876 886
877 * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns. 887 * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns.
878 888
879 * config/rx/rx.c (rx_print_operand): Remove workaround for 889 * config/rx/rx.c (rx_print_operand): Remove workaround for
880 unsplit comparison operations. 890 unsplit comparison operations.
881 891
882 * config/rx/rx.md (movsicc): Split after reload. 892 * config/rx/rx.md (movsicc): Split after reload.
883 (*movsicc): Merge *movsieq and *movsine via match_operator. 893 (*movsicc): Merge *movsieq and *movsine via match_operator.
884 (*stcc): New pattern. 894 (*stcc): New pattern.
885 895
886 * config/rx/rx.c (rx_float_compare_mode): Remove. 896 * config/rx/rx.c (rx_float_compare_mode): Remove.
887 * config/rx/rx.h (rx_float_compare_mode): Remove. 897 * config/rx/rx.h (rx_float_compare_mode): Remove.
888 * config/rx/rx.md (cstoresi4): Split after reload. 898 * config/rx/rx.md (cstoresi4): Split after reload.
889 (*sccc): New pattern. 899 (*sccc): New pattern.
890 900
891 * config/rx/predicates.md (label_ref_operand): New. 901 * config/rx/predicates.md (label_ref_operand): New.
892 (rx_z_comparison_operator): New. 902 (rx_z_comparison_operator): New.
893 (rx_zs_comparison_operator): New. 903 (rx_zs_comparison_operator): New.
894 (rx_fp_comparison_operator): New. 904 (rx_fp_comparison_operator): New.
895 * config/rx/rx.c (rx_print_operand) [B]: Examine comparison modes. 905 * config/rx/rx.c (rx_print_operand) [B]: Examine comparison modes.
896 Validate that the flags are set properly for the comparison. 906 Validate that the flags are set properly for the comparison.
897 (rx_gen_cond_branch_template): Remove. 907 (rx_gen_cond_branch_template): Remove.
898 (rx_cc_modes_compatible): Remove. 908 (rx_cc_modes_compatible): Remove.
899 (mode_from_flags): New. 909 (mode_from_flags): New.
900 (flags_from_code): Rename from flags_needed_for_conditional. 910 (flags_from_code): Rename from flags_needed_for_conditional.
901 (rx_cc_modes_compatible): Re-write in terms of flags_from_mode. 911 (rx_cc_modes_compatible): Re-write in terms of flags_from_mode.
902 (rx_select_cc_mode): Likewise. 912 (rx_select_cc_mode): Likewise.
903 (rx_split_fp_compare): New. 913 (rx_split_fp_compare): New.
904 (rx_split_cbranch): New. 914 (rx_split_cbranch): New.
905 * config/rx/rx.md (most_cond, zs_cond): Remove iterators. 915 * config/rx/rx.md (most_cond, zs_cond): Remove iterators.
906 (*cbranchsi4): Use match_operator and rx_split_cbranch. 916 (*cbranchsi4): Use match_operator and rx_split_cbranch.
907 (*cbranchsf4): Similarly. 917 (*cbranchsf4): Similarly.
908 (*cbranchsi4_tst): Rename from *tstbranchsi4_<code>. Use 918 (*cbranchsi4_tst): Rename from *tstbranchsi4_<code>. Use
909 match_operator and rx_split_cbranch. 919 match_operator and rx_split_cbranch.
910 (*cbranchsi4_tst_ext): Combine *tstbranchsi4m_eq and 920 (*cbranchsi4_tst_ext): Combine *tstbranchsi4m_eq and
911 tstbranchsi4m_ne. Use match_operator and rx_split_cbranch. 921 tstbranchsi4m_ne. Use match_operator and rx_split_cbranch.
912 (*cmpsi): Rename from cmpsi. 922 (*cmpsi): Rename from cmpsi.
913 (*tstsi): Rename from tstsi. 923 (*tstsi): Rename from tstsi.
914 (*cmpsf): Rename from cmpsf; use CC_Fmode. 924 (*cmpsf): Rename from cmpsf; use CC_Fmode.
915 (*conditional_branch): Rename from conditional_branch. 925 (*conditional_branch): Rename from conditional_branch.
916 (*reveresed_conditional_branch): Remove. 926 (*reveresed_conditional_branch): Remove.
917 (b<code>): Remove expander. 927 (b<code>): Remove expander.
918 * config/rx/rx-protos.h: Update. 928 * config/rx/rx-protos.h: Update.
919 929
920 * config/rx/rx.c (rx_compare_redundant): Remove. 930 * config/rx/rx.c (rx_compare_redundant): Remove.
921 * config/rx/rx.md (cmpsi): Don't use it. 931 * config/rx/rx.md (cmpsi): Don't use it.
922 * config/rx/rx-protos.h: Update. 932 * config/rx/rx-protos.h: Update.
923 933
924 * config/rx/rx-modes.def (CC_F): New mode. 934 * config/rx/rx-modes.def (CC_F): New mode.
925 * config/rx/rx.c (rx_select_cc_mode): New. 935 * config/rx/rx.c (rx_select_cc_mode): New.
926 * config/rx/rx.h (SELECT_CC_MODE): Use it. 936 * config/rx/rx.h (SELECT_CC_MODE): Use it.
927 * config/rx/rx-protos.h: Update. 937 * config/rx/rx-protos.h: Update.
928 938
9292011-02-01 Richard Guenther <rguenther@suse.de> 9392011-02-01 Richard Guenther <rguenther@suse.de>
930 940
931 PR tree-optimization/47541 941 PR tree-optimization/47541
932 * tree-ssa-structalias.c (push_fields_onto_fieldstack): Make 942 * tree-ssa-structalias.c (push_fields_onto_fieldstack): Make
933 sure to have a field at offset zero. 943 sure to have a field at offset zero.
934 944
9352011-01-31 Nathan Froyd <froydnj@codesourcery.com> 9452011-01-31 Nathan Froyd <froydnj@codesourcery.com>
936 946
937 Backport from mainline: 947 Backport from mainline:
938 2010-12-30 Nathan Froyd <froydnj@codesourcery.com> 948 2010-12-30 Nathan Froyd <froydnj@codesourcery.com>
939 949
940 PR target/44606 950 PR target/44606
941 * reload1.c (choose_reload_regs): Don't look for equivalences for 951 * reload1.c (choose_reload_regs): Don't look for equivalences for
942 output reloads of constant loads. 952 output reloads of constant loads.
943 953
9442011-01-30 Gerald Pfeifer <gerald@pfeifer.com> 9542011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
945 955
946 * doc/install.texi (hppa-hp-hpux10): Remove references to HP 956 * doc/install.texi (hppa-hp-hpux10): Remove references to HP
947 support sites. 957 support sites.
948 958
9492011-01-30 Gerald Pfeifer <gerald@pfeifer.com> 9592011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
950 960
951 * doc/install.texi: Update copyright years. 961 * doc/install.texi: Update copyright years.
952 962
9532011-01-30 Gerald Pfeifer <gerald@pfeifer.com> 9632011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
954 964
955 * doc/install.texi (Binaries): Remove outdated reference for 965 * doc/install.texi (Binaries): Remove outdated reference for
956 Motorola 68HC11/68HC12 downloads. 966 Motorola 68HC11/68HC12 downloads.
957 967
9582011-01-30 Gerald Pfeifer <gerald@pfeifer.com> 9682011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
959 969
960 * doc/extend.texi (Thread-Local): Adjust reference to Ulrich 970 * doc/extend.texi (Thread-Local): Adjust reference to Ulrich
961 Drepper's paper. 971 Drepper's paper.
962 972
9632011-01-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 9732011-01-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
964 974
965 Backport from mainline: 975 Backport from mainline:
966 2010-08-22 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> 976 2010-08-22 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
967 977
968 PR boehm-gc/34544 978 PR boehm-gc/34544
969 * gthr-posix.h (__gthread_active_init): Delete. 979 * gthr-posix.h (__gthread_active_init): Delete.
970 (__gthread_active_p): Do activity check here. 980 (__gthread_active_p): Do activity check here.
971 Don't include errno.h on hppa-hpux. Update comment. 981 Don't include errno.h on hppa-hpux. Update comment.
972 * gthr-posix95.h (__gthread_active_init): Delete. 982 * gthr-posix95.h (__gthread_active_init): Delete.
973 (__gthread_active_p): Do activity check here. 983 (__gthread_active_p): Do activity check here.
974 Don't include errno.h on hppa-hpux. Update comment. 984 Don't include errno.h on hppa-hpux. Update comment.
975 * config.gcc (hppa[12]*-*-hpux11*): Define extra_parts. 985 * config.gcc (hppa[12]*-*-hpux11*): Define extra_parts.
976 * config/pa/pa64-hpux.h (LIB_SPEC): When -static is specified, only 986 * config/pa/pa64-hpux.h (LIB_SPEC): When -static is specified, only
977 add -lpthread when -mt or -pthread is specified. 987 add -lpthread when -mt or -pthread is specified.
978 * config/pa/pa-hpux11.h (LIB_SPEC): likewise. 988 * config/pa/pa-hpux11.h (LIB_SPEC): likewise.
979 (LINK_GCC_C_SEQUENCE_SPEC): Define. 989 (LINK_GCC_C_SEQUENCE_SPEC): Define.
980 * config/pa/t-pa-hpux11 (LIBGCCSTUB_OBJS): Define. 990 * config/pa/t-pa-hpux11 (LIBGCCSTUB_OBJS): Define.
981 (stublib.c, pthread_default_stacksize_np-stub.o, 991 (stublib.c, pthread_default_stacksize_np-stub.o,
982 pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o, 992 pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o,
983 $(T)libgcc_stub.a): Add methods. 993 $(T)libgcc_stub.a): Add methods.
984 * config/pa/t-pa64 (LIBGCCSTUB_OBJS): Add pthread stubs. 994 * config/pa/t-pa64 (LIBGCCSTUB_OBJS): Add pthread stubs.
985 (stublib.c, pthread_default_stacksize_np-stub.o, 995 (stublib.c, pthread_default_stacksize_np-stub.o,
986 pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o): Add methods. 996 pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o): Add methods.
987 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock, 997 * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
988 pthread_mutex_unlock): New stubs. 998 pthread_mutex_unlock): New stubs.
989 999
9902011-01-26 Eric Botcazou <ebotcazou@adacore.com> 10002011-01-26 Eric Botcazou <ebotcazou@adacore.com>
991 1001
992 PR rtl-optimization/44469 1002 PR rtl-optimization/44469
993 * cfgcleanup.c (try_optimize_cfg): Iterate in CFG layout mode too 1003 * cfgcleanup.c (try_optimize_cfg): Iterate in CFG layout mode too
994 after removing trivially dead basic blocks. 1004 after removing trivially dead basic blocks.
995 1005
9962011-01-25 Richard Guenther <rguenther@suse.de> 10062011-01-25 Richard Guenther <rguenther@suse.de>
997 1007
998 PR tree-optimization/47411 1008 PR tree-optimization/47411
999 Backport from mainline 1009 Backport from mainline
cvs diff -r1.1.1.1 -r1.2 src/external/gpl3/gcc/dist/gcc/config/arm/arm.md (switch to unified diff)

--- src/external/gpl3/gcc/dist/gcc/config/arm/arm.md 2011/06/21 01:22:22 1.1.1.1
+++ src/external/gpl3/gcc/dist/gcc/config/arm/arm.md 2012/09/16 07:26:31 1.2
@@ -2138,1999 +2138,1999 @@ @@ -2138,1999 +2138,1999 @@
2138 && !reg_overlap_mentioned_p (operands[0], operands[4])" 2138 && !reg_overlap_mentioned_p (operands[0], operands[4])"
2139 [(parallel [(set (reg:CC_NOOV CC_REGNUM) 2139 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2140 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) 2140 (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2))
2141 (const_int 0))) 2141 (const_int 0)))
2142 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) 2142 (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))])
2143 (set (match_dup 0) 2143 (set (match_dup 0)
2144 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) 2144 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2145 (match_dup 0) (match_dup 4)))] 2145 (match_dup 0) (match_dup 4)))]
2146 " 2146 "
2147 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) 2147 operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1)
2148 << INTVAL (operands[3]));  2148 << INTVAL (operands[3]));
2149 " 2149 "
2150 [(set_attr "conds" "clob") 2150 [(set_attr "conds" "clob")
2151 (set_attr "length" "8")] 2151 (set_attr "length" "8")]
2152) 2152)
2153 2153
2154(define_insn_and_split "*ite_ne_zeroextractsi_shifted" 2154(define_insn_and_split "*ite_ne_zeroextractsi_shifted"
2155 [(set (match_operand:SI 0 "s_register_operand" "=r") 2155 [(set (match_operand:SI 0 "s_register_operand" "=r")
2156 (if_then_else:SI (ne (zero_extract:SI 2156 (if_then_else:SI (ne (zero_extract:SI
2157 (match_operand:SI 1 "s_register_operand" "r") 2157 (match_operand:SI 1 "s_register_operand" "r")
2158 (match_operand:SI 2 "const_int_operand" "n") 2158 (match_operand:SI 2 "const_int_operand" "n")
2159 (const_int 0)) 2159 (const_int 0))
2160 (const_int 0)) 2160 (const_int 0))
2161 (match_operand:SI 3 "arm_not_operand" "rIK") 2161 (match_operand:SI 3 "arm_not_operand" "rIK")
2162 (const_int 0))) 2162 (const_int 0)))
2163 (clobber (reg:CC CC_REGNUM))] 2163 (clobber (reg:CC CC_REGNUM))]
2164 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" 2164 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2165 "#" 2165 "#"
2166 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" 2166 "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])"
2167 [(parallel [(set (reg:CC_NOOV CC_REGNUM) 2167 [(parallel [(set (reg:CC_NOOV CC_REGNUM)
2168 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) 2168 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
2169 (const_int 0))) 2169 (const_int 0)))
2170 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) 2170 (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))])
2171 (set (match_dup 0) 2171 (set (match_dup 0)
2172 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) 2172 (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0))
2173 (match_dup 0) (match_dup 3)))] 2173 (match_dup 0) (match_dup 3)))]
2174 " 2174 "
2175 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 2175 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2176 " 2176 "
2177 [(set_attr "conds" "clob") 2177 [(set_attr "conds" "clob")
2178 (set_attr "length" "8")] 2178 (set_attr "length" "8")]
2179) 2179)
2180 2180
2181(define_split 2181(define_split
2182 [(set (match_operand:SI 0 "s_register_operand" "") 2182 [(set (match_operand:SI 0 "s_register_operand" "")
2183 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "") 2183 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "")
2184 (match_operand:SI 2 "const_int_operand" "") 2184 (match_operand:SI 2 "const_int_operand" "")
2185 (match_operand:SI 3 "const_int_operand" ""))) 2185 (match_operand:SI 3 "const_int_operand" "")))
2186 (clobber (match_operand:SI 4 "s_register_operand" ""))] 2186 (clobber (match_operand:SI 4 "s_register_operand" ""))]
2187 "TARGET_THUMB1" 2187 "TARGET_THUMB1"
2188 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 2))) 2188 [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 2)))
2189 (set (match_dup 0) (lshiftrt:SI (match_dup 4) (match_dup 3)))] 2189 (set (match_dup 0) (lshiftrt:SI (match_dup 4) (match_dup 3)))]
2190 "{ 2190 "{
2191 HOST_WIDE_INT temp = INTVAL (operands[2]); 2191 HOST_WIDE_INT temp = INTVAL (operands[2]);
2192 2192
2193 operands[2] = GEN_INT (32 - temp - INTVAL (operands[3])); 2193 operands[2] = GEN_INT (32 - temp - INTVAL (operands[3]));
2194 operands[3] = GEN_INT (32 - temp); 2194 operands[3] = GEN_INT (32 - temp);
2195 }" 2195 }"
2196) 2196)
2197 2197
2198;; ??? Use Thumb-2 has bitfield insert/extract instructions. 2198;; ??? Use Thumb-2 has bitfield insert/extract instructions.
2199(define_split 2199(define_split
2200 [(set (match_operand:SI 0 "s_register_operand" "") 2200 [(set (match_operand:SI 0 "s_register_operand" "")
2201 (match_operator:SI 1 "shiftable_operator" 2201 (match_operator:SI 1 "shiftable_operator"
2202 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "") 2202 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
2203 (match_operand:SI 3 "const_int_operand" "") 2203 (match_operand:SI 3 "const_int_operand" "")
2204 (match_operand:SI 4 "const_int_operand" "")) 2204 (match_operand:SI 4 "const_int_operand" ""))
2205 (match_operand:SI 5 "s_register_operand" "")])) 2205 (match_operand:SI 5 "s_register_operand" "")]))
2206 (clobber (match_operand:SI 6 "s_register_operand" ""))] 2206 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2207 "TARGET_ARM" 2207 "TARGET_ARM"
2208 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3))) 2208 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2209 (set (match_dup 0) 2209 (set (match_dup 0)
2210 (match_op_dup 1 2210 (match_op_dup 1
2211 [(lshiftrt:SI (match_dup 6) (match_dup 4)) 2211 [(lshiftrt:SI (match_dup 6) (match_dup 4))
2212 (match_dup 5)]))] 2212 (match_dup 5)]))]
2213 "{ 2213 "{
2214 HOST_WIDE_INT temp = INTVAL (operands[3]); 2214 HOST_WIDE_INT temp = INTVAL (operands[3]);
2215 2215
2216 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4])); 2216 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2217 operands[4] = GEN_INT (32 - temp); 2217 operands[4] = GEN_INT (32 - temp);
2218 }" 2218 }"
2219) 2219)
2220  2220
2221(define_split 2221(define_split
2222 [(set (match_operand:SI 0 "s_register_operand" "") 2222 [(set (match_operand:SI 0 "s_register_operand" "")
2223 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "") 2223 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "")
2224 (match_operand:SI 2 "const_int_operand" "") 2224 (match_operand:SI 2 "const_int_operand" "")
2225 (match_operand:SI 3 "const_int_operand" "")))] 2225 (match_operand:SI 3 "const_int_operand" "")))]
2226 "TARGET_THUMB1" 2226 "TARGET_THUMB1"
2227 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) 2227 [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
2228 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 3)))] 2228 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 3)))]
2229 "{ 2229 "{
2230 HOST_WIDE_INT temp = INTVAL (operands[2]); 2230 HOST_WIDE_INT temp = INTVAL (operands[2]);
2231 2231
2232 operands[2] = GEN_INT (32 - temp - INTVAL (operands[3])); 2232 operands[2] = GEN_INT (32 - temp - INTVAL (operands[3]));
2233 operands[3] = GEN_INT (32 - temp); 2233 operands[3] = GEN_INT (32 - temp);
2234 }" 2234 }"
2235) 2235)
2236 2236
2237(define_split 2237(define_split
2238 [(set (match_operand:SI 0 "s_register_operand" "") 2238 [(set (match_operand:SI 0 "s_register_operand" "")
2239 (match_operator:SI 1 "shiftable_operator" 2239 (match_operator:SI 1 "shiftable_operator"
2240 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "") 2240 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
2241 (match_operand:SI 3 "const_int_operand" "") 2241 (match_operand:SI 3 "const_int_operand" "")
2242 (match_operand:SI 4 "const_int_operand" "")) 2242 (match_operand:SI 4 "const_int_operand" ""))
2243 (match_operand:SI 5 "s_register_operand" "")])) 2243 (match_operand:SI 5 "s_register_operand" "")]))
2244 (clobber (match_operand:SI 6 "s_register_operand" ""))] 2244 (clobber (match_operand:SI 6 "s_register_operand" ""))]
2245 "TARGET_ARM" 2245 "TARGET_ARM"
2246 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3))) 2246 [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3)))
2247 (set (match_dup 0) 2247 (set (match_dup 0)
2248 (match_op_dup 1 2248 (match_op_dup 1
2249 [(ashiftrt:SI (match_dup 6) (match_dup 4)) 2249 [(ashiftrt:SI (match_dup 6) (match_dup 4))
2250 (match_dup 5)]))] 2250 (match_dup 5)]))]
2251 "{ 2251 "{
2252 HOST_WIDE_INT temp = INTVAL (operands[3]); 2252 HOST_WIDE_INT temp = INTVAL (operands[3]);
2253 2253
2254 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4])); 2254 operands[3] = GEN_INT (32 - temp - INTVAL (operands[4]));
2255 operands[4] = GEN_INT (32 - temp); 2255 operands[4] = GEN_INT (32 - temp);
2256 }" 2256 }"
2257) 2257)
2258  2258
2259;;; ??? This pattern is bogus. If operand3 has bits outside the range 2259;;; ??? This pattern is bogus. If operand3 has bits outside the range
2260;;; represented by the bitfield, then this will produce incorrect results. 2260;;; represented by the bitfield, then this will produce incorrect results.
2261;;; Somewhere, the value needs to be truncated. On targets like the m68k, 2261;;; Somewhere, the value needs to be truncated. On targets like the m68k,
2262;;; which have a real bit-field insert instruction, the truncation happens 2262;;; which have a real bit-field insert instruction, the truncation happens
2263;;; in the bit-field insert instruction itself. Since arm does not have a 2263;;; in the bit-field insert instruction itself. Since arm does not have a
2264;;; bit-field insert instruction, we would have to emit code here to truncate 2264;;; bit-field insert instruction, we would have to emit code here to truncate
2265;;; the value before we insert. This loses some of the advantage of having 2265;;; the value before we insert. This loses some of the advantage of having
2266;;; this insv pattern, so this pattern needs to be reevalutated. 2266;;; this insv pattern, so this pattern needs to be reevalutated.
2267 2267
2268(define_expand "insv" 2268(define_expand "insv"
2269 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "") 2269 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "")
2270 (match_operand:SI 1 "general_operand" "") 2270 (match_operand:SI 1 "general_operand" "")
2271 (match_operand:SI 2 "general_operand" "")) 2271 (match_operand:SI 2 "general_operand" ""))
2272 (match_operand:SI 3 "reg_or_int_operand" ""))] 2272 (match_operand:SI 3 "reg_or_int_operand" ""))]
2273 "TARGET_ARM || arm_arch_thumb2" 2273 "TARGET_ARM || arm_arch_thumb2"
2274 " 2274 "
2275 { 2275 {
2276 int start_bit = INTVAL (operands[2]); 2276 int start_bit = INTVAL (operands[2]);
2277 int width = INTVAL (operands[1]); 2277 int width = INTVAL (operands[1]);
2278 HOST_WIDE_INT mask = (((HOST_WIDE_INT)1) << width) - 1; 2278 HOST_WIDE_INT mask = (((HOST_WIDE_INT)1) << width) - 1;
2279 rtx target, subtarget; 2279 rtx target, subtarget;
2280 2280
2281 if (arm_arch_thumb2) 2281 if (arm_arch_thumb2)
2282 { 2282 {
2283 bool use_bfi = TRUE; 2283 bool use_bfi = TRUE;
2284 2284
2285 if (GET_CODE (operands[3]) == CONST_INT) 2285 if (GET_CODE (operands[3]) == CONST_INT)
2286 { 2286 {
2287 HOST_WIDE_INT val = INTVAL (operands[3]) & mask; 2287 HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
2288 2288
2289 if (val == 0) 2289 if (val == 0)
2290 { 2290 {
2291 emit_insn (gen_insv_zero (operands[0], operands[1], 2291 emit_insn (gen_insv_zero (operands[0], operands[1],
2292 operands[2])); 2292 operands[2]));
2293 DONE; 2293 DONE;
2294 } 2294 }
2295 2295
2296 /* See if the set can be done with a single orr instruction. */ 2296 /* See if the set can be done with a single orr instruction. */
2297 if (val == mask && const_ok_for_arm (val << start_bit)) 2297 if (val == mask && const_ok_for_arm (val << start_bit))
2298 use_bfi = FALSE; 2298 use_bfi = FALSE;
2299 } 2299 }
2300  2300
2301 if (use_bfi) 2301 if (use_bfi)
2302 { 2302 {
2303 if (GET_CODE (operands[3]) != REG) 2303 if (GET_CODE (operands[3]) != REG)
2304 operands[3] = force_reg (SImode, operands[3]); 2304 operands[3] = force_reg (SImode, operands[3]);
2305 2305
2306 emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2], 2306 emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
2307 operands[3])); 2307 operands[3]));
2308 DONE; 2308 DONE;
2309 } 2309 }
2310 } 2310 }
2311 2311
2312 target = copy_rtx (operands[0]); 2312 target = copy_rtx (operands[0]);
2313 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical  2313 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
2314 subreg as the final target. */ 2314 subreg as the final target. */
2315 if (GET_CODE (target) == SUBREG) 2315 if (GET_CODE (target) == SUBREG)
2316 { 2316 {
2317 subtarget = gen_reg_rtx (SImode); 2317 subtarget = gen_reg_rtx (SImode);
2318 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target))) 2318 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
2319 < GET_MODE_SIZE (SImode)) 2319 < GET_MODE_SIZE (SImode))
2320 target = SUBREG_REG (target); 2320 target = SUBREG_REG (target);
2321 } 2321 }
2322 else 2322 else
2323 subtarget = target;  2323 subtarget = target;
2324 2324
2325 if (GET_CODE (operands[3]) == CONST_INT) 2325 if (GET_CODE (operands[3]) == CONST_INT)
2326 { 2326 {
2327 /* Since we are inserting a known constant, we may be able to 2327 /* Since we are inserting a known constant, we may be able to
2328 reduce the number of bits that we have to clear so that 2328 reduce the number of bits that we have to clear so that
2329 the mask becomes simple. */ 2329 the mask becomes simple. */
2330 /* ??? This code does not check to see if the new mask is actually 2330 /* ??? This code does not check to see if the new mask is actually
2331 simpler. It may not be. */ 2331 simpler. It may not be. */
2332 rtx op1 = gen_reg_rtx (SImode); 2332 rtx op1 = gen_reg_rtx (SImode);
2333 /* ??? Truncate operand3 to fit in the bitfield. See comment before 2333 /* ??? Truncate operand3 to fit in the bitfield. See comment before
2334 start of this pattern. */ 2334 start of this pattern. */
2335 HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]); 2335 HOST_WIDE_INT op3_value = mask & INTVAL (operands[3]);
2336 HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit); 2336 HOST_WIDE_INT mask2 = ((mask & ~op3_value) << start_bit);
2337 2337
2338 emit_insn (gen_andsi3 (op1, operands[0], 2338 emit_insn (gen_andsi3 (op1, operands[0],
2339 gen_int_mode (~mask2, SImode))); 2339 gen_int_mode (~mask2, SImode)));
2340 emit_insn (gen_iorsi3 (subtarget, op1, 2340 emit_insn (gen_iorsi3 (subtarget, op1,
2341 gen_int_mode (op3_value << start_bit, SImode))); 2341 gen_int_mode (op3_value << start_bit, SImode)));
2342 } 2342 }
2343 else if (start_bit == 0 2343 else if (start_bit == 0
2344 && !(const_ok_for_arm (mask) 2344 && !(const_ok_for_arm (mask)
2345 || const_ok_for_arm (~mask))) 2345 || const_ok_for_arm (~mask)))
2346 { 2346 {
2347 /* A Trick, since we are setting the bottom bits in the word, 2347 /* A Trick, since we are setting the bottom bits in the word,
2348 we can shift operand[3] up, operand[0] down, OR them together 2348 we can shift operand[3] up, operand[0] down, OR them together
2349 and rotate the result back again. This takes 3 insns, and 2349 and rotate the result back again. This takes 3 insns, and
2350 the third might be mergeable into another op. */ 2350 the third might be mergeable into another op. */
2351 /* The shift up copes with the possibility that operand[3] is 2351 /* The shift up copes with the possibility that operand[3] is
2352 wider than the bitfield. */ 2352 wider than the bitfield. */
2353 rtx op0 = gen_reg_rtx (SImode); 2353 rtx op0 = gen_reg_rtx (SImode);
2354 rtx op1 = gen_reg_rtx (SImode); 2354 rtx op1 = gen_reg_rtx (SImode);
2355 2355
2356 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width))); 2356 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2357 emit_insn (gen_lshrsi3 (op1, operands[0], operands[1])); 2357 emit_insn (gen_lshrsi3 (op1, operands[0], operands[1]));
2358 emit_insn (gen_iorsi3 (op1, op1, op0)); 2358 emit_insn (gen_iorsi3 (op1, op1, op0));
2359 emit_insn (gen_rotlsi3 (subtarget, op1, operands[1])); 2359 emit_insn (gen_rotlsi3 (subtarget, op1, operands[1]));
2360 } 2360 }
2361 else if ((width + start_bit == 32) 2361 else if ((width + start_bit == 32)
2362 && !(const_ok_for_arm (mask) 2362 && !(const_ok_for_arm (mask)
2363 || const_ok_for_arm (~mask))) 2363 || const_ok_for_arm (~mask)))
2364 { 2364 {
2365 /* Similar trick, but slightly less efficient. */ 2365 /* Similar trick, but slightly less efficient. */
2366 2366
2367 rtx op0 = gen_reg_rtx (SImode); 2367 rtx op0 = gen_reg_rtx (SImode);
2368 rtx op1 = gen_reg_rtx (SImode); 2368 rtx op1 = gen_reg_rtx (SImode);
2369 2369
2370 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width))); 2370 emit_insn (gen_ashlsi3 (op0, operands[3], GEN_INT (32 - width)));
2371 emit_insn (gen_ashlsi3 (op1, operands[0], operands[1])); 2371 emit_insn (gen_ashlsi3 (op1, operands[0], operands[1]));
2372 emit_insn (gen_lshrsi3 (op1, op1, operands[1])); 2372 emit_insn (gen_lshrsi3 (op1, op1, operands[1]));
2373 emit_insn (gen_iorsi3 (subtarget, op1, op0)); 2373 emit_insn (gen_iorsi3 (subtarget, op1, op0));
2374 } 2374 }
2375 else 2375 else
2376 { 2376 {
2377 rtx op0 = gen_int_mode (mask, SImode); 2377 rtx op0 = gen_int_mode (mask, SImode);
2378 rtx op1 = gen_reg_rtx (SImode); 2378 rtx op1 = gen_reg_rtx (SImode);
2379 rtx op2 = gen_reg_rtx (SImode); 2379 rtx op2 = gen_reg_rtx (SImode);
2380 2380
2381 if (!(const_ok_for_arm (mask) || const_ok_for_arm (~mask))) 2381 if (!(const_ok_for_arm (mask) || const_ok_for_arm (~mask)))
2382 { 2382 {
2383 rtx tmp = gen_reg_rtx (SImode); 2383 rtx tmp = gen_reg_rtx (SImode);
2384 2384
2385 emit_insn (gen_movsi (tmp, op0)); 2385 emit_insn (gen_movsi (tmp, op0));
2386 op0 = tmp; 2386 op0 = tmp;
2387 } 2387 }
2388 2388
2389 /* Mask out any bits in operand[3] that are not needed. */ 2389 /* Mask out any bits in operand[3] that are not needed. */
2390 emit_insn (gen_andsi3 (op1, operands[3], op0)); 2390 emit_insn (gen_andsi3 (op1, operands[3], op0));
2391 2391
2392 if (GET_CODE (op0) == CONST_INT 2392 if (GET_CODE (op0) == CONST_INT
2393 && (const_ok_for_arm (mask << start_bit) 2393 && (const_ok_for_arm (mask << start_bit)
2394 || const_ok_for_arm (~(mask << start_bit)))) 2394 || const_ok_for_arm (~(mask << start_bit))))
2395 { 2395 {
2396 op0 = gen_int_mode (~(mask << start_bit), SImode); 2396 op0 = gen_int_mode (~(mask << start_bit), SImode);
2397 emit_insn (gen_andsi3 (op2, operands[0], op0)); 2397 emit_insn (gen_andsi3 (op2, operands[0], op0));
2398 } 2398 }
2399 else 2399 else
2400 { 2400 {
2401 if (GET_CODE (op0) == CONST_INT) 2401 if (GET_CODE (op0) == CONST_INT)
2402 { 2402 {
2403 rtx tmp = gen_reg_rtx (SImode); 2403 rtx tmp = gen_reg_rtx (SImode);
2404 2404
2405 emit_insn (gen_movsi (tmp, op0)); 2405 emit_insn (gen_movsi (tmp, op0));
2406 op0 = tmp; 2406 op0 = tmp;
2407 } 2407 }
2408 2408
2409 if (start_bit != 0) 2409 if (start_bit != 0)
2410 emit_insn (gen_ashlsi3 (op0, op0, operands[2])); 2410 emit_insn (gen_ashlsi3 (op0, op0, operands[2]));
2411  2411
2412 emit_insn (gen_andsi_notsi_si (op2, operands[0], op0)); 2412 emit_insn (gen_andsi_notsi_si (op2, operands[0], op0));
2413 } 2413 }
2414 2414
2415 if (start_bit != 0) 2415 if (start_bit != 0)
2416 emit_insn (gen_ashlsi3 (op1, op1, operands[2])); 2416 emit_insn (gen_ashlsi3 (op1, op1, operands[2]));
2417 2417
2418 emit_insn (gen_iorsi3 (subtarget, op1, op2)); 2418 emit_insn (gen_iorsi3 (subtarget, op1, op2));
2419 } 2419 }
2420 2420
2421 if (subtarget != target) 2421 if (subtarget != target)
2422 { 2422 {
2423 /* If TARGET is still a SUBREG, then it must be wider than a word, 2423 /* If TARGET is still a SUBREG, then it must be wider than a word,
2424 so we must be careful only to set the subword we were asked to. */ 2424 so we must be careful only to set the subword we were asked to. */
2425 if (GET_CODE (target) == SUBREG) 2425 if (GET_CODE (target) == SUBREG)
2426 emit_move_insn (target, subtarget); 2426 emit_move_insn (target, subtarget);
2427 else 2427 else
2428 emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget)); 2428 emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
2429 } 2429 }
2430 2430
2431 DONE; 2431 DONE;
2432 }" 2432 }"
2433) 2433)
2434 2434
2435(define_insn "insv_zero" 2435(define_insn "insv_zero"
2436 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") 2436 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2437 (match_operand:SI 1 "const_int_operand" "M") 2437 (match_operand:SI 1 "const_int_operand" "M")
2438 (match_operand:SI 2 "const_int_operand" "M")) 2438 (match_operand:SI 2 "const_int_operand" "M"))
2439 (const_int 0))] 2439 (const_int 0))]
2440 "arm_arch_thumb2" 2440 "arm_arch_thumb2"
2441 "bfc%?\t%0, %2, %1" 2441 "bfc%?\t%0, %2, %1"
2442 [(set_attr "length" "4") 2442 [(set_attr "length" "4")
2443 (set_attr "predicable" "yes")] 2443 (set_attr "predicable" "yes")]
2444) 2444)
2445 2445
2446(define_insn "insv_t2" 2446(define_insn "insv_t2"
2447 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r") 2447 [(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
2448 (match_operand:SI 1 "const_int_operand" "M") 2448 (match_operand:SI 1 "const_int_operand" "M")
2449 (match_operand:SI 2 "const_int_operand" "M")) 2449 (match_operand:SI 2 "const_int_operand" "M"))
2450 (match_operand:SI 3 "s_register_operand" "r"))] 2450 (match_operand:SI 3 "s_register_operand" "r"))]
2451 "arm_arch_thumb2" 2451 "arm_arch_thumb2"
2452 "bfi%?\t%0, %3, %2, %1" 2452 "bfi%?\t%0, %3, %2, %1"
2453 [(set_attr "length" "4") 2453 [(set_attr "length" "4")
2454 (set_attr "predicable" "yes")] 2454 (set_attr "predicable" "yes")]
2455) 2455)
2456 2456
2457; constants for op 2 will never be given to these patterns. 2457; constants for op 2 will never be given to these patterns.
2458(define_insn_and_split "*anddi_notdi_di" 2458(define_insn_and_split "*anddi_notdi_di"
2459 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2459 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2460 (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r")) 2460 (and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
2461 (match_operand:DI 2 "s_register_operand" "r,0")))] 2461 (match_operand:DI 2 "s_register_operand" "r,0")))]
2462 "TARGET_32BIT" 2462 "TARGET_32BIT"
2463 "#" 2463 "#"
2464 "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" 2464 "TARGET_32BIT && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
2465 [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) 2465 [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2)))
2466 (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] 2466 (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))]
2467 " 2467 "
2468 { 2468 {
2469 operands[3] = gen_highpart (SImode, operands[0]); 2469 operands[3] = gen_highpart (SImode, operands[0]);
2470 operands[0] = gen_lowpart (SImode, operands[0]); 2470 operands[0] = gen_lowpart (SImode, operands[0]);
2471 operands[4] = gen_highpart (SImode, operands[1]); 2471 operands[4] = gen_highpart (SImode, operands[1]);
2472 operands[1] = gen_lowpart (SImode, operands[1]); 2472 operands[1] = gen_lowpart (SImode, operands[1]);
2473 operands[5] = gen_highpart (SImode, operands[2]); 2473 operands[5] = gen_highpart (SImode, operands[2]);
2474 operands[2] = gen_lowpart (SImode, operands[2]); 2474 operands[2] = gen_lowpart (SImode, operands[2]);
2475 }" 2475 }"
2476 [(set_attr "length" "8") 2476 [(set_attr "length" "8")
2477 (set_attr "predicable" "yes")] 2477 (set_attr "predicable" "yes")]
2478) 2478)
2479  2479
2480(define_insn_and_split "*anddi_notzesidi_di" 2480(define_insn_and_split "*anddi_notzesidi_di"
2481 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2481 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2482 (and:DI (not:DI (zero_extend:DI 2482 (and:DI (not:DI (zero_extend:DI
2483 (match_operand:SI 2 "s_register_operand" "r,r"))) 2483 (match_operand:SI 2 "s_register_operand" "r,r")))
2484 (match_operand:DI 1 "s_register_operand" "0,?r")))] 2484 (match_operand:DI 1 "s_register_operand" "0,?r")))]
2485 "TARGET_32BIT" 2485 "TARGET_32BIT"
2486 "@ 2486 "@
2487 bic%?\\t%Q0, %Q1, %2 2487 bic%?\\t%Q0, %Q1, %2
2488 #" 2488 #"
2489 ; (not (zero_extend ...)) allows us to just copy the high word from 2489 ; (not (zero_extend ...)) allows us to just copy the high word from
2490 ; operand1 to operand0. 2490 ; operand1 to operand0.
2491 "TARGET_32BIT 2491 "TARGET_32BIT
2492 && reload_completed 2492 && reload_completed
2493 && operands[0] != operands[1]" 2493 && operands[0] != operands[1]"
2494 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) 2494 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
2495 (set (match_dup 3) (match_dup 4))] 2495 (set (match_dup 3) (match_dup 4))]
2496 " 2496 "
2497 { 2497 {
2498 operands[3] = gen_highpart (SImode, operands[0]); 2498 operands[3] = gen_highpart (SImode, operands[0]);
2499 operands[0] = gen_lowpart (SImode, operands[0]); 2499 operands[0] = gen_lowpart (SImode, operands[0]);
2500 operands[4] = gen_highpart (SImode, operands[1]); 2500 operands[4] = gen_highpart (SImode, operands[1]);
2501 operands[1] = gen_lowpart (SImode, operands[1]); 2501 operands[1] = gen_lowpart (SImode, operands[1]);
2502 }" 2502 }"
2503 [(set_attr "length" "4,8") 2503 [(set_attr "length" "4,8")
2504 (set_attr "predicable" "yes")] 2504 (set_attr "predicable" "yes")]
2505) 2505)
2506  2506
2507(define_insn_and_split "*anddi_notsesidi_di" 2507(define_insn_and_split "*anddi_notsesidi_di"
2508 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2508 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2509 (and:DI (not:DI (sign_extend:DI 2509 (and:DI (not:DI (sign_extend:DI
2510 (match_operand:SI 2 "s_register_operand" "r,r"))) 2510 (match_operand:SI 2 "s_register_operand" "r,r")))
2511 (match_operand:DI 1 "s_register_operand" "0,r")))] 2511 (match_operand:DI 1 "s_register_operand" "0,r")))]
2512 "TARGET_32BIT" 2512 "TARGET_32BIT"
2513 "#" 2513 "#"
2514 "TARGET_32BIT && reload_completed" 2514 "TARGET_32BIT && reload_completed"
2515 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1))) 2515 [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
2516 (set (match_dup 3) (and:SI (not:SI 2516 (set (match_dup 3) (and:SI (not:SI
2517 (ashiftrt:SI (match_dup 2) (const_int 31))) 2517 (ashiftrt:SI (match_dup 2) (const_int 31)))
2518 (match_dup 4)))] 2518 (match_dup 4)))]
2519 " 2519 "
2520 { 2520 {
2521 operands[3] = gen_highpart (SImode, operands[0]); 2521 operands[3] = gen_highpart (SImode, operands[0]);
2522 operands[0] = gen_lowpart (SImode, operands[0]); 2522 operands[0] = gen_lowpart (SImode, operands[0]);
2523 operands[4] = gen_highpart (SImode, operands[1]); 2523 operands[4] = gen_highpart (SImode, operands[1]);
2524 operands[1] = gen_lowpart (SImode, operands[1]); 2524 operands[1] = gen_lowpart (SImode, operands[1]);
2525 }" 2525 }"
2526 [(set_attr "length" "8") 2526 [(set_attr "length" "8")
2527 (set_attr "predicable" "yes")] 2527 (set_attr "predicable" "yes")]
2528) 2528)
2529  2529
2530(define_insn "andsi_notsi_si" 2530(define_insn "andsi_notsi_si"
2531 [(set (match_operand:SI 0 "s_register_operand" "=r") 2531 [(set (match_operand:SI 0 "s_register_operand" "=r")
2532 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 2532 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2533 (match_operand:SI 1 "s_register_operand" "r")))] 2533 (match_operand:SI 1 "s_register_operand" "r")))]
2534 "TARGET_32BIT" 2534 "TARGET_32BIT"
2535 "bic%?\\t%0, %1, %2" 2535 "bic%?\\t%0, %1, %2"
2536 [(set_attr "predicable" "yes")] 2536 [(set_attr "predicable" "yes")]
2537) 2537)
2538 2538
2539(define_insn "bicsi3" 2539(define_insn "bicsi3"
2540 [(set (match_operand:SI 0 "register_operand" "=l") 2540 [(set (match_operand:SI 0 "register_operand" "=l")
2541 (and:SI (not:SI (match_operand:SI 1 "register_operand" "l")) 2541 (and:SI (not:SI (match_operand:SI 1 "register_operand" "l"))
2542 (match_operand:SI 2 "register_operand" "0")))] 2542 (match_operand:SI 2 "register_operand" "0")))]
2543 "TARGET_THUMB1" 2543 "TARGET_THUMB1"
2544 "bic\\t%0, %0, %1" 2544 "bic\\t%0, %0, %1"
2545 [(set_attr "length" "2")] 2545 [(set_attr "length" "2")]
2546) 2546)
2547 2547
2548(define_insn "andsi_not_shiftsi_si" 2548(define_insn "andsi_not_shiftsi_si"
2549 [(set (match_operand:SI 0 "s_register_operand" "=r") 2549 [(set (match_operand:SI 0 "s_register_operand" "=r")
2550 (and:SI (not:SI (match_operator:SI 4 "shift_operator" 2550 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
2551 [(match_operand:SI 2 "s_register_operand" "r") 2551 [(match_operand:SI 2 "s_register_operand" "r")
2552 (match_operand:SI 3 "arm_rhs_operand" "rM")])) 2552 (match_operand:SI 3 "arm_rhs_operand" "rM")]))
2553 (match_operand:SI 1 "s_register_operand" "r")))] 2553 (match_operand:SI 1 "s_register_operand" "r")))]
2554 "TARGET_ARM" 2554 "TARGET_ARM"
2555 "bic%?\\t%0, %1, %2%S4" 2555 "bic%?\\t%0, %1, %2%S4"
2556 [(set_attr "predicable" "yes") 2556 [(set_attr "predicable" "yes")
2557 (set_attr "shift" "2") 2557 (set_attr "shift" "2")
2558 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") 2558 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
2559 (const_string "alu_shift") 2559 (const_string "alu_shift")
2560 (const_string "alu_shift_reg")))] 2560 (const_string "alu_shift_reg")))]
2561) 2561)
2562 2562
2563(define_insn "*andsi_notsi_si_compare0" 2563(define_insn "*andsi_notsi_si_compare0"
2564 [(set (reg:CC_NOOV CC_REGNUM) 2564 [(set (reg:CC_NOOV CC_REGNUM)
2565 (compare:CC_NOOV 2565 (compare:CC_NOOV
2566 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 2566 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2567 (match_operand:SI 1 "s_register_operand" "r")) 2567 (match_operand:SI 1 "s_register_operand" "r"))
2568 (const_int 0))) 2568 (const_int 0)))
2569 (set (match_operand:SI 0 "s_register_operand" "=r") 2569 (set (match_operand:SI 0 "s_register_operand" "=r")
2570 (and:SI (not:SI (match_dup 2)) (match_dup 1)))] 2570 (and:SI (not:SI (match_dup 2)) (match_dup 1)))]
2571 "TARGET_32BIT" 2571 "TARGET_32BIT"
2572 "bic%.\\t%0, %1, %2" 2572 "bic%.\\t%0, %1, %2"
2573 [(set_attr "conds" "set")] 2573 [(set_attr "conds" "set")]
2574) 2574)
2575 2575
2576(define_insn "*andsi_notsi_si_compare0_scratch" 2576(define_insn "*andsi_notsi_si_compare0_scratch"
2577 [(set (reg:CC_NOOV CC_REGNUM) 2577 [(set (reg:CC_NOOV CC_REGNUM)
2578 (compare:CC_NOOV 2578 (compare:CC_NOOV
2579 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) 2579 (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
2580 (match_operand:SI 1 "s_register_operand" "r")) 2580 (match_operand:SI 1 "s_register_operand" "r"))
2581 (const_int 0))) 2581 (const_int 0)))
2582 (clobber (match_scratch:SI 0 "=r"))] 2582 (clobber (match_scratch:SI 0 "=r"))]
2583 "TARGET_32BIT" 2583 "TARGET_32BIT"
2584 "bic%.\\t%0, %1, %2" 2584 "bic%.\\t%0, %1, %2"
2585 [(set_attr "conds" "set")] 2585 [(set_attr "conds" "set")]
2586) 2586)
2587 2587
2588(define_insn "iordi3" 2588(define_insn "iordi3"
2589 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2589 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2590 (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") 2590 (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r")
2591 (match_operand:DI 2 "s_register_operand" "r,r")))] 2591 (match_operand:DI 2 "s_register_operand" "r,r")))]
2592 "TARGET_32BIT && ! TARGET_IWMMXT" 2592 "TARGET_32BIT && ! TARGET_IWMMXT"
2593 "#" 2593 "#"
2594 [(set_attr "length" "8") 2594 [(set_attr "length" "8")
2595 (set_attr "predicable" "yes")] 2595 (set_attr "predicable" "yes")]
2596) 2596)
2597 2597
2598(define_insn "*iordi_zesidi_di" 2598(define_insn "*iordi_zesidi_di"
2599 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2599 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2600 (ior:DI (zero_extend:DI 2600 (ior:DI (zero_extend:DI
2601 (match_operand:SI 2 "s_register_operand" "r,r")) 2601 (match_operand:SI 2 "s_register_operand" "r,r"))
2602 (match_operand:DI 1 "s_register_operand" "0,?r")))] 2602 (match_operand:DI 1 "s_register_operand" "0,?r")))]
2603 "TARGET_32BIT" 2603 "TARGET_32BIT"
2604 "@ 2604 "@
2605 orr%?\\t%Q0, %Q1, %2 2605 orr%?\\t%Q0, %Q1, %2
2606 #" 2606 #"
2607 [(set_attr "length" "4,8") 2607 [(set_attr "length" "4,8")
2608 (set_attr "predicable" "yes")] 2608 (set_attr "predicable" "yes")]
2609) 2609)
2610 2610
2611(define_insn "*iordi_sesidi_di" 2611(define_insn "*iordi_sesidi_di"
2612 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2612 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2613 (ior:DI (sign_extend:DI 2613 (ior:DI (sign_extend:DI
2614 (match_operand:SI 2 "s_register_operand" "r,r")) 2614 (match_operand:SI 2 "s_register_operand" "r,r"))
2615 (match_operand:DI 1 "s_register_operand" "0,r")))] 2615 (match_operand:DI 1 "s_register_operand" "0,r")))]
2616 "TARGET_32BIT" 2616 "TARGET_32BIT"
2617 "#" 2617 "#"
2618 [(set_attr "length" "8") 2618 [(set_attr "length" "8")
2619 (set_attr "predicable" "yes")] 2619 (set_attr "predicable" "yes")]
2620) 2620)
2621 2621
2622(define_expand "iorsi3" 2622(define_expand "iorsi3"
2623 [(set (match_operand:SI 0 "s_register_operand" "") 2623 [(set (match_operand:SI 0 "s_register_operand" "")
2624 (ior:SI (match_operand:SI 1 "s_register_operand" "") 2624 (ior:SI (match_operand:SI 1 "s_register_operand" "")
2625 (match_operand:SI 2 "reg_or_int_operand" "")))] 2625 (match_operand:SI 2 "reg_or_int_operand" "")))]
2626 "TARGET_EITHER" 2626 "TARGET_EITHER"
2627 " 2627 "
2628 if (GET_CODE (operands[2]) == CONST_INT) 2628 if (GET_CODE (operands[2]) == CONST_INT)
2629 { 2629 {
2630 if (TARGET_32BIT) 2630 if (TARGET_32BIT)
2631 { 2631 {
2632 arm_split_constant (IOR, SImode, NULL_RTX, 2632 arm_split_constant (IOR, SImode, NULL_RTX,
2633 INTVAL (operands[2]), operands[0], operands[1], 2633 INTVAL (operands[2]), operands[0], operands[1],
2634 optimize && can_create_pseudo_p ()); 2634 optimize && can_create_pseudo_p ());
2635 DONE; 2635 DONE;
2636 } 2636 }
2637 else /* TARGET_THUMB1 */ 2637 else /* TARGET_THUMB1 */
2638 { 2638 {
2639 rtx tmp = force_reg (SImode, operands[2]); 2639 rtx tmp = force_reg (SImode, operands[2]);
2640 if (rtx_equal_p (operands[0], operands[1])) 2640 if (rtx_equal_p (operands[0], operands[1]))
2641 operands[2] = tmp; 2641 operands[2] = tmp;
2642 else 2642 else
2643 { 2643 {
2644 operands[2] = operands[1]; 2644 operands[2] = operands[1];
2645 operands[1] = tmp; 2645 operands[1] = tmp;
2646 } 2646 }
2647 } 2647 }
2648 } 2648 }
2649 " 2649 "
2650) 2650)
2651 2651
2652(define_insn_and_split "*arm_iorsi3" 2652(define_insn_and_split "*arm_iorsi3"
2653 [(set (match_operand:SI 0 "s_register_operand" "=r,r") 2653 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
2654 (ior:SI (match_operand:SI 1 "s_register_operand" "r,r") 2654 (ior:SI (match_operand:SI 1 "s_register_operand" "r,r")
2655 (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))] 2655 (match_operand:SI 2 "reg_or_int_operand" "rI,?n")))]
2656 "TARGET_ARM" 2656 "TARGET_ARM"
2657 "@ 2657 "@
2658 orr%?\\t%0, %1, %2 2658 orr%?\\t%0, %1, %2
2659 #" 2659 #"
2660 "TARGET_ARM 2660 "TARGET_ARM
2661 && GET_CODE (operands[2]) == CONST_INT 2661 && GET_CODE (operands[2]) == CONST_INT
2662 && !const_ok_for_arm (INTVAL (operands[2]))" 2662 && !const_ok_for_arm (INTVAL (operands[2]))"
2663 [(clobber (const_int 0))] 2663 [(clobber (const_int 0))]
2664 " 2664 "
2665 arm_split_constant (IOR, SImode, curr_insn,  2665 arm_split_constant (IOR, SImode, curr_insn,
2666 INTVAL (operands[2]), operands[0], operands[1], 0); 2666 INTVAL (operands[2]), operands[0], operands[1], 0);
2667 DONE; 2667 DONE;
2668 " 2668 "
2669 [(set_attr "length" "4,16") 2669 [(set_attr "length" "4,16")
2670 (set_attr "predicable" "yes")] 2670 (set_attr "predicable" "yes")]
2671) 2671)
2672 2672
2673(define_insn "*thumb1_iorsi3" 2673(define_insn "*thumb1_iorsi3"
2674 [(set (match_operand:SI 0 "register_operand" "=l") 2674 [(set (match_operand:SI 0 "register_operand" "=l")
2675 (ior:SI (match_operand:SI 1 "register_operand" "%0") 2675 (ior:SI (match_operand:SI 1 "register_operand" "%0")
2676 (match_operand:SI 2 "register_operand" "l")))] 2676 (match_operand:SI 2 "register_operand" "l")))]
2677 "TARGET_THUMB1" 2677 "TARGET_THUMB1"
2678 "orr\\t%0, %0, %2" 2678 "orr\\t%0, %0, %2"
2679 [(set_attr "length" "2")] 2679 [(set_attr "length" "2")]
2680) 2680)
2681 2681
2682(define_peephole2 2682(define_peephole2
2683 [(match_scratch:SI 3 "r") 2683 [(match_scratch:SI 3 "r")
2684 (set (match_operand:SI 0 "arm_general_register_operand" "") 2684 (set (match_operand:SI 0 "arm_general_register_operand" "")
2685 (ior:SI (match_operand:SI 1 "arm_general_register_operand" "") 2685 (ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
2686 (match_operand:SI 2 "const_int_operand" "")))] 2686 (match_operand:SI 2 "const_int_operand" "")))]
2687 "TARGET_ARM 2687 "TARGET_ARM
2688 && !const_ok_for_arm (INTVAL (operands[2])) 2688 && !const_ok_for_arm (INTVAL (operands[2]))
2689 && const_ok_for_arm (~INTVAL (operands[2]))" 2689 && const_ok_for_arm (~INTVAL (operands[2]))"
2690 [(set (match_dup 3) (match_dup 2)) 2690 [(set (match_dup 3) (match_dup 2))
2691 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))] 2691 (set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))]
2692 "" 2692 ""
2693) 2693)
2694 2694
2695(define_insn "*iorsi3_compare0" 2695(define_insn "*iorsi3_compare0"
2696 [(set (reg:CC_NOOV CC_REGNUM) 2696 [(set (reg:CC_NOOV CC_REGNUM)
2697 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") 2697 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
2698 (match_operand:SI 2 "arm_rhs_operand" "rI")) 2698 (match_operand:SI 2 "arm_rhs_operand" "rI"))
2699 (const_int 0))) 2699 (const_int 0)))
2700 (set (match_operand:SI 0 "s_register_operand" "=r") 2700 (set (match_operand:SI 0 "s_register_operand" "=r")
2701 (ior:SI (match_dup 1) (match_dup 2)))] 2701 (ior:SI (match_dup 1) (match_dup 2)))]
2702 "TARGET_32BIT" 2702 "TARGET_32BIT"
2703 "orr%.\\t%0, %1, %2" 2703 "orr%.\\t%0, %1, %2"
2704 [(set_attr "conds" "set")] 2704 [(set_attr "conds" "set")]
2705) 2705)
2706 2706
2707(define_insn "*iorsi3_compare0_scratch" 2707(define_insn "*iorsi3_compare0_scratch"
2708 [(set (reg:CC_NOOV CC_REGNUM) 2708 [(set (reg:CC_NOOV CC_REGNUM)
2709 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r") 2709 (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r")
2710 (match_operand:SI 2 "arm_rhs_operand" "rI")) 2710 (match_operand:SI 2 "arm_rhs_operand" "rI"))
2711 (const_int 0))) 2711 (const_int 0)))
2712 (clobber (match_scratch:SI 0 "=r"))] 2712 (clobber (match_scratch:SI 0 "=r"))]
2713 "TARGET_32BIT" 2713 "TARGET_32BIT"
2714 "orr%.\\t%0, %1, %2" 2714 "orr%.\\t%0, %1, %2"
2715 [(set_attr "conds" "set")] 2715 [(set_attr "conds" "set")]
2716) 2716)
2717 2717
2718(define_insn "xordi3" 2718(define_insn "xordi3"
2719 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2719 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2720 (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") 2720 (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r")
2721 (match_operand:DI 2 "s_register_operand" "r,r")))] 2721 (match_operand:DI 2 "s_register_operand" "r,r")))]
2722 "TARGET_32BIT && !TARGET_IWMMXT" 2722 "TARGET_32BIT && !TARGET_IWMMXT"
2723 "#" 2723 "#"
2724 [(set_attr "length" "8") 2724 [(set_attr "length" "8")
2725 (set_attr "predicable" "yes")] 2725 (set_attr "predicable" "yes")]
2726) 2726)
2727 2727
2728(define_insn "*xordi_zesidi_di" 2728(define_insn "*xordi_zesidi_di"
2729 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2729 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2730 (xor:DI (zero_extend:DI 2730 (xor:DI (zero_extend:DI
2731 (match_operand:SI 2 "s_register_operand" "r,r")) 2731 (match_operand:SI 2 "s_register_operand" "r,r"))
2732 (match_operand:DI 1 "s_register_operand" "0,?r")))] 2732 (match_operand:DI 1 "s_register_operand" "0,?r")))]
2733 "TARGET_32BIT" 2733 "TARGET_32BIT"
2734 "@ 2734 "@
2735 eor%?\\t%Q0, %Q1, %2 2735 eor%?\\t%Q0, %Q1, %2
2736 #" 2736 #"
2737 [(set_attr "length" "4,8") 2737 [(set_attr "length" "4,8")
2738 (set_attr "predicable" "yes")] 2738 (set_attr "predicable" "yes")]
2739) 2739)
2740 2740
2741(define_insn "*xordi_sesidi_di" 2741(define_insn "*xordi_sesidi_di"
2742 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 2742 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
2743 (xor:DI (sign_extend:DI 2743 (xor:DI (sign_extend:DI
2744 (match_operand:SI 2 "s_register_operand" "r,r")) 2744 (match_operand:SI 2 "s_register_operand" "r,r"))
2745 (match_operand:DI 1 "s_register_operand" "0,r")))] 2745 (match_operand:DI 1 "s_register_operand" "0,r")))]
2746 "TARGET_32BIT" 2746 "TARGET_32BIT"
2747 "#" 2747 "#"
2748 [(set_attr "length" "8") 2748 [(set_attr "length" "8")
2749 (set_attr "predicable" "yes")] 2749 (set_attr "predicable" "yes")]
2750) 2750)
2751 2751
2752(define_expand "xorsi3" 2752(define_expand "xorsi3"
2753 [(set (match_operand:SI 0 "s_register_operand" "") 2753 [(set (match_operand:SI 0 "s_register_operand" "")
2754 (xor:SI (match_operand:SI 1 "s_register_operand" "") 2754 (xor:SI (match_operand:SI 1 "s_register_operand" "")
2755 (match_operand:SI 2 "reg_or_int_operand" "")))] 2755 (match_operand:SI 2 "reg_or_int_operand" "")))]
2756 "TARGET_EITHER" 2756 "TARGET_EITHER"
2757 "if (GET_CODE (operands[2]) == CONST_INT) 2757 "if (GET_CODE (operands[2]) == CONST_INT)
2758 { 2758 {
2759 if (TARGET_32BIT) 2759 if (TARGET_32BIT)
2760 { 2760 {
2761 arm_split_constant (XOR, SImode, NULL_RTX, 2761 arm_split_constant (XOR, SImode, NULL_RTX,
2762 INTVAL (operands[2]), operands[0], operands[1], 2762 INTVAL (operands[2]), operands[0], operands[1],
2763 optimize && can_create_pseudo_p ()); 2763 optimize && can_create_pseudo_p ());
2764 DONE; 2764 DONE;
2765 } 2765 }
2766 else /* TARGET_THUMB1 */ 2766 else /* TARGET_THUMB1 */
2767 { 2767 {
2768 rtx tmp = force_reg (SImode, operands[2]); 2768 rtx tmp = force_reg (SImode, operands[2]);
2769 if (rtx_equal_p (operands[0], operands[1])) 2769 if (rtx_equal_p (operands[0], operands[1]))
2770 operands[2] = tmp; 2770 operands[2] = tmp;
2771 else 2771 else
2772 { 2772 {
2773 operands[2] = operands[1]; 2773 operands[2] = operands[1];
2774 operands[1] = tmp; 2774 operands[1] = tmp;
2775 } 2775 }
2776 } 2776 }
2777 }" 2777 }"
2778) 2778)
2779 2779
2780(define_insn "*arm_xorsi3" 2780(define_insn "*arm_xorsi3"
2781 [(set (match_operand:SI 0 "s_register_operand" "=r") 2781 [(set (match_operand:SI 0 "s_register_operand" "=r")
2782 (xor:SI (match_operand:SI 1 "s_register_operand" "r") 2782 (xor:SI (match_operand:SI 1 "s_register_operand" "r")
2783 (match_operand:SI 2 "arm_rhs_operand" "rI")))] 2783 (match_operand:SI 2 "arm_rhs_operand" "rI")))]
2784 "TARGET_32BIT" 2784 "TARGET_32BIT"
2785 "eor%?\\t%0, %1, %2" 2785 "eor%?\\t%0, %1, %2"
2786 [(set_attr "predicable" "yes")] 2786 [(set_attr "predicable" "yes")]
2787) 2787)
2788 2788
2789(define_insn "*thumb1_xorsi3" 2789(define_insn "*thumb1_xorsi3"
2790 [(set (match_operand:SI 0 "register_operand" "=l") 2790 [(set (match_operand:SI 0 "register_operand" "=l")
2791 (xor:SI (match_operand:SI 1 "register_operand" "%0") 2791 (xor:SI (match_operand:SI 1 "register_operand" "%0")
2792 (match_operand:SI 2 "register_operand" "l")))] 2792 (match_operand:SI 2 "register_operand" "l")))]
2793 "TARGET_THUMB1" 2793 "TARGET_THUMB1"
2794 "eor\\t%0, %0, %2" 2794 "eor\\t%0, %0, %2"
2795 [(set_attr "length" "2")] 2795 [(set_attr "length" "2")]
2796) 2796)
2797 2797
2798(define_insn "*xorsi3_compare0" 2798(define_insn "*xorsi3_compare0"
2799 [(set (reg:CC_NOOV CC_REGNUM) 2799 [(set (reg:CC_NOOV CC_REGNUM)
2800 (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r") 2800 (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r")
2801 (match_operand:SI 2 "arm_rhs_operand" "rI")) 2801 (match_operand:SI 2 "arm_rhs_operand" "rI"))
2802 (const_int 0))) 2802 (const_int 0)))
2803 (set (match_operand:SI 0 "s_register_operand" "=r") 2803 (set (match_operand:SI 0 "s_register_operand" "=r")
2804 (xor:SI (match_dup 1) (match_dup 2)))] 2804 (xor:SI (match_dup 1) (match_dup 2)))]
2805 "TARGET_32BIT" 2805 "TARGET_32BIT"
2806 "eor%.\\t%0, %1, %2" 2806 "eor%.\\t%0, %1, %2"
2807 [(set_attr "conds" "set")] 2807 [(set_attr "conds" "set")]
2808) 2808)
2809 2809
2810(define_insn "*xorsi3_compare0_scratch" 2810(define_insn "*xorsi3_compare0_scratch"
2811 [(set (reg:CC_NOOV CC_REGNUM) 2811 [(set (reg:CC_NOOV CC_REGNUM)
2812 (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r") 2812 (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
2813 (match_operand:SI 1 "arm_rhs_operand" "rI")) 2813 (match_operand:SI 1 "arm_rhs_operand" "rI"))
2814 (const_int 0)))] 2814 (const_int 0)))]
2815 "TARGET_32BIT" 2815 "TARGET_32BIT"
2816 "teq%?\\t%0, %1" 2816 "teq%?\\t%0, %1"
2817 [(set_attr "conds" "set")] 2817 [(set_attr "conds" "set")]
2818) 2818)
2819 2819
2820; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),  2820; By splitting (IOR (AND (NOT A) (NOT B)) C) as D = AND (IOR A B) (NOT C),
2821; (NOT D) we can sometimes merge the final NOT into one of the following 2821; (NOT D) we can sometimes merge the final NOT into one of the following
2822; insns. 2822; insns.
2823 2823
2824(define_split 2824(define_split
2825 [(set (match_operand:SI 0 "s_register_operand" "") 2825 [(set (match_operand:SI 0 "s_register_operand" "")
2826 (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" "")) 2826 (ior:SI (and:SI (not:SI (match_operand:SI 1 "s_register_operand" ""))
2827 (not:SI (match_operand:SI 2 "arm_rhs_operand" ""))) 2827 (not:SI (match_operand:SI 2 "arm_rhs_operand" "")))
2828 (match_operand:SI 3 "arm_rhs_operand" ""))) 2828 (match_operand:SI 3 "arm_rhs_operand" "")))
2829 (clobber (match_operand:SI 4 "s_register_operand" ""))] 2829 (clobber (match_operand:SI 4 "s_register_operand" ""))]
2830 "TARGET_32BIT" 2830 "TARGET_32BIT"
2831 [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2)) 2831 [(set (match_dup 4) (and:SI (ior:SI (match_dup 1) (match_dup 2))
2832 (not:SI (match_dup 3)))) 2832 (not:SI (match_dup 3))))
2833 (set (match_dup 0) (not:SI (match_dup 4)))] 2833 (set (match_dup 0) (not:SI (match_dup 4)))]
2834 "" 2834 ""
2835) 2835)
2836 2836
2837(define_insn "*andsi_iorsi3_notsi" 2837(define_insn "*andsi_iorsi3_notsi"
2838 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") 2838 [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r")
2839 (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r") 2839 (and:SI (ior:SI (match_operand:SI 1 "s_register_operand" "%0,r,r")
2840 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")) 2840 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))
2841 (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))] 2841 (not:SI (match_operand:SI 3 "arm_rhs_operand" "rI,rI,rI"))))]
2842 "TARGET_32BIT" 2842 "TARGET_32BIT"
2843 "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3" 2843 "orr%?\\t%0, %1, %2\;bic%?\\t%0, %0, %3"
2844 [(set_attr "length" "8") 2844 [(set_attr "length" "8")
2845 (set_attr "ce_count" "2") 2845 (set_attr "ce_count" "2")
2846 (set_attr "predicable" "yes")] 2846 (set_attr "predicable" "yes")]
2847) 2847)
2848 2848
2849; ??? Are these four splitters still beneficial when the Thumb-2 bitfield 2849; ??? Are these four splitters still beneficial when the Thumb-2 bitfield
2850; insns are available? 2850; insns are available?
2851(define_split 2851(define_split
2852 [(set (match_operand:SI 0 "s_register_operand" "") 2852 [(set (match_operand:SI 0 "s_register_operand" "")
2853 (match_operator:SI 1 "logical_binary_operator" 2853 (match_operator:SI 1 "logical_binary_operator"
2854 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "") 2854 [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
2855 (match_operand:SI 3 "const_int_operand" "") 2855 (match_operand:SI 3 "const_int_operand" "")
2856 (match_operand:SI 4 "const_int_operand" "")) 2856 (match_operand:SI 4 "const_int_operand" ""))
2857 (match_operator:SI 9 "logical_binary_operator" 2857 (match_operator:SI 9 "logical_binary_operator"
2858 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "") 2858 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
2859 (match_operand:SI 6 "const_int_operand" "")) 2859 (match_operand:SI 6 "const_int_operand" ""))
2860 (match_operand:SI 7 "s_register_operand" "")])])) 2860 (match_operand:SI 7 "s_register_operand" "")])]))
2861 (clobber (match_operand:SI 8 "s_register_operand" ""))] 2861 (clobber (match_operand:SI 8 "s_register_operand" ""))]
2862 "TARGET_32BIT 2862 "TARGET_32BIT
2863 && GET_CODE (operands[1]) == GET_CODE (operands[9]) 2863 && GET_CODE (operands[1]) == GET_CODE (operands[9])
2864 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" 2864 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
2865 [(set (match_dup 8) 2865 [(set (match_dup 8)
2866 (match_op_dup 1 2866 (match_op_dup 1
2867 [(ashift:SI (match_dup 2) (match_dup 4)) 2867 [(ashift:SI (match_dup 2) (match_dup 4))
2868 (match_dup 5)])) 2868 (match_dup 5)]))
2869 (set (match_dup 0) 2869 (set (match_dup 0)
2870 (match_op_dup 1 2870 (match_op_dup 1
2871 [(lshiftrt:SI (match_dup 8) (match_dup 6)) 2871 [(lshiftrt:SI (match_dup 8) (match_dup 6))
2872 (match_dup 7)]))] 2872 (match_dup 7)]))]
2873 " 2873 "
2874 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); 2874 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
2875") 2875")
2876 2876
2877(define_split 2877(define_split
2878 [(set (match_operand:SI 0 "s_register_operand" "") 2878 [(set (match_operand:SI 0 "s_register_operand" "")
2879 (match_operator:SI 1 "logical_binary_operator" 2879 (match_operator:SI 1 "logical_binary_operator"
2880 [(match_operator:SI 9 "logical_binary_operator" 2880 [(match_operator:SI 9 "logical_binary_operator"
2881 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "") 2881 [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "")
2882 (match_operand:SI 6 "const_int_operand" "")) 2882 (match_operand:SI 6 "const_int_operand" ""))
2883 (match_operand:SI 7 "s_register_operand" "")]) 2883 (match_operand:SI 7 "s_register_operand" "")])
2884 (zero_extract:SI (match_operand:SI 2 "s_register_operand" "") 2884 (zero_extract:SI (match_operand:SI 2 "s_register_operand" "")
2885 (match_operand:SI 3 "const_int_operand" "") 2885 (match_operand:SI 3 "const_int_operand" "")
2886 (match_operand:SI 4 "const_int_operand" ""))])) 2886 (match_operand:SI 4 "const_int_operand" ""))]))
2887 (clobber (match_operand:SI 8 "s_register_operand" ""))] 2887 (clobber (match_operand:SI 8 "s_register_operand" ""))]
2888 "TARGET_32BIT 2888 "TARGET_32BIT
2889 && GET_CODE (operands[1]) == GET_CODE (operands[9]) 2889 && GET_CODE (operands[1]) == GET_CODE (operands[9])
2890 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" 2890 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
2891 [(set (match_dup 8) 2891 [(set (match_dup 8)
2892 (match_op_dup 1 2892 (match_op_dup 1
2893 [(ashift:SI (match_dup 2) (match_dup 4)) 2893 [(ashift:SI (match_dup 2) (match_dup 4))
2894 (match_dup 5)])) 2894 (match_dup 5)]))
2895 (set (match_dup 0) 2895 (set (match_dup 0)
2896 (match_op_dup 1 2896 (match_op_dup 1
2897 [(lshiftrt:SI (match_dup 8) (match_dup 6)) 2897 [(lshiftrt:SI (match_dup 8) (match_dup 6))
2898 (match_dup 7)]))] 2898 (match_dup 7)]))]
2899 " 2899 "
2900 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); 2900 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
2901") 2901")
2902 2902
2903(define_split 2903(define_split
2904 [(set (match_operand:SI 0 "s_register_operand" "") 2904 [(set (match_operand:SI 0 "s_register_operand" "")
2905 (match_operator:SI 1 "logical_binary_operator" 2905 (match_operator:SI 1 "logical_binary_operator"
2906 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "") 2906 [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
2907 (match_operand:SI 3 "const_int_operand" "") 2907 (match_operand:SI 3 "const_int_operand" "")
2908 (match_operand:SI 4 "const_int_operand" "")) 2908 (match_operand:SI 4 "const_int_operand" ""))
2909 (match_operator:SI 9 "logical_binary_operator" 2909 (match_operator:SI 9 "logical_binary_operator"
2910 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "") 2910 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
2911 (match_operand:SI 6 "const_int_operand" "")) 2911 (match_operand:SI 6 "const_int_operand" ""))
2912 (match_operand:SI 7 "s_register_operand" "")])])) 2912 (match_operand:SI 7 "s_register_operand" "")])]))
2913 (clobber (match_operand:SI 8 "s_register_operand" ""))] 2913 (clobber (match_operand:SI 8 "s_register_operand" ""))]
2914 "TARGET_32BIT 2914 "TARGET_32BIT
2915 && GET_CODE (operands[1]) == GET_CODE (operands[9]) 2915 && GET_CODE (operands[1]) == GET_CODE (operands[9])
2916 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" 2916 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
2917 [(set (match_dup 8) 2917 [(set (match_dup 8)
2918 (match_op_dup 1 2918 (match_op_dup 1
2919 [(ashift:SI (match_dup 2) (match_dup 4)) 2919 [(ashift:SI (match_dup 2) (match_dup 4))
2920 (match_dup 5)])) 2920 (match_dup 5)]))
2921 (set (match_dup 0) 2921 (set (match_dup 0)
2922 (match_op_dup 1 2922 (match_op_dup 1
2923 [(ashiftrt:SI (match_dup 8) (match_dup 6)) 2923 [(ashiftrt:SI (match_dup 8) (match_dup 6))
2924 (match_dup 7)]))] 2924 (match_dup 7)]))]
2925 " 2925 "
2926 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); 2926 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
2927") 2927")
2928 2928
2929(define_split 2929(define_split
2930 [(set (match_operand:SI 0 "s_register_operand" "") 2930 [(set (match_operand:SI 0 "s_register_operand" "")
2931 (match_operator:SI 1 "logical_binary_operator" 2931 (match_operator:SI 1 "logical_binary_operator"
2932 [(match_operator:SI 9 "logical_binary_operator" 2932 [(match_operator:SI 9 "logical_binary_operator"
2933 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "") 2933 [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "")
2934 (match_operand:SI 6 "const_int_operand" "")) 2934 (match_operand:SI 6 "const_int_operand" ""))
2935 (match_operand:SI 7 "s_register_operand" "")]) 2935 (match_operand:SI 7 "s_register_operand" "")])
2936 (sign_extract:SI (match_operand:SI 2 "s_register_operand" "") 2936 (sign_extract:SI (match_operand:SI 2 "s_register_operand" "")
2937 (match_operand:SI 3 "const_int_operand" "") 2937 (match_operand:SI 3 "const_int_operand" "")
2938 (match_operand:SI 4 "const_int_operand" ""))])) 2938 (match_operand:SI 4 "const_int_operand" ""))]))
2939 (clobber (match_operand:SI 8 "s_register_operand" ""))] 2939 (clobber (match_operand:SI 8 "s_register_operand" ""))]
2940 "TARGET_32BIT 2940 "TARGET_32BIT
2941 && GET_CODE (operands[1]) == GET_CODE (operands[9]) 2941 && GET_CODE (operands[1]) == GET_CODE (operands[9])
2942 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" 2942 && INTVAL (operands[3]) == 32 - INTVAL (operands[6])"
2943 [(set (match_dup 8) 2943 [(set (match_dup 8)
2944 (match_op_dup 1 2944 (match_op_dup 1
2945 [(ashift:SI (match_dup 2) (match_dup 4)) 2945 [(ashift:SI (match_dup 2) (match_dup 4))
2946 (match_dup 5)])) 2946 (match_dup 5)]))
2947 (set (match_dup 0) 2947 (set (match_dup 0)
2948 (match_op_dup 1 2948 (match_op_dup 1
2949 [(ashiftrt:SI (match_dup 8) (match_dup 6)) 2949 [(ashiftrt:SI (match_dup 8) (match_dup 6))
2950 (match_dup 7)]))] 2950 (match_dup 7)]))]
2951 " 2951 "
2952 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); 2952 operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4])));
2953") 2953")
2954  2954
2955 2955
2956;; Minimum and maximum insns 2956;; Minimum and maximum insns
2957 2957
2958(define_expand "smaxsi3" 2958(define_expand "smaxsi3"
2959 [(parallel [ 2959 [(parallel [
2960 (set (match_operand:SI 0 "s_register_operand" "") 2960 (set (match_operand:SI 0 "s_register_operand" "")
2961 (smax:SI (match_operand:SI 1 "s_register_operand" "") 2961 (smax:SI (match_operand:SI 1 "s_register_operand" "")
2962 (match_operand:SI 2 "arm_rhs_operand" ""))) 2962 (match_operand:SI 2 "arm_rhs_operand" "")))
2963 (clobber (reg:CC CC_REGNUM))])] 2963 (clobber (reg:CC CC_REGNUM))])]
2964 "TARGET_32BIT" 2964 "TARGET_32BIT"
2965 " 2965 "
2966 if (operands[2] == const0_rtx || operands[2] == constm1_rtx) 2966 if (operands[2] == const0_rtx || operands[2] == constm1_rtx)
2967 { 2967 {
2968 /* No need for a clobber of the condition code register here. */ 2968 /* No need for a clobber of the condition code register here. */
2969 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 2969 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2970 gen_rtx_SMAX (SImode, operands[1], 2970 gen_rtx_SMAX (SImode, operands[1],
2971 operands[2]))); 2971 operands[2])));
2972 DONE; 2972 DONE;
2973 } 2973 }
2974") 2974")
2975 2975
2976(define_insn "*smax_0" 2976(define_insn "*smax_0"
2977 [(set (match_operand:SI 0 "s_register_operand" "=r") 2977 [(set (match_operand:SI 0 "s_register_operand" "=r")
2978 (smax:SI (match_operand:SI 1 "s_register_operand" "r") 2978 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
2979 (const_int 0)))] 2979 (const_int 0)))]
2980 "TARGET_32BIT" 2980 "TARGET_32BIT"
2981 "bic%?\\t%0, %1, %1, asr #31" 2981 "bic%?\\t%0, %1, %1, asr #31"
2982 [(set_attr "predicable" "yes")] 2982 [(set_attr "predicable" "yes")]
2983) 2983)
2984 2984
2985(define_insn "*smax_m1" 2985(define_insn "*smax_m1"
2986 [(set (match_operand:SI 0 "s_register_operand" "=r") 2986 [(set (match_operand:SI 0 "s_register_operand" "=r")
2987 (smax:SI (match_operand:SI 1 "s_register_operand" "r") 2987 (smax:SI (match_operand:SI 1 "s_register_operand" "r")
2988 (const_int -1)))] 2988 (const_int -1)))]
2989 "TARGET_32BIT" 2989 "TARGET_32BIT"
2990 "orr%?\\t%0, %1, %1, asr #31" 2990 "orr%?\\t%0, %1, %1, asr #31"
2991 [(set_attr "predicable" "yes")] 2991 [(set_attr "predicable" "yes")]
2992) 2992)
2993 2993
2994(define_insn "*arm_smax_insn" 2994(define_insn "*arm_smax_insn"
2995 [(set (match_operand:SI 0 "s_register_operand" "=r,r") 2995 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
2996 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r") 2996 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
2997 (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) 2997 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
2998 (clobber (reg:CC CC_REGNUM))] 2998 (clobber (reg:CC CC_REGNUM))]
2999 "TARGET_ARM" 2999 "TARGET_ARM"
3000 "@ 3000 "@
3001 cmp\\t%1, %2\;movlt\\t%0, %2 3001 cmp\\t%1, %2\;movlt\\t%0, %2
3002 cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" 3002 cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
3003 [(set_attr "conds" "clob") 3003 [(set_attr "conds" "clob")
3004 (set_attr "length" "8,12")] 3004 (set_attr "length" "8,12")]
3005) 3005)
3006 3006
3007(define_expand "sminsi3" 3007(define_expand "sminsi3"
3008 [(parallel [ 3008 [(parallel [
3009 (set (match_operand:SI 0 "s_register_operand" "") 3009 (set (match_operand:SI 0 "s_register_operand" "")
3010 (smin:SI (match_operand:SI 1 "s_register_operand" "") 3010 (smin:SI (match_operand:SI 1 "s_register_operand" "")
3011 (match_operand:SI 2 "arm_rhs_operand" ""))) 3011 (match_operand:SI 2 "arm_rhs_operand" "")))
3012 (clobber (reg:CC CC_REGNUM))])] 3012 (clobber (reg:CC CC_REGNUM))])]
3013 "TARGET_32BIT" 3013 "TARGET_32BIT"
3014 " 3014 "
3015 if (operands[2] == const0_rtx) 3015 if (operands[2] == const0_rtx)
3016 { 3016 {
3017 /* No need for a clobber of the condition code register here. */ 3017 /* No need for a clobber of the condition code register here. */
3018 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 3018 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3019 gen_rtx_SMIN (SImode, operands[1], 3019 gen_rtx_SMIN (SImode, operands[1],
3020 operands[2]))); 3020 operands[2])));
3021 DONE; 3021 DONE;
3022 } 3022 }
3023") 3023")
3024 3024
3025(define_insn "*smin_0" 3025(define_insn "*smin_0"
3026 [(set (match_operand:SI 0 "s_register_operand" "=r") 3026 [(set (match_operand:SI 0 "s_register_operand" "=r")
3027 (smin:SI (match_operand:SI 1 "s_register_operand" "r") 3027 (smin:SI (match_operand:SI 1 "s_register_operand" "r")
3028 (const_int 0)))] 3028 (const_int 0)))]
3029 "TARGET_32BIT" 3029 "TARGET_32BIT"
3030 "and%?\\t%0, %1, %1, asr #31" 3030 "and%?\\t%0, %1, %1, asr #31"
3031 [(set_attr "predicable" "yes")] 3031 [(set_attr "predicable" "yes")]
3032) 3032)
3033 3033
3034(define_insn "*arm_smin_insn" 3034(define_insn "*arm_smin_insn"
3035 [(set (match_operand:SI 0 "s_register_operand" "=r,r") 3035 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3036 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r") 3036 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
3037 (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) 3037 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
3038 (clobber (reg:CC CC_REGNUM))] 3038 (clobber (reg:CC CC_REGNUM))]
3039 "TARGET_ARM" 3039 "TARGET_ARM"
3040 "@ 3040 "@
3041 cmp\\t%1, %2\;movge\\t%0, %2 3041 cmp\\t%1, %2\;movge\\t%0, %2
3042 cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" 3042 cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
3043 [(set_attr "conds" "clob") 3043 [(set_attr "conds" "clob")
3044 (set_attr "length" "8,12")] 3044 (set_attr "length" "8,12")]
3045) 3045)
3046 3046
3047(define_expand "umaxsi3" 3047(define_expand "umaxsi3"
3048 [(parallel [ 3048 [(parallel [
3049 (set (match_operand:SI 0 "s_register_operand" "") 3049 (set (match_operand:SI 0 "s_register_operand" "")
3050 (umax:SI (match_operand:SI 1 "s_register_operand" "") 3050 (umax:SI (match_operand:SI 1 "s_register_operand" "")
3051 (match_operand:SI 2 "arm_rhs_operand" ""))) 3051 (match_operand:SI 2 "arm_rhs_operand" "")))
3052 (clobber (reg:CC CC_REGNUM))])] 3052 (clobber (reg:CC CC_REGNUM))])]
3053 "TARGET_32BIT" 3053 "TARGET_32BIT"
3054 "" 3054 ""
3055) 3055)
3056 3056
3057(define_insn "*arm_umaxsi3" 3057(define_insn "*arm_umaxsi3"
3058 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 3058 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3059 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 3059 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3060 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 3060 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3061 (clobber (reg:CC CC_REGNUM))] 3061 (clobber (reg:CC CC_REGNUM))]
3062 "TARGET_ARM" 3062 "TARGET_ARM"
3063 "@ 3063 "@
3064 cmp\\t%1, %2\;movcc\\t%0, %2 3064 cmp\\t%1, %2\;movcc\\t%0, %2
3065 cmp\\t%1, %2\;movcs\\t%0, %1 3065 cmp\\t%1, %2\;movcs\\t%0, %1
3066 cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" 3066 cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2"
3067 [(set_attr "conds" "clob") 3067 [(set_attr "conds" "clob")
3068 (set_attr "length" "8,8,12")] 3068 (set_attr "length" "8,8,12")]
3069) 3069)
3070 3070
3071(define_expand "uminsi3" 3071(define_expand "uminsi3"
3072 [(parallel [ 3072 [(parallel [
3073 (set (match_operand:SI 0 "s_register_operand" "") 3073 (set (match_operand:SI 0 "s_register_operand" "")
3074 (umin:SI (match_operand:SI 1 "s_register_operand" "") 3074 (umin:SI (match_operand:SI 1 "s_register_operand" "")
3075 (match_operand:SI 2 "arm_rhs_operand" ""))) 3075 (match_operand:SI 2 "arm_rhs_operand" "")))
3076 (clobber (reg:CC CC_REGNUM))])] 3076 (clobber (reg:CC CC_REGNUM))])]
3077 "TARGET_32BIT" 3077 "TARGET_32BIT"
3078 "" 3078 ""
3079) 3079)
3080 3080
3081(define_insn "*arm_uminsi3" 3081(define_insn "*arm_uminsi3"
3082 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") 3082 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
3083 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") 3083 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
3084 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) 3084 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
3085 (clobber (reg:CC CC_REGNUM))] 3085 (clobber (reg:CC CC_REGNUM))]
3086 "TARGET_ARM" 3086 "TARGET_ARM"
3087 "@ 3087 "@
3088 cmp\\t%1, %2\;movcs\\t%0, %2 3088 cmp\\t%1, %2\;movcs\\t%0, %2
3089 cmp\\t%1, %2\;movcc\\t%0, %1 3089 cmp\\t%1, %2\;movcc\\t%0, %1
3090 cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" 3090 cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2"
3091 [(set_attr "conds" "clob") 3091 [(set_attr "conds" "clob")
3092 (set_attr "length" "8,8,12")] 3092 (set_attr "length" "8,8,12")]
3093) 3093)
3094 3094
3095(define_insn "*store_minmaxsi" 3095(define_insn "*store_minmaxsi"
3096 [(set (match_operand:SI 0 "memory_operand" "=m") 3096 [(set (match_operand:SI 0 "memory_operand" "=m")
3097 (match_operator:SI 3 "minmax_operator" 3097 (match_operator:SI 3 "minmax_operator"
3098 [(match_operand:SI 1 "s_register_operand" "r") 3098 [(match_operand:SI 1 "s_register_operand" "r")
3099 (match_operand:SI 2 "s_register_operand" "r")])) 3099 (match_operand:SI 2 "s_register_operand" "r")]))
3100 (clobber (reg:CC CC_REGNUM))] 3100 (clobber (reg:CC CC_REGNUM))]
3101 "TARGET_32BIT" 3101 "TARGET_32BIT"
3102 "* 3102 "*
3103 operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode, 3103 operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode,
3104 operands[1], operands[2]); 3104 operands[1], operands[2]);
3105 output_asm_insn (\"cmp\\t%1, %2\", operands); 3105 output_asm_insn (\"cmp\\t%1, %2\", operands);
3106 if (TARGET_THUMB2) 3106 if (TARGET_THUMB2)
3107 output_asm_insn (\"ite\t%d3\", operands); 3107 output_asm_insn (\"ite\t%d3\", operands);
3108 output_asm_insn (\"str%d3\\t%1, %0\", operands); 3108 output_asm_insn (\"str%d3\\t%1, %0\", operands);
3109 output_asm_insn (\"str%D3\\t%2, %0\", operands); 3109 output_asm_insn (\"str%D3\\t%2, %0\", operands);
3110 return \"\"; 3110 return \"\";
3111 " 3111 "
3112 [(set_attr "conds" "clob") 3112 [(set_attr "conds" "clob")
3113 (set (attr "length") 3113 (set (attr "length")
3114 (if_then_else (eq_attr "is_thumb" "yes") 3114 (if_then_else (eq_attr "is_thumb" "yes")
3115 (const_int 14) 3115 (const_int 14)
3116 (const_int 12))) 3116 (const_int 12)))
3117 (set_attr "type" "store1")] 3117 (set_attr "type" "store1")]
3118) 3118)
3119 3119
3120; Reject the frame pointer in operand[1], since reloading this after 3120; Reject the frame pointer in operand[1], since reloading this after
3121; it has been eliminated can cause carnage. 3121; it has been eliminated can cause carnage.
3122(define_insn "*minmax_arithsi" 3122(define_insn "*minmax_arithsi"
3123 [(set (match_operand:SI 0 "s_register_operand" "=r,r") 3123 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
3124 (match_operator:SI 4 "shiftable_operator" 3124 (match_operator:SI 4 "shiftable_operator"
3125 [(match_operator:SI 5 "minmax_operator" 3125 [(match_operator:SI 5 "minmax_operator"
3126 [(match_operand:SI 2 "s_register_operand" "r,r") 3126 [(match_operand:SI 2 "s_register_operand" "r,r")
3127 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")]) 3127 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
3128 (match_operand:SI 1 "s_register_operand" "0,?r")])) 3128 (match_operand:SI 1 "s_register_operand" "0,?r")]))
3129 (clobber (reg:CC CC_REGNUM))] 3129 (clobber (reg:CC CC_REGNUM))]
3130 "TARGET_32BIT && !arm_eliminable_register (operands[1])" 3130 "TARGET_32BIT && !arm_eliminable_register (operands[1])"
3131 "* 3131 "*
3132 { 3132 {
3133 enum rtx_code code = GET_CODE (operands[4]); 3133 enum rtx_code code = GET_CODE (operands[4]);
3134 bool need_else; 3134 bool need_else;
3135 3135
3136 if (which_alternative != 0 || operands[3] != const0_rtx 3136 if (which_alternative != 0 || operands[3] != const0_rtx
3137 || (code != PLUS && code != MINUS && code != IOR && code != XOR)) 3137 || (code != PLUS && code != IOR && code != XOR))
3138 need_else = true; 3138 need_else = true;
3139 else 3139 else
3140 need_else = false; 3140 need_else = false;
3141 3141
3142 operands[5] = gen_rtx_fmt_ee (minmax_code (operands[5]), SImode, 3142 operands[5] = gen_rtx_fmt_ee (minmax_code (operands[5]), SImode,
3143 operands[2], operands[3]); 3143 operands[2], operands[3]);
3144 output_asm_insn (\"cmp\\t%2, %3\", operands); 3144 output_asm_insn (\"cmp\\t%2, %3\", operands);
3145 if (TARGET_THUMB2) 3145 if (TARGET_THUMB2)
3146 { 3146 {
3147 if (need_else) 3147 if (need_else)
3148 output_asm_insn (\"ite\\t%d5\", operands); 3148 output_asm_insn (\"ite\\t%d5\", operands);
3149 else 3149 else
3150 output_asm_insn (\"it\\t%d5\", operands); 3150 output_asm_insn (\"it\\t%d5\", operands);
3151 } 3151 }
3152 output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands); 3152 output_asm_insn (\"%i4%d5\\t%0, %1, %2\", operands);
3153 if (need_else) 3153 if (need_else)
3154 output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands); 3154 output_asm_insn (\"%i4%D5\\t%0, %1, %3\", operands);
3155 return \"\"; 3155 return \"\";
3156 }" 3156 }"
3157 [(set_attr "conds" "clob") 3157 [(set_attr "conds" "clob")
3158 (set (attr "length") 3158 (set (attr "length")
3159 (if_then_else (eq_attr "is_thumb" "yes") 3159 (if_then_else (eq_attr "is_thumb" "yes")
3160 (const_int 14) 3160 (const_int 14)
3161 (const_int 12)))] 3161 (const_int 12)))]
3162) 3162)
3163 3163
3164  3164
3165;; Shift and rotation insns 3165;; Shift and rotation insns
3166 3166
3167(define_expand "ashldi3" 3167(define_expand "ashldi3"
3168 [(set (match_operand:DI 0 "s_register_operand" "") 3168 [(set (match_operand:DI 0 "s_register_operand" "")
3169 (ashift:DI (match_operand:DI 1 "s_register_operand" "") 3169 (ashift:DI (match_operand:DI 1 "s_register_operand" "")
3170 (match_operand:SI 2 "reg_or_int_operand" "")))] 3170 (match_operand:SI 2 "reg_or_int_operand" "")))]
3171 "TARGET_32BIT" 3171 "TARGET_32BIT"
3172 " 3172 "
3173 if (GET_CODE (operands[2]) == CONST_INT) 3173 if (GET_CODE (operands[2]) == CONST_INT)
3174 { 3174 {
3175 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) 3175 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1)
3176 { 3176 {
3177 emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1])); 3177 emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1]));
3178 DONE; 3178 DONE;
3179 } 3179 }
3180 /* Ideally we shouldn't fail here if we could know that operands[1]  3180 /* Ideally we shouldn't fail here if we could know that operands[1]
3181 ends up already living in an iwmmxt register. Otherwise it's 3181 ends up already living in an iwmmxt register. Otherwise it's
3182 cheaper to have the alternate code being generated than moving 3182 cheaper to have the alternate code being generated than moving
3183 values to iwmmxt regs and back. */ 3183 values to iwmmxt regs and back. */
3184 FAIL; 3184 FAIL;
3185 } 3185 }
3186 else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) 3186 else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK))
3187 FAIL; 3187 FAIL;
3188 " 3188 "
3189) 3189)
3190 3190
3191(define_insn "arm_ashldi3_1bit" 3191(define_insn "arm_ashldi3_1bit"
3192 [(set (match_operand:DI 0 "s_register_operand" "=&r,r") 3192 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
3193 (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") 3193 (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
3194 (const_int 1))) 3194 (const_int 1)))
3195 (clobber (reg:CC CC_REGNUM))] 3195 (clobber (reg:CC CC_REGNUM))]
3196 "TARGET_32BIT" 3196 "TARGET_32BIT"
3197 "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" 3197 "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1"
3198 [(set_attr "conds" "clob") 3198 [(set_attr "conds" "clob")
3199 (set_attr "length" "8")] 3199 (set_attr "length" "8")]
3200) 3200)
3201 3201
3202(define_expand "ashlsi3" 3202(define_expand "ashlsi3"
3203 [(set (match_operand:SI 0 "s_register_operand" "") 3203 [(set (match_operand:SI 0 "s_register_operand" "")
3204 (ashift:SI (match_operand:SI 1 "s_register_operand" "") 3204 (ashift:SI (match_operand:SI 1 "s_register_operand" "")
3205 (match_operand:SI 2 "arm_rhs_operand" "")))] 3205 (match_operand:SI 2 "arm_rhs_operand" "")))]
3206 "TARGET_EITHER" 3206 "TARGET_EITHER"
3207 " 3207 "
3208 if (GET_CODE (operands[2]) == CONST_INT 3208 if (GET_CODE (operands[2]) == CONST_INT
3209 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 3209 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
3210 { 3210 {
3211 emit_insn (gen_movsi (operands[0], const0_rtx)); 3211 emit_insn (gen_movsi (operands[0], const0_rtx));
3212 DONE; 3212 DONE;
3213 } 3213 }
3214 " 3214 "
3215) 3215)
3216 3216
3217(define_insn "*thumb1_ashlsi3" 3217(define_insn "*thumb1_ashlsi3"
3218 [(set (match_operand:SI 0 "register_operand" "=l,l") 3218 [(set (match_operand:SI 0 "register_operand" "=l,l")
3219 (ashift:SI (match_operand:SI 1 "register_operand" "l,0") 3219 (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
3220 (match_operand:SI 2 "nonmemory_operand" "N,l")))] 3220 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
3221 "TARGET_THUMB1" 3221 "TARGET_THUMB1"
3222 "lsl\\t%0, %1, %2" 3222 "lsl\\t%0, %1, %2"
3223 [(set_attr "length" "2")] 3223 [(set_attr "length" "2")]
3224) 3224)
3225 3225
3226(define_expand "ashrdi3" 3226(define_expand "ashrdi3"
3227 [(set (match_operand:DI 0 "s_register_operand" "") 3227 [(set (match_operand:DI 0 "s_register_operand" "")
3228 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "") 3228 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "")
3229 (match_operand:SI 2 "reg_or_int_operand" "")))] 3229 (match_operand:SI 2 "reg_or_int_operand" "")))]
3230 "TARGET_32BIT" 3230 "TARGET_32BIT"
3231 " 3231 "
3232 if (GET_CODE (operands[2]) == CONST_INT) 3232 if (GET_CODE (operands[2]) == CONST_INT)
3233 { 3233 {
3234 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) 3234 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1)
3235 { 3235 {
3236 emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1])); 3236 emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1]));
3237 DONE; 3237 DONE;
3238 } 3238 }
3239 /* Ideally we shouldn't fail here if we could know that operands[1]  3239 /* Ideally we shouldn't fail here if we could know that operands[1]
3240 ends up already living in an iwmmxt register. Otherwise it's 3240 ends up already living in an iwmmxt register. Otherwise it's
3241 cheaper to have the alternate code being generated than moving 3241 cheaper to have the alternate code being generated than moving
3242 values to iwmmxt regs and back. */ 3242 values to iwmmxt regs and back. */
3243 FAIL; 3243 FAIL;
3244 } 3244 }
3245 else if (!TARGET_REALLY_IWMMXT) 3245 else if (!TARGET_REALLY_IWMMXT)
3246 FAIL; 3246 FAIL;
3247 " 3247 "
3248) 3248)
3249 3249
3250(define_insn "arm_ashrdi3_1bit" 3250(define_insn "arm_ashrdi3_1bit"
3251 [(set (match_operand:DI 0 "s_register_operand" "=&r,r") 3251 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
3252 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") 3252 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
3253 (const_int 1))) 3253 (const_int 1)))
3254 (clobber (reg:CC CC_REGNUM))] 3254 (clobber (reg:CC CC_REGNUM))]
3255 "TARGET_32BIT" 3255 "TARGET_32BIT"
3256 "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" 3256 "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx"
3257 [(set_attr "conds" "clob") 3257 [(set_attr "conds" "clob")
3258 (set_attr "length" "8")] 3258 (set_attr "length" "8")]
3259) 3259)
3260 3260
3261(define_expand "ashrsi3" 3261(define_expand "ashrsi3"
3262 [(set (match_operand:SI 0 "s_register_operand" "") 3262 [(set (match_operand:SI 0 "s_register_operand" "")
3263 (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") 3263 (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "")
3264 (match_operand:SI 2 "arm_rhs_operand" "")))] 3264 (match_operand:SI 2 "arm_rhs_operand" "")))]
3265 "TARGET_EITHER" 3265 "TARGET_EITHER"
3266 " 3266 "
3267 if (GET_CODE (operands[2]) == CONST_INT 3267 if (GET_CODE (operands[2]) == CONST_INT
3268 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 3268 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
3269 operands[2] = GEN_INT (31); 3269 operands[2] = GEN_INT (31);
3270 " 3270 "
3271) 3271)
3272 3272
3273(define_insn "*thumb1_ashrsi3" 3273(define_insn "*thumb1_ashrsi3"
3274 [(set (match_operand:SI 0 "register_operand" "=l,l") 3274 [(set (match_operand:SI 0 "register_operand" "=l,l")
3275 (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0") 3275 (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
3276 (match_operand:SI 2 "nonmemory_operand" "N,l")))] 3276 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
3277 "TARGET_THUMB1" 3277 "TARGET_THUMB1"
3278 "asr\\t%0, %1, %2" 3278 "asr\\t%0, %1, %2"
3279 [(set_attr "length" "2")] 3279 [(set_attr "length" "2")]
3280) 3280)
3281 3281
3282(define_expand "lshrdi3" 3282(define_expand "lshrdi3"
3283 [(set (match_operand:DI 0 "s_register_operand" "") 3283 [(set (match_operand:DI 0 "s_register_operand" "")
3284 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "") 3284 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "")
3285 (match_operand:SI 2 "reg_or_int_operand" "")))] 3285 (match_operand:SI 2 "reg_or_int_operand" "")))]
3286 "TARGET_32BIT" 3286 "TARGET_32BIT"
3287 " 3287 "
3288 if (GET_CODE (operands[2]) == CONST_INT) 3288 if (GET_CODE (operands[2]) == CONST_INT)
3289 { 3289 {
3290 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) 3290 if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1)
3291 { 3291 {
3292 emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1])); 3292 emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1]));
3293 DONE; 3293 DONE;
3294 } 3294 }
3295 /* Ideally we shouldn't fail here if we could know that operands[1]  3295 /* Ideally we shouldn't fail here if we could know that operands[1]
3296 ends up already living in an iwmmxt register. Otherwise it's 3296 ends up already living in an iwmmxt register. Otherwise it's
3297 cheaper to have the alternate code being generated than moving 3297 cheaper to have the alternate code being generated than moving
3298 values to iwmmxt regs and back. */ 3298 values to iwmmxt regs and back. */
3299 FAIL; 3299 FAIL;
3300 } 3300 }
3301 else if (!TARGET_REALLY_IWMMXT) 3301 else if (!TARGET_REALLY_IWMMXT)
3302 FAIL; 3302 FAIL;
3303 " 3303 "
3304) 3304)
3305 3305
3306(define_insn "arm_lshrdi3_1bit" 3306(define_insn "arm_lshrdi3_1bit"
3307 [(set (match_operand:DI 0 "s_register_operand" "=&r,r") 3307 [(set (match_operand:DI 0 "s_register_operand" "=&r,r")
3308 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") 3308 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
3309 (const_int 1))) 3309 (const_int 1)))
3310 (clobber (reg:CC CC_REGNUM))] 3310 (clobber (reg:CC CC_REGNUM))]
3311 "TARGET_32BIT" 3311 "TARGET_32BIT"
3312 "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" 3312 "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx"
3313 [(set_attr "conds" "clob") 3313 [(set_attr "conds" "clob")
3314 (set_attr "length" "8")] 3314 (set_attr "length" "8")]
3315) 3315)
3316 3316
3317(define_expand "lshrsi3" 3317(define_expand "lshrsi3"
3318 [(set (match_operand:SI 0 "s_register_operand" "") 3318 [(set (match_operand:SI 0 "s_register_operand" "")
3319 (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "") 3319 (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "")
3320 (match_operand:SI 2 "arm_rhs_operand" "")))] 3320 (match_operand:SI 2 "arm_rhs_operand" "")))]
3321 "TARGET_EITHER" 3321 "TARGET_EITHER"
3322 " 3322 "
3323 if (GET_CODE (operands[2]) == CONST_INT 3323 if (GET_CODE (operands[2]) == CONST_INT
3324 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 3324 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
3325 { 3325 {
3326 emit_insn (gen_movsi (operands[0], const0_rtx)); 3326 emit_insn (gen_movsi (operands[0], const0_rtx));
3327 DONE; 3327 DONE;
3328 } 3328 }
3329 " 3329 "
3330) 3330)
3331 3331
3332(define_insn "*thumb1_lshrsi3" 3332(define_insn "*thumb1_lshrsi3"
3333 [(set (match_operand:SI 0 "register_operand" "=l,l") 3333 [(set (match_operand:SI 0 "register_operand" "=l,l")
3334 (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0") 3334 (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
3335 (match_operand:SI 2 "nonmemory_operand" "N,l")))] 3335 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
3336 "TARGET_THUMB1" 3336 "TARGET_THUMB1"
3337 "lsr\\t%0, %1, %2" 3337 "lsr\\t%0, %1, %2"
3338 [(set_attr "length" "2")] 3338 [(set_attr "length" "2")]
3339) 3339)
3340 3340
3341(define_expand "rotlsi3" 3341(define_expand "rotlsi3"
3342 [(set (match_operand:SI 0 "s_register_operand" "") 3342 [(set (match_operand:SI 0 "s_register_operand" "")
3343 (rotatert:SI (match_operand:SI 1 "s_register_operand" "") 3343 (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
3344 (match_operand:SI 2 "reg_or_int_operand" "")))] 3344 (match_operand:SI 2 "reg_or_int_operand" "")))]
3345 "TARGET_32BIT" 3345 "TARGET_32BIT"
3346 " 3346 "
3347 if (GET_CODE (operands[2]) == CONST_INT) 3347 if (GET_CODE (operands[2]) == CONST_INT)
3348 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32); 3348 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
3349 else 3349 else
3350 { 3350 {
3351 rtx reg = gen_reg_rtx (SImode); 3351 rtx reg = gen_reg_rtx (SImode);
3352 emit_insn (gen_subsi3 (reg, GEN_INT (32), operands[2])); 3352 emit_insn (gen_subsi3 (reg, GEN_INT (32), operands[2]));
3353 operands[2] = reg; 3353 operands[2] = reg;
3354 } 3354 }
3355 " 3355 "
3356) 3356)
3357 3357
3358(define_expand "rotrsi3" 3358(define_expand "rotrsi3"
3359 [(set (match_operand:SI 0 "s_register_operand" "") 3359 [(set (match_operand:SI 0 "s_register_operand" "")
3360 (rotatert:SI (match_operand:SI 1 "s_register_operand" "") 3360 (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
3361 (match_operand:SI 2 "arm_rhs_operand" "")))] 3361 (match_operand:SI 2 "arm_rhs_operand" "")))]
3362 "TARGET_EITHER" 3362 "TARGET_EITHER"
3363 " 3363 "
3364 if (TARGET_32BIT) 3364 if (TARGET_32BIT)
3365 { 3365 {
3366 if (GET_CODE (operands[2]) == CONST_INT 3366 if (GET_CODE (operands[2]) == CONST_INT
3367 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31) 3367 && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
3368 operands[2] = GEN_INT (INTVAL (operands[2]) % 32); 3368 operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
3369 } 3369 }
3370 else /* TARGET_THUMB1 */ 3370 else /* TARGET_THUMB1 */
3371 { 3371 {
3372 if (GET_CODE (operands [2]) == CONST_INT) 3372 if (GET_CODE (operands [2]) == CONST_INT)
3373 operands [2] = force_reg (SImode, operands[2]); 3373 operands [2] = force_reg (SImode, operands[2]);
3374 } 3374 }
3375 " 3375 "
3376) 3376)
3377 3377
3378(define_insn "*thumb1_rotrsi3" 3378(define_insn "*thumb1_rotrsi3"
3379 [(set (match_operand:SI 0 "register_operand" "=l") 3379 [(set (match_operand:SI 0 "register_operand" "=l")
3380 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 3380 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
3381 (match_operand:SI 2 "register_operand" "l")))] 3381 (match_operand:SI 2 "register_operand" "l")))]
3382 "TARGET_THUMB1" 3382 "TARGET_THUMB1"
3383 "ror\\t%0, %0, %2" 3383 "ror\\t%0, %0, %2"
3384 [(set_attr "length" "2")] 3384 [(set_attr "length" "2")]
3385) 3385)
3386 3386
3387(define_insn "*arm_shiftsi3" 3387(define_insn "*arm_shiftsi3"
3388 [(set (match_operand:SI 0 "s_register_operand" "=r") 3388 [(set (match_operand:SI 0 "s_register_operand" "=r")
3389 (match_operator:SI 3 "shift_operator" 3389 (match_operator:SI 3 "shift_operator"
3390 [(match_operand:SI 1 "s_register_operand" "r") 3390 [(match_operand:SI 1 "s_register_operand" "r")
3391 (match_operand:SI 2 "reg_or_int_operand" "rM")]))] 3391 (match_operand:SI 2 "reg_or_int_operand" "rM")]))]
3392 "TARGET_32BIT" 3392 "TARGET_32BIT"
3393 "* return arm_output_shift(operands, 0);" 3393 "* return arm_output_shift(operands, 0);"
3394 [(set_attr "predicable" "yes") 3394 [(set_attr "predicable" "yes")
3395 (set_attr "shift" "1") 3395 (set_attr "shift" "1")
3396 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") 3396 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3397 (const_string "alu_shift") 3397 (const_string "alu_shift")
3398 (const_string "alu_shift_reg")))] 3398 (const_string "alu_shift_reg")))]
3399) 3399)
3400 3400
3401(define_insn "*shiftsi3_compare0" 3401(define_insn "*shiftsi3_compare0"
3402 [(set (reg:CC_NOOV CC_REGNUM) 3402 [(set (reg:CC_NOOV CC_REGNUM)
3403 (compare:CC_NOOV (match_operator:SI 3 "shift_operator" 3403 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
3404 [(match_operand:SI 1 "s_register_operand" "r") 3404 [(match_operand:SI 1 "s_register_operand" "r")
3405 (match_operand:SI 2 "arm_rhs_operand" "rM")]) 3405 (match_operand:SI 2 "arm_rhs_operand" "rM")])
3406 (const_int 0))) 3406 (const_int 0)))
3407 (set (match_operand:SI 0 "s_register_operand" "=r") 3407 (set (match_operand:SI 0 "s_register_operand" "=r")
3408 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] 3408 (match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
3409 "TARGET_32BIT" 3409 "TARGET_32BIT"
3410 "* return arm_output_shift(operands, 1);" 3410 "* return arm_output_shift(operands, 1);"
3411 [(set_attr "conds" "set") 3411 [(set_attr "conds" "set")
3412 (set_attr "shift" "1") 3412 (set_attr "shift" "1")
3413 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") 3413 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3414 (const_string "alu_shift") 3414 (const_string "alu_shift")
3415 (const_string "alu_shift_reg")))] 3415 (const_string "alu_shift_reg")))]
3416) 3416)
3417 3417
3418(define_insn "*shiftsi3_compare0_scratch" 3418(define_insn "*shiftsi3_compare0_scratch"
3419 [(set (reg:CC_NOOV CC_REGNUM) 3419 [(set (reg:CC_NOOV CC_REGNUM)
3420 (compare:CC_NOOV (match_operator:SI 3 "shift_operator" 3420 (compare:CC_NOOV (match_operator:SI 3 "shift_operator"
3421 [(match_operand:SI 1 "s_register_operand" "r") 3421 [(match_operand:SI 1 "s_register_operand" "r")
3422 (match_operand:SI 2 "arm_rhs_operand" "rM")]) 3422 (match_operand:SI 2 "arm_rhs_operand" "rM")])
3423 (const_int 0))) 3423 (const_int 0)))
3424 (clobber (match_scratch:SI 0 "=r"))] 3424 (clobber (match_scratch:SI 0 "=r"))]
3425 "TARGET_32BIT" 3425 "TARGET_32BIT"
3426 "* return arm_output_shift(operands, 1);" 3426 "* return arm_output_shift(operands, 1);"
3427 [(set_attr "conds" "set") 3427 [(set_attr "conds" "set")
3428 (set_attr "shift" "1")] 3428 (set_attr "shift" "1")]
3429) 3429)
3430 3430
3431(define_insn "*arm_notsi_shiftsi" 3431(define_insn "*arm_notsi_shiftsi"
3432 [(set (match_operand:SI 0 "s_register_operand" "=r") 3432 [(set (match_operand:SI 0 "s_register_operand" "=r")
3433 (not:SI (match_operator:SI 3 "shift_operator" 3433 (not:SI (match_operator:SI 3 "shift_operator"
3434 [(match_operand:SI 1 "s_register_operand" "r") 3434 [(match_operand:SI 1 "s_register_operand" "r")
3435 (match_operand:SI 2 "arm_rhs_operand" "rM")])))] 3435 (match_operand:SI 2 "arm_rhs_operand" "rM")])))]
3436 "TARGET_ARM" 3436 "TARGET_ARM"
3437 "mvn%?\\t%0, %1%S3" 3437 "mvn%?\\t%0, %1%S3"
3438 [(set_attr "predicable" "yes") 3438 [(set_attr "predicable" "yes")
3439 (set_attr "shift" "1") 3439 (set_attr "shift" "1")
3440 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") 3440 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3441 (const_string "alu_shift") 3441 (const_string "alu_shift")
3442 (const_string "alu_shift_reg")))] 3442 (const_string "alu_shift_reg")))]
3443) 3443)
3444 3444
3445(define_insn "*arm_notsi_shiftsi_compare0" 3445(define_insn "*arm_notsi_shiftsi_compare0"
3446 [(set (reg:CC_NOOV CC_REGNUM) 3446 [(set (reg:CC_NOOV CC_REGNUM)
3447 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" 3447 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
3448 [(match_operand:SI 1 "s_register_operand" "r") 3448 [(match_operand:SI 1 "s_register_operand" "r")
3449 (match_operand:SI 2 "arm_rhs_operand" "rM")])) 3449 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
3450 (const_int 0))) 3450 (const_int 0)))
3451 (set (match_operand:SI 0 "s_register_operand" "=r") 3451 (set (match_operand:SI 0 "s_register_operand" "=r")
3452 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))] 3452 (not:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)])))]
3453 "TARGET_ARM" 3453 "TARGET_ARM"
3454 "mvn%.\\t%0, %1%S3" 3454 "mvn%.\\t%0, %1%S3"
3455 [(set_attr "conds" "set") 3455 [(set_attr "conds" "set")
3456 (set_attr "shift" "1") 3456 (set_attr "shift" "1")
3457 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") 3457 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3458 (const_string "alu_shift") 3458 (const_string "alu_shift")
3459 (const_string "alu_shift_reg")))] 3459 (const_string "alu_shift_reg")))]
3460) 3460)
3461 3461
3462(define_insn "*arm_not_shiftsi_compare0_scratch" 3462(define_insn "*arm_not_shiftsi_compare0_scratch"
3463 [(set (reg:CC_NOOV CC_REGNUM) 3463 [(set (reg:CC_NOOV CC_REGNUM)
3464 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator" 3464 (compare:CC_NOOV (not:SI (match_operator:SI 3 "shift_operator"
3465 [(match_operand:SI 1 "s_register_operand" "r") 3465 [(match_operand:SI 1 "s_register_operand" "r")
3466 (match_operand:SI 2 "arm_rhs_operand" "rM")])) 3466 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
3467 (const_int 0))) 3467 (const_int 0)))
3468 (clobber (match_scratch:SI 0 "=r"))] 3468 (clobber (match_scratch:SI 0 "=r"))]
3469 "TARGET_ARM" 3469 "TARGET_ARM"
3470 "mvn%.\\t%0, %1%S3" 3470 "mvn%.\\t%0, %1%S3"
3471 [(set_attr "conds" "set") 3471 [(set_attr "conds" "set")
3472 (set_attr "shift" "1") 3472 (set_attr "shift" "1")
3473 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") 3473 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
3474 (const_string "alu_shift") 3474 (const_string "alu_shift")
3475 (const_string "alu_shift_reg")))] 3475 (const_string "alu_shift_reg")))]
3476) 3476)
3477 3477
3478;; We don't really have extzv, but defining this using shifts helps 3478;; We don't really have extzv, but defining this using shifts helps
3479;; to reduce register pressure later on. 3479;; to reduce register pressure later on.
3480 3480
3481(define_expand "extzv" 3481(define_expand "extzv"
3482 [(set (match_dup 4) 3482 [(set (match_dup 4)
3483 (ashift:SI (match_operand:SI 1 "register_operand" "") 3483 (ashift:SI (match_operand:SI 1 "register_operand" "")
3484 (match_operand:SI 2 "const_int_operand" ""))) 3484 (match_operand:SI 2 "const_int_operand" "")))
3485 (set (match_operand:SI 0 "register_operand" "") 3485 (set (match_operand:SI 0 "register_operand" "")
3486 (lshiftrt:SI (match_dup 4) 3486 (lshiftrt:SI (match_dup 4)
3487 (match_operand:SI 3 "const_int_operand" "")))] 3487 (match_operand:SI 3 "const_int_operand" "")))]
3488 "TARGET_THUMB1 || arm_arch_thumb2" 3488 "TARGET_THUMB1 || arm_arch_thumb2"
3489 " 3489 "
3490 { 3490 {
3491 HOST_WIDE_INT lshift = 32 - INTVAL (operands[2]) - INTVAL (operands[3]); 3491 HOST_WIDE_INT lshift = 32 - INTVAL (operands[2]) - INTVAL (operands[3]);
3492 HOST_WIDE_INT rshift = 32 - INTVAL (operands[2]); 3492 HOST_WIDE_INT rshift = 32 - INTVAL (operands[2]);
3493  3493
3494 if (arm_arch_thumb2) 3494 if (arm_arch_thumb2)
3495 { 3495 {
3496 emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2], 3496 emit_insn (gen_extzv_t2 (operands[0], operands[1], operands[2],
3497 operands[3])); 3497 operands[3]));
3498 DONE; 3498 DONE;
3499 } 3499 }
3500 3500
3501 operands[3] = GEN_INT (rshift); 3501 operands[3] = GEN_INT (rshift);
3502  3502
3503 if (lshift == 0) 3503 if (lshift == 0)
3504 { 3504 {
3505 emit_insn (gen_lshrsi3 (operands[0], operands[1], operands[3])); 3505 emit_insn (gen_lshrsi3 (operands[0], operands[1], operands[3]));
3506 DONE; 3506 DONE;
3507 } 3507 }
3508  3508
3509 operands[2] = GEN_INT (lshift); 3509 operands[2] = GEN_INT (lshift);
3510 operands[4] = gen_reg_rtx (SImode); 3510 operands[4] = gen_reg_rtx (SImode);
3511 }" 3511 }"
3512) 3512)
3513 3513
3514(define_insn "extv" 3514(define_insn "extv"
3515 [(set (match_operand:SI 0 "s_register_operand" "=r") 3515 [(set (match_operand:SI 0 "s_register_operand" "=r")
3516 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r") 3516 (sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
3517 (match_operand:SI 2 "const_int_operand" "M") 3517 (match_operand:SI 2 "const_int_operand" "M")
3518 (match_operand:SI 3 "const_int_operand" "M")))] 3518 (match_operand:SI 3 "const_int_operand" "M")))]
3519 "arm_arch_thumb2" 3519 "arm_arch_thumb2"
3520 "sbfx%?\t%0, %1, %3, %2" 3520 "sbfx%?\t%0, %1, %3, %2"
3521 [(set_attr "length" "4") 3521 [(set_attr "length" "4")
3522 (set_attr "predicable" "yes")] 3522 (set_attr "predicable" "yes")]
3523) 3523)
3524 3524
3525(define_insn "extzv_t2" 3525(define_insn "extzv_t2"
3526 [(set (match_operand:SI 0 "s_register_operand" "=r") 3526 [(set (match_operand:SI 0 "s_register_operand" "=r")
3527 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r") 3527 (zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
3528 (match_operand:SI 2 "const_int_operand" "M") 3528 (match_operand:SI 2 "const_int_operand" "M")
3529 (match_operand:SI 3 "const_int_operand" "M")))] 3529 (match_operand:SI 3 "const_int_operand" "M")))]
3530 "arm_arch_thumb2" 3530 "arm_arch_thumb2"
3531 "ubfx%?\t%0, %1, %3, %2" 3531 "ubfx%?\t%0, %1, %3, %2"
3532 [(set_attr "length" "4") 3532 [(set_attr "length" "4")
3533 (set_attr "predicable" "yes")] 3533 (set_attr "predicable" "yes")]
3534) 3534)
3535 3535
3536  3536
3537;; Unary arithmetic insns 3537;; Unary arithmetic insns
3538 3538
3539(define_expand "negdi2" 3539(define_expand "negdi2"
3540 [(parallel 3540 [(parallel
3541 [(set (match_operand:DI 0 "s_register_operand" "") 3541 [(set (match_operand:DI 0 "s_register_operand" "")
3542 (neg:DI (match_operand:DI 1 "s_register_operand" ""))) 3542 (neg:DI (match_operand:DI 1 "s_register_operand" "")))
3543 (clobber (reg:CC CC_REGNUM))])] 3543 (clobber (reg:CC CC_REGNUM))])]
3544 "TARGET_EITHER" 3544 "TARGET_EITHER"
3545 " 3545 "
3546 if (TARGET_THUMB1) 3546 if (TARGET_THUMB1)
3547 { 3547 {
3548 if (GET_CODE (operands[1]) != REG) 3548 if (GET_CODE (operands[1]) != REG)
3549 operands[1] = force_reg (DImode, operands[1]); 3549 operands[1] = force_reg (DImode, operands[1]);
3550 } 3550 }
3551 " 3551 "
3552) 3552)
3553 3553
3554;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). 3554;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1).
3555;; The first alternative allows the common case of a *full* overlap. 3555;; The first alternative allows the common case of a *full* overlap.
3556(define_insn "*arm_negdi2" 3556(define_insn "*arm_negdi2"
3557 [(set (match_operand:DI 0 "s_register_operand" "=r,&r") 3557 [(set (match_operand:DI 0 "s_register_operand" "=r,&r")
3558 (neg:DI (match_operand:DI 1 "s_register_operand" "0,r"))) 3558 (neg:DI (match_operand:DI 1 "s_register_operand" "0,r")))
3559 (clobber (reg:CC CC_REGNUM))] 3559 (clobber (reg:CC CC_REGNUM))]
3560 "TARGET_ARM" 3560 "TARGET_ARM"
3561 "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" 3561 "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0"
3562 [(set_attr "conds" "clob") 3562 [(set_attr "conds" "clob")
3563 (set_attr "length" "8")] 3563 (set_attr "length" "8")]
3564) 3564)
3565 3565
3566(define_insn "*thumb1_negdi2" 3566(define_insn "*thumb1_negdi2"
3567 [(set (match_operand:DI 0 "register_operand" "=&l") 3567 [(set (match_operand:DI 0 "register_operand" "=&l")
3568 (neg:DI (match_operand:DI 1 "register_operand" "l"))) 3568 (neg:DI (match_operand:DI 1 "register_operand" "l")))
3569 (clobber (reg:CC CC_REGNUM))] 3569 (clobber (reg:CC CC_REGNUM))]
3570 "TARGET_THUMB1" 3570 "TARGET_THUMB1"
3571 "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1" 3571 "mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
3572 [(set_attr "length" "6")] 3572 [(set_attr "length" "6")]
3573) 3573)
3574 3574
3575(define_expand "negsi2" 3575(define_expand "negsi2"
3576 [(set (match_operand:SI 0 "s_register_operand" "") 3576 [(set (match_operand:SI 0 "s_register_operand" "")
3577 (neg:SI (match_operand:SI 1 "s_register_operand" "")))] 3577 (neg:SI (match_operand:SI 1 "s_register_operand" "")))]
3578 "TARGET_EITHER" 3578 "TARGET_EITHER"
3579 "" 3579 ""
3580) 3580)
3581 3581
3582(define_insn "*arm_negsi2" 3582(define_insn "*arm_negsi2"
3583 [(set (match_operand:SI 0 "s_register_operand" "=r") 3583 [(set (match_operand:SI 0 "s_register_operand" "=r")
3584 (neg:SI (match_operand:SI 1 "s_register_operand" "r")))] 3584 (neg:SI (match_operand:SI 1 "s_register_operand" "r")))]
3585 "TARGET_32BIT" 3585 "TARGET_32BIT"
3586 "rsb%?\\t%0, %1, #0" 3586 "rsb%?\\t%0, %1, #0"
3587 [(set_attr "predicable" "yes")] 3587 [(set_attr "predicable" "yes")]
3588) 3588)
3589 3589
3590(define_insn "*thumb1_negsi2" 3590(define_insn "*thumb1_negsi2"
3591 [(set (match_operand:SI 0 "register_operand" "=l") 3591 [(set (match_operand:SI 0 "register_operand" "=l")
3592 (neg:SI (match_operand:SI 1 "register_operand" "l")))] 3592 (neg:SI (match_operand:SI 1 "register_operand" "l")))]
3593 "TARGET_THUMB1" 3593 "TARGET_THUMB1"
3594 "neg\\t%0, %1" 3594 "neg\\t%0, %1"
3595 [(set_attr "length" "2")] 3595 [(set_attr "length" "2")]
3596) 3596)
3597 3597
3598(define_expand "negsf2" 3598(define_expand "negsf2"
3599 [(set (match_operand:SF 0 "s_register_operand" "") 3599 [(set (match_operand:SF 0 "s_register_operand" "")
3600 (neg:SF (match_operand:SF 1 "s_register_operand" "")))] 3600 (neg:SF (match_operand:SF 1 "s_register_operand" "")))]
3601 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" 3601 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
3602 "" 3602 ""
3603) 3603)
3604 3604
3605(define_expand "negdf2" 3605(define_expand "negdf2"
3606 [(set (match_operand:DF 0 "s_register_operand" "") 3606 [(set (match_operand:DF 0 "s_register_operand" "")
3607 (neg:DF (match_operand:DF 1 "s_register_operand" "")))] 3607 (neg:DF (match_operand:DF 1 "s_register_operand" "")))]
3608 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" 3608 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
3609 "") 3609 "")
3610 3610
3611;; abssi2 doesn't really clobber the condition codes if a different register 3611;; abssi2 doesn't really clobber the condition codes if a different register
3612;; is being set. To keep things simple, assume during rtl manipulations that 3612;; is being set. To keep things simple, assume during rtl manipulations that
3613;; it does, but tell the final scan operator the truth. Similarly for 3613;; it does, but tell the final scan operator the truth. Similarly for
3614;; (neg (abs...)) 3614;; (neg (abs...))
3615 3615
3616(define_expand "abssi2" 3616(define_expand "abssi2"
3617 [(parallel 3617 [(parallel
3618 [(set (match_operand:SI 0 "s_register_operand" "") 3618 [(set (match_operand:SI 0 "s_register_operand" "")
3619 (abs:SI (match_operand:SI 1 "s_register_operand" ""))) 3619 (abs:SI (match_operand:SI 1 "s_register_operand" "")))
3620 (clobber (match_dup 2))])] 3620 (clobber (match_dup 2))])]
3621 "TARGET_EITHER" 3621 "TARGET_EITHER"
3622 " 3622 "
3623 if (TARGET_THUMB1) 3623 if (TARGET_THUMB1)
3624 operands[2] = gen_rtx_SCRATCH (SImode); 3624 operands[2] = gen_rtx_SCRATCH (SImode);
3625 else 3625 else
3626 operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); 3626 operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
3627") 3627")
3628 3628
3629(define_insn "*arm_abssi2" 3629(define_insn "*arm_abssi2"
3630 [(set (match_operand:SI 0 "s_register_operand" "=r,&r") 3630 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
3631 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) 3631 (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
3632 (clobber (reg:CC CC_REGNUM))] 3632 (clobber (reg:CC CC_REGNUM))]
3633 "TARGET_ARM" 3633 "TARGET_ARM"
3634 "@ 3634 "@
3635 cmp\\t%0, #0\;rsblt\\t%0, %0, #0 3635 cmp\\t%0, #0\;rsblt\\t%0, %0, #0
3636 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31" 3636 eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
3637 [(set_attr "conds" "clob,*") 3637 [(set_attr "conds" "clob,*")
3638 (set_attr "shift" "1") 3638 (set_attr "shift" "1")
3639 ;; predicable can't be set based on the variant, so left as no 3639 ;; predicable can't be set based on the variant, so left as no
3640 (set_attr "length" "8")] 3640 (set_attr "length" "8")]
3641) 3641)
3642 3642
3643(define_insn_and_split "*thumb1_abssi2" 3643(define_insn_and_split "*thumb1_abssi2"
3644 [(set (match_operand:SI 0 "s_register_operand" "=l") 3644 [(set (match_operand:SI 0 "s_register_operand" "=l")
3645 (abs:SI (match_operand:SI 1 "s_register_operand" "l"))) 3645 (abs:SI (match_operand:SI 1 "s_register_operand" "l")))
3646 (clobber (match_scratch:SI 2 "=&l"))] 3646 (clobber (match_scratch:SI 2 "=&l"))]
3647 "TARGET_THUMB1" 3647 "TARGET_THUMB1"
3648 "#" 3648 "#"
3649 "TARGET_THUMB1 && reload_completed" 3649 "TARGET_THUMB1 && reload_completed"
3650 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 3650 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
3651 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2))) 3651 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
3652 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))] 3652 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
3653 "" 3653 ""
3654 [(set_attr "length" "6")] 3654 [(set_attr "length" "6")]
3655) 3655)
3656 3656
3657(define_insn "*arm_neg_abssi2" 3657(define_insn "*arm_neg_abssi2"
3658 [(set (match_operand:SI 0 "s_register_operand" "=r,&r") 3658 [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
3659 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))) 3659 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
3660 (clobber (reg:CC CC_REGNUM))] 3660 (clobber (reg:CC CC_REGNUM))]
3661 "TARGET_ARM" 3661 "TARGET_ARM"
3662 "@ 3662 "@
3663 cmp\\t%0, #0\;rsbgt\\t%0, %0, #0 3663 cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
3664 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31" 3664 eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
3665 [(set_attr "conds" "clob,*") 3665 [(set_attr "conds" "clob,*")
3666 (set_attr "shift" "1") 3666 (set_attr "shift" "1")
3667 ;; predicable can't be set based on the variant, so left as no 3667 ;; predicable can't be set based on the variant, so left as no
3668 (set_attr "length" "8")] 3668 (set_attr "length" "8")]
3669) 3669)
3670 3670
3671(define_insn_and_split "*thumb1_neg_abssi2" 3671(define_insn_and_split "*thumb1_neg_abssi2"
3672 [(set (match_operand:SI 0 "s_register_operand" "=l") 3672 [(set (match_operand:SI 0 "s_register_operand" "=l")
3673 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "l")))) 3673 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "l"))))
3674 (clobber (match_scratch:SI 2 "=&l"))] 3674 (clobber (match_scratch:SI 2 "=&l"))]
3675 "TARGET_THUMB1" 3675 "TARGET_THUMB1"
3676 "#" 3676 "#"
3677 "TARGET_THUMB1 && reload_completed" 3677 "TARGET_THUMB1 && reload_completed"
3678 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) 3678 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
3679 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1))) 3679 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))
3680 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))] 3680 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
3681 "" 3681 ""
3682 [(set_attr "length" "6")] 3682 [(set_attr "length" "6")]
3683) 3683)
3684 3684
3685(define_expand "abssf2" 3685(define_expand "abssf2"
3686 [(set (match_operand:SF 0 "s_register_operand" "") 3686 [(set (match_operand:SF 0 "s_register_operand" "")
3687 (abs:SF (match_operand:SF 1 "s_register_operand" "")))] 3687 (abs:SF (match_operand:SF 1 "s_register_operand" "")))]
3688 "TARGET_32BIT && TARGET_HARD_FLOAT" 3688 "TARGET_32BIT && TARGET_HARD_FLOAT"
3689 "") 3689 "")
3690 3690
3691(define_expand "absdf2" 3691(define_expand "absdf2"
3692 [(set (match_operand:DF 0 "s_register_operand" "") 3692 [(set (match_operand:DF 0 "s_register_operand" "")
3693 (abs:DF (match_operand:DF 1 "s_register_operand" "")))] 3693 (abs:DF (match_operand:DF 1 "s_register_operand" "")))]
3694 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" 3694 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
3695 "") 3695 "")
3696 3696
3697(define_expand "sqrtsf2" 3697(define_expand "sqrtsf2"
3698 [(set (match_operand:SF 0 "s_register_operand" "") 3698 [(set (match_operand:SF 0 "s_register_operand" "")
3699 (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))] 3699 (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))]
3700 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)" 3700 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
3701 "") 3701 "")
3702 3702
3703(define_expand "sqrtdf2" 3703(define_expand "sqrtdf2"
3704 [(set (match_operand:DF 0 "s_register_operand" "") 3704 [(set (match_operand:DF 0 "s_register_operand" "")
3705 (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))] 3705 (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
3706 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" 3706 "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
3707 "") 3707 "")
3708 3708
3709(define_insn_and_split "one_cmpldi2" 3709(define_insn_and_split "one_cmpldi2"
3710 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") 3710 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
3711 (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))] 3711 (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))]
3712 "TARGET_32BIT" 3712 "TARGET_32BIT"
3713 "#" 3713 "#"
3714 "TARGET_32BIT && reload_completed" 3714 "TARGET_32BIT && reload_completed"
3715 [(set (match_dup 0) (not:SI (match_dup 1))) 3715 [(set (match_dup 0) (not:SI (match_dup 1)))
3716 (set (match_dup 2) (not:SI (match_dup 3)))] 3716 (set (match_dup 2) (not:SI (match_dup 3)))]
3717 " 3717 "
3718 { 3718 {
3719 operands[2] = gen_highpart (SImode, operands[0]); 3719 operands[2] = gen_highpart (SImode, operands[0]);
3720 operands[0] = gen_lowpart (SImode, operands[0]); 3720 operands[0] = gen_lowpart (SImode, operands[0]);
3721 operands[3] = gen_highpart (SImode, operands[1]); 3721 operands[3] = gen_highpart (SImode, operands[1]);
3722 operands[1] = gen_lowpart (SImode, operands[1]); 3722 operands[1] = gen_lowpart (SImode, operands[1]);
3723 }" 3723 }"
3724 [(set_attr "length" "8") 3724 [(set_attr "length" "8")
3725 (set_attr "predicable" "yes")] 3725 (set_attr "predicable" "yes")]
3726) 3726)
3727 3727
3728(define_expand "one_cmplsi2" 3728(define_expand "one_cmplsi2"
3729 [(set (match_operand:SI 0 "s_register_operand" "") 3729 [(set (match_operand:SI 0 "s_register_operand" "")
3730 (not:SI (match_operand:SI 1 "s_register_operand" "")))] 3730 (not:SI (match_operand:SI 1 "s_register_operand" "")))]
3731 "TARGET_EITHER" 3731 "TARGET_EITHER"
3732 "" 3732 ""
3733) 3733)
3734 3734
3735(define_insn "*arm_one_cmplsi2" 3735(define_insn "*arm_one_cmplsi2"
3736 [(set (match_operand:SI 0 "s_register_operand" "=r") 3736 [(set (match_operand:SI 0 "s_register_operand" "=r")
3737 (not:SI (match_operand:SI 1 "s_register_operand" "r")))] 3737 (not:SI (match_operand:SI 1 "s_register_operand" "r")))]
3738 "TARGET_32BIT" 3738 "TARGET_32BIT"
3739 "mvn%?\\t%0, %1" 3739 "mvn%?\\t%0, %1"
3740 [(set_attr "predicable" "yes")] 3740 [(set_attr "predicable" "yes")]
3741) 3741)
3742 3742
3743(define_insn "*thumb1_one_cmplsi2" 3743(define_insn "*thumb1_one_cmplsi2"
3744 [(set (match_operand:SI 0 "register_operand" "=l") 3744 [(set (match_operand:SI 0 "register_operand" "=l")
3745 (not:SI (match_operand:SI 1 "register_operand" "l")))] 3745 (not:SI (match_operand:SI 1 "register_operand" "l")))]
3746 "TARGET_THUMB1" 3746 "TARGET_THUMB1"
3747 "mvn\\t%0, %1" 3747 "mvn\\t%0, %1"
3748 [(set_attr "length" "2")] 3748 [(set_attr "length" "2")]
3749) 3749)
3750 3750
3751(define_insn "*notsi_compare0" 3751(define_insn "*notsi_compare0"
3752 [(set (reg:CC_NOOV CC_REGNUM) 3752 [(set (reg:CC_NOOV CC_REGNUM)
3753 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) 3753 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
3754 (const_int 0))) 3754 (const_int 0)))
3755 (set (match_operand:SI 0 "s_register_operand" "=r") 3755 (set (match_operand:SI 0 "s_register_operand" "=r")
3756 (not:SI (match_dup 1)))] 3756 (not:SI (match_dup 1)))]
3757 "TARGET_32BIT" 3757 "TARGET_32BIT"
3758 "mvn%.\\t%0, %1" 3758 "mvn%.\\t%0, %1"
3759 [(set_attr "conds" "set")] 3759 [(set_attr "conds" "set")]
3760) 3760)
3761 3761
3762(define_insn "*notsi_compare0_scratch" 3762(define_insn "*notsi_compare0_scratch"
3763 [(set (reg:CC_NOOV CC_REGNUM) 3763 [(set (reg:CC_NOOV CC_REGNUM)
3764 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) 3764 (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r"))
3765 (const_int 0))) 3765 (const_int 0)))
3766 (clobber (match_scratch:SI 0 "=r"))] 3766 (clobber (match_scratch:SI 0 "=r"))]
3767 "TARGET_32BIT" 3767 "TARGET_32BIT"
3768 "mvn%.\\t%0, %1" 3768 "mvn%.\\t%0, %1"
3769 [(set_attr "conds" "set")] 3769 [(set_attr "conds" "set")]
3770) 3770)
3771  3771
3772;; Fixed <--> Floating conversion insns 3772;; Fixed <--> Floating conversion insns
3773 3773
3774(define_expand "floatsihf2" 3774(define_expand "floatsihf2"
3775 [(set (match_operand:HF 0 "general_operand" "") 3775 [(set (match_operand:HF 0 "general_operand" "")
3776 (float:HF (match_operand:SI 1 "general_operand" "")))] 3776 (float:HF (match_operand:SI 1 "general_operand" "")))]
3777 "TARGET_EITHER" 3777 "TARGET_EITHER"
3778 " 3778 "
3779 { 3779 {
3780 rtx op1 = gen_reg_rtx (SFmode); 3780 rtx op1 = gen_reg_rtx (SFmode);
3781 expand_float (op1, operands[1], 0); 3781 expand_float (op1, operands[1], 0);
3782 op1 = convert_to_mode (HFmode, op1, 0); 3782 op1 = convert_to_mode (HFmode, op1, 0);
3783 emit_move_insn (operands[0], op1); 3783 emit_move_insn (operands[0], op1);
3784 DONE; 3784 DONE;
3785 }" 3785 }"
3786) 3786)
3787 3787
3788(define_expand "floatdihf2" 3788(define_expand "floatdihf2"
3789 [(set (match_operand:HF 0 "general_operand" "") 3789 [(set (match_operand:HF 0 "general_operand" "")
3790 (float:HF (match_operand:DI 1 "general_operand" "")))] 3790 (float:HF (match_operand:DI 1 "general_operand" "")))]
3791 "TARGET_EITHER" 3791 "TARGET_EITHER"
3792 " 3792 "
3793 { 3793 {
3794 rtx op1 = gen_reg_rtx (SFmode); 3794 rtx op1 = gen_reg_rtx (SFmode);
3795 expand_float (op1, operands[1], 0); 3795 expand_float (op1, operands[1], 0);
3796 op1 = convert_to_mode (HFmode, op1, 0); 3796 op1 = convert_to_mode (HFmode, op1, 0);
3797 emit_move_insn (operands[0], op1); 3797 emit_move_insn (operands[0], op1);
3798 DONE; 3798 DONE;
3799 }" 3799 }"
3800) 3800)
3801 3801
3802(define_expand "floatsisf2" 3802(define_expand "floatsisf2"
3803 [(set (match_operand:SF 0 "s_register_operand" "") 3803 [(set (match_operand:SF 0 "s_register_operand" "")
3804 (float:SF (match_operand:SI 1 "s_register_operand" "")))] 3804 (float:SF (match_operand:SI 1 "s_register_operand" "")))]
3805 "TARGET_32BIT && TARGET_HARD_FLOAT" 3805 "TARGET_32BIT && TARGET_HARD_FLOAT"
3806 " 3806 "
3807 if (TARGET_MAVERICK) 3807 if (TARGET_MAVERICK)
3808 { 3808 {
3809 emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); 3809 emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1]));
3810 DONE; 3810 DONE;
3811 } 3811 }
3812") 3812")
3813 3813
3814(define_expand "floatsidf2" 3814(define_expand "floatsidf2"
3815 [(set (match_operand:DF 0 "s_register_operand" "") 3815 [(set (match_operand:DF 0 "s_register_operand" "")
3816 (float:DF (match_operand:SI 1 "s_register_operand" "")))] 3816 (float:DF (match_operand:SI 1 "s_register_operand" "")))]
3817 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" 3817 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
3818 " 3818 "
3819 if (TARGET_MAVERICK) 3819 if (TARGET_MAVERICK)
3820 { 3820 {
3821 emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); 3821 emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1]));
3822 DONE; 3822 DONE;
3823 } 3823 }
3824") 3824")
3825 3825
3826(define_expand "fix_trunchfsi2" 3826(define_expand "fix_trunchfsi2"
3827 [(set (match_operand:SI 0 "general_operand" "") 3827 [(set (match_operand:SI 0 "general_operand" "")
3828 (fix:SI (fix:HF (match_operand:HF 1 "general_operand" ""))))] 3828 (fix:SI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
3829 "TARGET_EITHER" 3829 "TARGET_EITHER"
3830 " 3830 "
3831 { 3831 {
3832 rtx op1 = convert_to_mode (SFmode, operands[1], 0); 3832 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
3833 expand_fix (operands[0], op1, 0); 3833 expand_fix (operands[0], op1, 0);
3834 DONE; 3834 DONE;
3835 }" 3835 }"
3836) 3836)
3837 3837
3838(define_expand "fix_trunchfdi2" 3838(define_expand "fix_trunchfdi2"
3839 [(set (match_operand:DI 0 "general_operand" "") 3839 [(set (match_operand:DI 0 "general_operand" "")
3840 (fix:DI (fix:HF (match_operand:HF 1 "general_operand" ""))))] 3840 (fix:DI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
3841 "TARGET_EITHER" 3841 "TARGET_EITHER"
3842 " 3842 "
3843 { 3843 {
3844 rtx op1 = convert_to_mode (SFmode, operands[1], 0); 3844 rtx op1 = convert_to_mode (SFmode, operands[1], 0);
3845 expand_fix (operands[0], op1, 0); 3845 expand_fix (operands[0], op1, 0);
3846 DONE; 3846 DONE;
3847 }" 3847 }"
3848) 3848)
3849 3849
3850(define_expand "fix_truncsfsi2" 3850(define_expand "fix_truncsfsi2"
3851 [(set (match_operand:SI 0 "s_register_operand" "") 3851 [(set (match_operand:SI 0 "s_register_operand" "")
3852 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] 3852 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
3853 "TARGET_32BIT && TARGET_HARD_FLOAT" 3853 "TARGET_32BIT && TARGET_HARD_FLOAT"
3854 " 3854 "
3855 if (TARGET_MAVERICK) 3855 if (TARGET_MAVERICK)
3856 { 3856 {
3857 if (!cirrus_fp_register (operands[0], SImode)) 3857 if (!cirrus_fp_register (operands[0], SImode))
3858 operands[0] = force_reg (SImode, operands[0]); 3858 operands[0] = force_reg (SImode, operands[0]);
3859 if (!cirrus_fp_register (operands[1], SFmode)) 3859 if (!cirrus_fp_register (operands[1], SFmode))
3860 operands[1] = force_reg (SFmode, operands[0]); 3860 operands[1] = force_reg (SFmode, operands[0]);
3861 emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1])); 3861 emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1]));
3862 DONE; 3862 DONE;
3863 } 3863 }
3864") 3864")
3865 3865
3866(define_expand "fix_truncdfsi2" 3866(define_expand "fix_truncdfsi2"
3867 [(set (match_operand:SI 0 "s_register_operand" "") 3867 [(set (match_operand:SI 0 "s_register_operand" "")
3868 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] 3868 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
3869 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" 3869 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
3870 " 3870 "
3871 if (TARGET_MAVERICK) 3871 if (TARGET_MAVERICK)
3872 { 3872 {
3873 if (!cirrus_fp_register (operands[1], DFmode)) 3873 if (!cirrus_fp_register (operands[1], DFmode))
3874 operands[1] = force_reg (DFmode, operands[0]); 3874 operands[1] = force_reg (DFmode, operands[0]);
3875 emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1])); 3875 emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1]));
3876 DONE; 3876 DONE;
3877 } 3877 }
3878") 3878")
3879 3879
3880;; Truncation insns 3880;; Truncation insns
3881 3881
3882(define_expand "truncdfsf2" 3882(define_expand "truncdfsf2"
3883 [(set (match_operand:SF 0 "s_register_operand" "") 3883 [(set (match_operand:SF 0 "s_register_operand" "")
3884 (float_truncate:SF 3884 (float_truncate:SF
3885 (match_operand:DF 1 "s_register_operand" "")))] 3885 (match_operand:DF 1 "s_register_operand" "")))]
3886 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" 3886 "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
3887 "" 3887 ""
3888) 3888)
3889 3889
3890/* DFmode -> HFmode conversions have to go through SFmode. */ 3890/* DFmode -> HFmode conversions have to go through SFmode. */
3891(define_expand "truncdfhf2" 3891(define_expand "truncdfhf2"
3892 [(set (match_operand:HF 0 "general_operand" "") 3892 [(set (match_operand:HF 0 "general_operand" "")
3893 (float_truncate:HF 3893 (float_truncate:HF
3894 (match_operand:DF 1 "general_operand" "")))] 3894 (match_operand:DF 1 "general_operand" "")))]
3895 "TARGET_EITHER" 3895 "TARGET_EITHER"
3896 " 3896 "
3897 { 3897 {
3898 rtx op1; 3898 rtx op1;
3899 op1 = convert_to_mode (SFmode, operands[1], 0); 3899 op1 = convert_to_mode (SFmode, operands[1], 0);
3900 op1 = convert_to_mode (HFmode, op1, 0); 3900 op1 = convert_to_mode (HFmode, op1, 0);
3901 emit_move_insn (operands[0], op1); 3901 emit_move_insn (operands[0], op1);
3902 DONE; 3902 DONE;
3903 }" 3903 }"
3904) 3904)
3905  3905
3906;; Zero and sign extension instructions. 3906;; Zero and sign extension instructions.
3907 3907
3908(define_expand "zero_extendsidi2" 3908(define_expand "zero_extendsidi2"
3909 [(set (match_operand:DI 0 "s_register_operand" "") 3909 [(set (match_operand:DI 0 "s_register_operand" "")
3910 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))] 3910 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
3911 "TARGET_32BIT" 3911 "TARGET_32BIT"
3912 "" 3912 ""
3913) 3913)
3914 3914
3915(define_insn "*arm_zero_extendsidi2" 3915(define_insn "*arm_zero_extendsidi2"
3916 [(set (match_operand:DI 0 "s_register_operand" "=r") 3916 [(set (match_operand:DI 0 "s_register_operand" "=r")
3917 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] 3917 (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
3918 "TARGET_ARM" 3918 "TARGET_ARM"
3919 "* 3919 "*
3920 if (REGNO (operands[1]) 3920 if (REGNO (operands[1])
3921 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) 3921 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
3922 output_asm_insn (\"mov%?\\t%Q0, %1\", operands); 3922 output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
3923 return \"mov%?\\t%R0, #0\"; 3923 return \"mov%?\\t%R0, #0\";
3924 " 3924 "
3925 [(set_attr "length" "8") 3925 [(set_attr "length" "8")
3926 (set_attr "predicable" "yes")] 3926 (set_attr "predicable" "yes")]
3927) 3927)
3928 3928
3929(define_expand "zero_extendqidi2" 3929(define_expand "zero_extendqidi2"
3930 [(set (match_operand:DI 0 "s_register_operand" "") 3930 [(set (match_operand:DI 0 "s_register_operand" "")
3931 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))] 3931 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
3932 "TARGET_32BIT" 3932 "TARGET_32BIT"
3933 "" 3933 ""
3934) 3934)
3935 3935
3936(define_insn "*arm_zero_extendqidi2" 3936(define_insn "*arm_zero_extendqidi2"
3937 [(set (match_operand:DI 0 "s_register_operand" "=r,r") 3937 [(set (match_operand:DI 0 "s_register_operand" "=r,r")
3938 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] 3938 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
3939 "TARGET_ARM" 3939 "TARGET_ARM"
3940 "@ 3940 "@
3941 and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0 3941 and%?\\t%Q0, %1, #255\;mov%?\\t%R0, #0
3942 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0" 3942 ldr%(b%)\\t%Q0, %1\;mov%?\\t%R0, #0"
3943 [(set_attr "length" "8") 3943 [(set_attr "length" "8")
3944 (set_attr "predicable" "yes") 3944 (set_attr "predicable" "yes")
3945 (set_attr "type" "*,load_byte") 3945 (set_attr "type" "*,load_byte")
3946 (set_attr "pool_range" "*,4092") 3946 (set_attr "pool_range" "*,4092")
3947 (set_attr "neg_pool_range" "*,4084")] 3947 (set_attr "neg_pool_range" "*,4084")]
3948) 3948)
3949 3949
3950(define_expand "extendsidi2" 3950(define_expand "extendsidi2"
3951 [(set (match_operand:DI 0 "s_register_operand" "") 3951 [(set (match_operand:DI 0 "s_register_operand" "")
3952 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))] 3952 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))]
3953 "TARGET_32BIT" 3953 "TARGET_32BIT"
3954 "" 3954 ""
3955) 3955)
3956 3956
3957(define_insn "*arm_extendsidi2" 3957(define_insn "*arm_extendsidi2"
3958 [(set (match_operand:DI 0 "s_register_operand" "=r") 3958 [(set (match_operand:DI 0 "s_register_operand" "=r")
3959 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))] 3959 (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))]
3960 "TARGET_ARM" 3960 "TARGET_ARM"
3961 "* 3961 "*
3962 if (REGNO (operands[1]) 3962 if (REGNO (operands[1])
3963 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0)) 3963 != REGNO (operands[0]) + (WORDS_BIG_ENDIAN ? 1 : 0))
3964 output_asm_insn (\"mov%?\\t%Q0, %1\", operands); 3964 output_asm_insn (\"mov%?\\t%Q0, %1\", operands);
3965 return \"mov%?\\t%R0, %Q0, asr #31\"; 3965 return \"mov%?\\t%R0, %Q0, asr #31\";
3966 " 3966 "
3967 [(set_attr "length" "8") 3967 [(set_attr "length" "8")
3968 (set_attr "shift" "1") 3968 (set_attr "shift" "1")
3969 (set_attr "predicable" "yes")] 3969 (set_attr "predicable" "yes")]
3970) 3970)
3971 3971
3972(define_expand "zero_extendhisi2" 3972(define_expand "zero_extendhisi2"
3973 [(set (match_dup 2) 3973 [(set (match_dup 2)
3974 (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "") 3974 (ashift:SI (match_operand:HI 1 "nonimmediate_operand" "")
3975 (const_int 16))) 3975 (const_int 16)))
3976 (set (match_operand:SI 0 "s_register_operand" "") 3976 (set (match_operand:SI 0 "s_register_operand" "")
3977 (lshiftrt:SI (match_dup 2) (const_int 16)))] 3977 (lshiftrt:SI (match_dup 2) (const_int 16)))]
3978 "TARGET_EITHER" 3978 "TARGET_EITHER"
3979 " 3979 "
3980 { 3980 {
3981 if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM) 3981 if ((TARGET_THUMB1 || arm_arch4) && GET_CODE (operands[1]) == MEM)
3982 { 3982 {
3983 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 3983 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3984 gen_rtx_ZERO_EXTEND (SImode, operands[1]))); 3984 gen_rtx_ZERO_EXTEND (SImode, operands[1])));
3985 DONE; 3985 DONE;
3986 } 3986 }
3987 3987
3988 if (TARGET_ARM && GET_CODE (operands[1]) == MEM) 3988 if (TARGET_ARM && GET_CODE (operands[1]) == MEM)
3989 { 3989 {
3990 emit_insn (gen_movhi_bytes (operands[0], operands[1])); 3990 emit_insn (gen_movhi_bytes (operands[0], operands[1]));
3991 DONE; 3991 DONE;
3992 } 3992 }
3993 3993
3994 if (!s_register_operand (operands[1], HImode)) 3994 if (!s_register_operand (operands[1], HImode))
3995 operands[1] = copy_to_mode_reg (HImode, operands[1]); 3995 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3996 3996
3997 if (arm_arch6) 3997 if (arm_arch6)
3998 { 3998 {
3999 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 3999 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4000 gen_rtx_ZERO_EXTEND (SImode, operands[1]))); 4000 gen_rtx_ZERO_EXTEND (SImode, operands[1])));
4001 DONE; 4001 DONE;
4002 } 4002 }
4003 4003
4004 operands[1] = gen_lowpart (SImode, operands[1]); 4004 operands[1] = gen_lowpart (SImode, operands[1]);
4005 operands[2] = gen_reg_rtx (SImode); 4005 operands[2] = gen_reg_rtx (SImode);
4006 }" 4006 }"
4007) 4007)
4008 4008
4009(define_insn "*thumb1_zero_extendhisi2" 4009(define_insn "*thumb1_zero_extendhisi2"
4010 [(set (match_operand:SI 0 "register_operand" "=l") 4010 [(set (match_operand:SI 0 "register_operand" "=l")
4011 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 4011 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4012 "TARGET_THUMB1 && !arm_arch6" 4012 "TARGET_THUMB1 && !arm_arch6"
4013 "* 4013 "*
4014 rtx mem = XEXP (operands[1], 0); 4014 rtx mem = XEXP (operands[1], 0);
4015 4015
4016 if (GET_CODE (mem) == CONST) 4016 if (GET_CODE (mem) == CONST)
4017 mem = XEXP (mem, 0); 4017 mem = XEXP (mem, 0);
4018  4018
4019 if (GET_CODE (mem) == LABEL_REF) 4019 if (GET_CODE (mem) == LABEL_REF)
4020 return \"ldr\\t%0, %1\"; 4020 return \"ldr\\t%0, %1\";
4021  4021
4022 if (GET_CODE (mem) == PLUS) 4022 if (GET_CODE (mem) == PLUS)
4023 { 4023 {
4024 rtx a = XEXP (mem, 0); 4024 rtx a = XEXP (mem, 0);
4025 rtx b = XEXP (mem, 1); 4025 rtx b = XEXP (mem, 1);
4026 4026
4027 /* This can happen due to bugs in reload. */ 4027 /* This can happen due to bugs in reload. */
4028 if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) 4028 if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
4029 { 4029 {
4030 rtx ops[2]; 4030 rtx ops[2];
4031 ops[0] = operands[0]; 4031 ops[0] = operands[0];
4032 ops[1] = a; 4032 ops[1] = a;
4033  4033
4034 output_asm_insn (\"mov %0, %1\", ops); 4034 output_asm_insn (\"mov %0, %1\", ops);
4035 4035
4036 XEXP (mem, 0) = operands[0]; 4036 XEXP (mem, 0) = operands[0];
4037 } 4037 }
4038 4038
4039 else if ( GET_CODE (a) == LABEL_REF 4039 else if ( GET_CODE (a) == LABEL_REF
4040 && GET_CODE (b) == CONST_INT) 4040 && GET_CODE (b) == CONST_INT)
4041 return \"ldr\\t%0, %1\"; 4041 return \"ldr\\t%0, %1\";
4042 } 4042 }
4043  4043
4044 return \"ldrh\\t%0, %1\"; 4044 return \"ldrh\\t%0, %1\";
4045 " 4045 "
4046 [(set_attr "length" "4") 4046 [(set_attr "length" "4")
4047 (set_attr "type" "load_byte") 4047 (set_attr "type" "load_byte")
4048 (set_attr "pool_range" "60")] 4048 (set_attr "pool_range" "60")]
4049) 4049)
4050 4050
4051(define_insn "*thumb1_zero_extendhisi2_v6" 4051(define_insn "*thumb1_zero_extendhisi2_v6"
4052 [(set (match_operand:SI 0 "register_operand" "=l,l") 4052 [(set (match_operand:SI 0 "register_operand" "=l,l")
4053 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))] 4053 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "l,m")))]
4054 "TARGET_THUMB1 && arm_arch6" 4054 "TARGET_THUMB1 && arm_arch6"
4055 "* 4055 "*
4056 rtx mem; 4056 rtx mem;
4057 4057
4058 if (which_alternative == 0) 4058 if (which_alternative == 0)
4059 return \"uxth\\t%0, %1\"; 4059 return \"uxth\\t%0, %1\";
4060 4060
4061 mem = XEXP (operands[1], 0); 4061 mem = XEXP (operands[1], 0);
4062 4062
4063 if (GET_CODE (mem) == CONST) 4063 if (GET_CODE (mem) == CONST)
4064 mem = XEXP (mem, 0); 4064 mem = XEXP (mem, 0);
4065  4065
4066 if (GET_CODE (mem) == LABEL_REF) 4066 if (GET_CODE (mem) == LABEL_REF)
4067 return \"ldr\\t%0, %1\"; 4067 return \"ldr\\t%0, %1\";
4068  4068
4069 if (GET_CODE (mem) == PLUS) 4069 if (GET_CODE (mem) == PLUS)
4070 { 4070 {
4071 rtx a = XEXP (mem, 0); 4071 rtx a = XEXP (mem, 0);
4072 rtx b = XEXP (mem, 1); 4072 rtx b = XEXP (mem, 1);
4073 4073
4074 /* This can happen due to bugs in reload. */ 4074 /* This can happen due to bugs in reload. */
4075 if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM) 4075 if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
4076 { 4076 {
4077 rtx ops[2]; 4077 rtx ops[2];
4078 ops[0] = operands[0]; 4078 ops[0] = operands[0];
4079 ops[1] = a; 4079 ops[1] = a;
4080  4080
4081 output_asm_insn (\"mov %0, %1\", ops); 4081 output_asm_insn (\"mov %0, %1\", ops);
4082 4082
4083 XEXP (mem, 0) = operands[0]; 4083 XEXP (mem, 0) = operands[0];
4084 } 4084 }
4085 4085
4086 else if ( GET_CODE (a) == LABEL_REF 4086 else if ( GET_CODE (a) == LABEL_REF
4087 && GET_CODE (b) == CONST_INT) 4087 && GET_CODE (b) == CONST_INT)
4088 return \"ldr\\t%0, %1\"; 4088 return \"ldr\\t%0, %1\";
4089 } 4089 }
4090  4090
4091 return \"ldrh\\t%0, %1\"; 4091 return \"ldrh\\t%0, %1\";
4092 " 4092 "
4093 [(set_attr "length" "2,4") 4093 [(set_attr "length" "2,4")
4094 (set_attr "type" "alu_shift,load_byte") 4094 (set_attr "type" "alu_shift,load_byte")
4095 (set_attr "pool_range" "*,60")] 4095 (set_attr "pool_range" "*,60")]
4096) 4096)
4097 4097
4098(define_insn "*arm_zero_extendhisi2" 4098(define_insn "*arm_zero_extendhisi2"
4099 [(set (match_operand:SI 0 "s_register_operand" "=r") 4099 [(set (match_operand:SI 0 "s_register_operand" "=r")
4100 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 4100 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
4101 "TARGET_ARM && arm_arch4 && !arm_arch6" 4101 "TARGET_ARM && arm_arch4 && !arm_arch6"
4102 "ldr%(h%)\\t%0, %1" 4102 "ldr%(h%)\\t%0, %1"
4103 [(set_attr "type" "load_byte") 4103 [(set_attr "type" "load_byte")
4104 (set_attr "predicable" "yes") 4104 (set_attr "predicable" "yes")
4105 (set_attr "pool_range" "256") 4105 (set_attr "pool_range" "256")
4106 (set_attr "neg_pool_range" "244")] 4106 (set_attr "neg_pool_range" "244")]
4107) 4107)
4108 4108
4109(define_insn "*arm_zero_extendhisi2_v6" 4109(define_insn "*arm_zero_extendhisi2_v6"
4110 [(set (match_operand:SI 0 "s_register_operand" "=r,r") 4110 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
4111 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 4111 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
4112 "TARGET_ARM && arm_arch6" 4112 "TARGET_ARM && arm_arch6"
4113 "@ 4113 "@
4114 uxth%?\\t%0, %1 4114 uxth%?\\t%0, %1
4115 ldr%(h%)\\t%0, %1" 4115 ldr%(h%)\\t%0, %1"
4116 [(set_attr "type" "alu_shift,load_byte") 4116 [(set_attr "type" "alu_shift,load_byte")
4117 (set_attr "predicable" "yes") 4117 (set_attr "predicable" "yes")
4118 (set_attr "pool_range" "*,256") 4118 (set_attr "pool_range" "*,256")
4119 (set_attr "neg_pool_range" "*,244")] 4119 (set_attr "neg_pool_range" "*,244")]
4120) 4120)
4121 4121
4122(define_insn "*arm_zero_extendhisi2addsi" 4122(define_insn "*arm_zero_extendhisi2addsi"
4123 [(set (match_operand:SI 0 "s_register_operand" "=r") 4123 [(set (match_operand:SI 0 "s_register_operand" "=r")
4124 (plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r")) 4124 (plus:SI (zero_extend:SI (match_operand:HI 1 "s_register_operand" "r"))
4125 (match_operand:SI 2 "s_register_operand" "r")))] 4125 (match_operand:SI 2 "s_register_operand" "r")))]
4126 "TARGET_INT_SIMD" 4126 "TARGET_INT_SIMD"
4127 "uxtah%?\\t%0, %2, %1" 4127 "uxtah%?\\t%0, %2, %1"
4128 [(set_attr "type" "alu_shift") 4128 [(set_attr "type" "alu_shift")
4129 (set_attr "predicable" "yes")] 4129 (set_attr "predicable" "yes")]
4130) 4130)
4131 4131
4132(define_expand "zero_extendqisi2" 4132(define_expand "zero_extendqisi2"
4133 [(set (match_operand:SI 0 "s_register_operand" "") 4133 [(set (match_operand:SI 0 "s_register_operand" "")
4134 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 4134 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
4135 "TARGET_EITHER" 4135 "TARGET_EITHER"
4136 " 4136 "