 @@ -1,14 +1,14 @@
-/*	$NetBSD: rpi_start.S,v 1.5 2012/08/22 12:36:35 jakllsch Exp $	*/
+/*	$NetBSD: rpi_start.S,v 1.6 2012/09/16 14:14:56 skrll Exp $	*/
 /*
  * Copyright (c) 2002, 2003  Genetec Corporation.  All rights reserved.
  * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -77,31 +77,27 @@
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 #include "opt_cputypes.h"
 #include <machine/asm.h>
 #include <arm/armreg.h>
 #include "assym.h"
-RCSID("$NetBSD: rpi_start.S,v 1.5 2012/08/22 12:36:35 jakllsch Exp $")
+RCSID("$NetBSD: rpi_start.S,v 1.6 2012/09/16 14:14:56 skrll Exp $")
 /* Location (in MiB) to put temporary MMU tables just below. */
 /* Raspberry Pi start.elf will give us anywhere between 128MiB and 240MiB */
 #define MINSPLIT 128
 /*
  * Workaround Erratum 411920
+ *
  *	- value of arg 'reg' Should Be Zero
  */
 #define Invalidate_I_cache(reg) \
 	.p2align 5;								\
 	mcr	p15, 0, reg, c7, c5, 0;	/* Invalidate Entire I cache */		\
 	mcr	p15, 0, reg, c7, c5, 0;	/* Invalidate Entire I cache */		\
 	mcr	p15, 0, reg, c7, c5, 0;	/* Invalidate Entire I cache */		\
 	mcr	p15, 0, reg, c7, c5, 0;	/* Invalidate Entire I cache */		\
 	nop;									\
 @@ -167,26 +163,27 @@ _C_LABEL(rpi_start):
 	l1sfrm	.req r6
 	adr	itable, mmu_init_table
 	ldr	l1sfrm, Ll1_s_frame
 	b	3f
 :	str	pa, [l1table, va]
 	add	va, va, #4
 	add	pa, pa, #(L1_S_SIZE)
 	adds	n_sec, n_sec, #-1
 	bhi	2b
 :	ldmia	itable!, {va,pa,n_sec,attr}
 	mov	n_sec, n_sec, lsr #L1_S_SHIFT
 	/* Convert va to l1 offset:	va = 4 * (va >> L1_S_SHIFT)	*/
 	mov	va, va, LSR #L1_S_SHIFT
 	mov	va, va, LSL #2
 	/* Convert pa to l1 entry:	pa = (pa & L1_S_FRAME) | attr	*/
 	and	pa, pa, l1sfrm
 	orr	pa, pa, attr
 	cmp	n_sec, #0
 	bne	2b
 	.unreq	va
 	.unreq	pa
 	.unreq	n_sec
 	.unreq	attr
 @@ -249,28 +246,28 @@ _C_LABEL(rpi_start):
 	 * Jump to start in locore.S, which in turn will call initarm and main.
 	 */
 	mov	pc, lr
 	nop
 	nop
 	nop
 	nop
 	/* NOTREACHED */
 Ll1_s_frame:
 	.word	L1_S_FRAME
 Ltemp_l1_table:
-	/* Put the temporary L1 translation table at the end of SDRAM. */
+	/* Put the temporary L1 translation table just below the kernel. */
-	.word	0x00000000 + MINSPLIT * 0x100000 - L1_TABLE_SIZE
+	.word	0x4000
 Lstart:
 	.word	start
 /*
  * Coprocessor register initialization values
  */
 	/* bits to set in the Control Register */
 Lcontrol_set:
 	.word CPU_CONTROL_MMU_ENABLE  | \
 	      CPU_CONTROL_AFLT_ENABLE | \
 	      CPU_CONTROL_DC_ENABLE   | \
 	      CPU_CONTROL_WBUF_ENABLE |    /* not defined in 1176 */   \
 @@ -300,32 +297,32 @@ Lcontrol_wax:
 	/* bits to disable the caches */
 Lctl_ID_dis:
 	.word	~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
 /* We'll modify va and pa at run time so we can use relocatable addresses. */
 #define MMU_INIT(va,pa,n_sec,attr) \
 	.word	va					    ; \
 	.word	pa					    ; \
 	.word	n_sec					    ; \
 	.word	attr					    ;
 mmu_init_table:
 	/* Add 1MB of VA==PA at 0x00000000 so we can keep the kernel going */
-	MMU_INIT(0x00000000, 0x00000000,
+	MMU_INIT(0x0, 0x0,
-	    (MINSPLIT * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+	    (_end - KERNEL_BASE + L1_S_SIZE - 1),
 	    L1_S_PROTO | L1_S_AP_KRW)
 	MMU_INIT(KERNEL_BASE, 0x0,
-	    (MINSPLIT * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+	    (_end - KERNEL_BASE + L1_S_SIZE - 1),
 	    L1_S_PROTO | L1_S_AP_KRW  | L1_S_B | L1_S_C)
 	/* Map the 16MB of peripherals */
 	MMU_INIT(RPI_KERNEL_IO_VBASE, RPI_KERNEL_IO_PBASE,
-	    (RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+	    (RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1),
 	    L1_S_PROTO | L1_S_AP_KRW)
 	/* end of table */
 	MMU_INIT(0, 0, 0, 0)
 	.globl	_C_LABEL(rpi_boot_regs)
 rpi_boot_regs:
 	.space 4 * 4