Thu Sep 20 17:53:49 2012 UTC ()
sc_ahci_cap should be uint32_t


(matt)
diff -r1.13 -r1.14 src/sys/dev/ic/ahcisatavar.h

cvs diff -r1.13 -r1.14 src/sys/dev/ic/ahcisatavar.h (expand / switch to unified diff)

--- src/sys/dev/ic/ahcisatavar.h 2012/08/20 12:48:47 1.13
+++ src/sys/dev/ic/ahcisatavar.h 2012/09/20 17:53:48 1.14
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: ahcisatavar.h,v 1.13 2012/08/20 12:48:47 bouyer Exp $ */ 1/* $NetBSD: ahcisatavar.h,v 1.14 2012/09/20 17:53:48 matt Exp $ */
2 2
3/* 3/*
4 * Copyright (c) 2006 Manuel Bouyer. 4 * Copyright (c) 2006 Manuel Bouyer.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions 7 * modification, are permitted provided that the following conditions
8 * are met: 8 * are met:
9 * 1. Redistributions of source code must retain the above copyright 9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer. 10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright 11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the 12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution. 13 * documentation and/or other materials provided with the distribution.
14 * 14 *
@@ -50,27 +50,27 @@ struct ahci_softc { @@ -50,27 +50,27 @@ struct ahci_softc {
50 bus_size_t sc_ahcis; 50 bus_size_t sc_ahcis;
51 bus_dma_tag_t sc_dmat; /* DMA memory mappings: */ 51 bus_dma_tag_t sc_dmat; /* DMA memory mappings: */
52 void *sc_cmd_hdr; /* command tables and received FIS */ 52 void *sc_cmd_hdr; /* command tables and received FIS */
53 bus_dmamap_t sc_cmd_hdrd; 53 bus_dmamap_t sc_cmd_hdrd;
54 bus_dma_segment_t sc_cmd_hdr_seg; 54 bus_dma_segment_t sc_cmd_hdr_seg;
55 int sc_cmd_hdr_nseg; 55 int sc_cmd_hdr_nseg;
56 int sc_atac_capflags; 56 int sc_atac_capflags;
57 int sc_ahci_quirks; 57 int sc_ahci_quirks;
58#define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */ 58#define AHCI_PCI_QUIRK_FORCE __BIT(0) /* force attach */
59#define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */ 59#define AHCI_PCI_QUIRK_BAD64 __BIT(1) /* broken 64-bit DMA */
60#define AHCI_QUIRK_BADPMP __BIT(2) /* broken PMP support, ignore */ 60#define AHCI_QUIRK_BADPMP __BIT(2) /* broken PMP support, ignore */
61#define AHCI_QUIRK_BADPMPRESET __BIT(3) /* broken PMP support for reset */ 61#define AHCI_QUIRK_BADPMPRESET __BIT(3) /* broken PMP support for reset */
62 62
63 int32_t sc_ahci_cap; /* copy of AHCI_CAP */ 63 uint32_t sc_ahci_cap; /* copy of AHCI_CAP */
64 int sc_ncmds; /* number of command slots */ 64 int sc_ncmds; /* number of command slots */
65 struct ata_channel *sc_chanarray[AHCI_MAX_PORTS]; 65 struct ata_channel *sc_chanarray[AHCI_MAX_PORTS];
66 struct ahci_channel { 66 struct ahci_channel {
67 struct ata_channel ata_channel; /* generic part */ 67 struct ata_channel ata_channel; /* generic part */
68 bus_space_handle_t ahcic_scontrol; 68 bus_space_handle_t ahcic_scontrol;
69 bus_space_handle_t ahcic_sstatus; 69 bus_space_handle_t ahcic_sstatus;
70 bus_space_handle_t ahcic_serror; 70 bus_space_handle_t ahcic_serror;
71 /* pointers allocated from sc_cmd_hdrd */ 71 /* pointers allocated from sc_cmd_hdrd */
72 struct ahci_r_fis *ahcic_rfis; /* received FIS */ 72 struct ahci_r_fis *ahcic_rfis; /* received FIS */
73 bus_addr_t ahcic_bus_rfis; 73 bus_addr_t ahcic_bus_rfis;
74 struct ahci_cmd_header *ahcic_cmdh; /* command headers */ 74 struct ahci_cmd_header *ahcic_cmdh; /* command headers */
75 bus_addr_t ahcic_bus_cmdh; 75 bus_addr_t ahcic_bus_cmdh;
76 /* command tables (allocated per-channel) */ 76 /* command tables (allocated per-channel) */