Fri Sep 21 09:05:09 2012 UTC ()
adapt for _UC_TLSBASE.

Approved by manu@ and msaitoh@


(ryo)
diff -r1.100 -r1.101 src/sys/arch/sh3/sh3/sh3_machdep.c

cvs diff -r1.100 -r1.101 src/sys/arch/sh3/sh3/sh3_machdep.c (expand / switch to unified diff)

--- src/sys/arch/sh3/sh3/sh3_machdep.c 2012/07/08 20:14:12 1.100
+++ src/sys/arch/sh3/sh3/sh3_machdep.c 2012/09/21 09:05:08 1.101
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: sh3_machdep.c,v 1.100 2012/07/08 20:14:12 dsl Exp $ */ 1/* $NetBSD: sh3_machdep.c,v 1.101 2012/09/21 09:05:08 ryo Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 1996, 1997, 1998, 2002 The NetBSD Foundation, Inc. 4 * Copyright (c) 1996, 1997, 1998, 2002 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace 8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center. 9 * Simulation Facility, NASA Ames Research Center.
10 * 10 *
11 * Redistribution and use in source and binary forms, with or without 11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions 12 * modification, are permitted provided that the following conditions
13 * are met: 13 * are met:
14 * 1. Redistributions of source code must retain the above copyright 14 * 1. Redistributions of source code must retain the above copyright
@@ -55,27 +55,27 @@ @@ -55,27 +55,27 @@
55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
62 * SUCH DAMAGE. 62 * SUCH DAMAGE.
63 * 63 *
64 * @(#)machdep.c 7.4 (Berkeley) 6/3/91 64 * @(#)machdep.c 7.4 (Berkeley) 6/3/91
65 */ 65 */
66 66
67#include <sys/cdefs.h> 67#include <sys/cdefs.h>
68__KERNEL_RCSID(0, "$NetBSD: sh3_machdep.c,v 1.100 2012/07/08 20:14:12 dsl Exp $"); 68__KERNEL_RCSID(0, "$NetBSD: sh3_machdep.c,v 1.101 2012/09/21 09:05:08 ryo Exp $");
69 69
70#include "opt_ddb.h" 70#include "opt_ddb.h"
71#include "opt_kgdb.h" 71#include "opt_kgdb.h"
72#include "opt_memsize.h" 72#include "opt_memsize.h"
73#include "opt_kstack_debug.h" 73#include "opt_kstack_debug.h"
74#include "opt_ptrace.h" 74#include "opt_ptrace.h"
75 75
76#include <sys/param.h> 76#include <sys/param.h>
77#include <sys/systm.h> 77#include <sys/systm.h>
78 78
79#include <sys/buf.h> 79#include <sys/buf.h>
80#include <sys/exec.h> 80#include <sys/exec.h>
81#include <sys/kernel.h> 81#include <sys/kernel.h>
@@ -422,27 +422,27 @@ cpu_getmcontext(struct lwp *l, mcontext_ @@ -422,27 +422,27 @@ cpu_getmcontext(struct lwp *l, mcontext_
422 gr[_REG_R6] = tf->tf_r6; 422 gr[_REG_R6] = tf->tf_r6;
423 gr[_REG_R5] = tf->tf_r5; 423 gr[_REG_R5] = tf->tf_r5;
424 gr[_REG_R4] = tf->tf_r4; 424 gr[_REG_R4] = tf->tf_r4;
425 gr[_REG_R3] = tf->tf_r3; 425 gr[_REG_R3] = tf->tf_r3;
426 gr[_REG_R2] = tf->tf_r2; 426 gr[_REG_R2] = tf->tf_r2;
427 gr[_REG_R1] = tf->tf_r1; 427 gr[_REG_R1] = tf->tf_r1;
428 gr[_REG_R0] = tf->tf_r0; 428 gr[_REG_R0] = tf->tf_r0;
429 gr[_REG_R15] = tf->tf_r15; 429 gr[_REG_R15] = tf->tf_r15;
430 430
431 if ((ras_pc = (__greg_t)ras_lookup(l->l_proc, 431 if ((ras_pc = (__greg_t)ras_lookup(l->l_proc,
432 (void *) gr[_REG_PC])) != -1) 432 (void *) gr[_REG_PC])) != -1)
433 gr[_REG_PC] = ras_pc; 433 gr[_REG_PC] = ras_pc;
434 434
435 *flags |= _UC_CPU; 435 *flags |= (_UC_CPU|_UC_TLSBASE);
436 436
437 /* FPU context is currently not handled by the kernel. */ 437 /* FPU context is currently not handled by the kernel. */
438 memset(&mcp->__fpregs, 0, sizeof (mcp->__fpregs)); 438 memset(&mcp->__fpregs, 0, sizeof (mcp->__fpregs));
439} 439}
440 440
441int 441int
442cpu_mcontext_validate(struct lwp *l, const mcontext_t *mcp) 442cpu_mcontext_validate(struct lwp *l, const mcontext_t *mcp)
443{ 443{
444 struct trapframe *tf = l->l_md.md_regs; 444 struct trapframe *tf = l->l_md.md_regs;
445 const __greg_t *gr = mcp->__gregs; 445 const __greg_t *gr = mcp->__gregs;
446 446
447 if (((tf->tf_ssr ^ gr[_REG_SR]) & PSL_USERSTATIC) != 0) 447 if (((tf->tf_ssr ^ gr[_REG_SR]) & PSL_USERSTATIC) != 0)
448 return EINVAL; 448 return EINVAL;
@@ -455,50 +455,52 @@ cpu_setmcontext(struct lwp *l, const mco @@ -455,50 +455,52 @@ cpu_setmcontext(struct lwp *l, const mco
455{ 455{
456 struct trapframe *tf = l->l_md.md_regs; 456 struct trapframe *tf = l->l_md.md_regs;
457 const __greg_t *gr = mcp->__gregs; 457 const __greg_t *gr = mcp->__gregs;
458 struct proc *p = l->l_proc; 458 struct proc *p = l->l_proc;
459 int error; 459 int error;
460 460
461 /* Restore register context, if any. */ 461 /* Restore register context, if any. */
462 if ((flags & _UC_CPU) != 0) { 462 if ((flags & _UC_CPU) != 0) {
463 /* Check for security violations. */ 463 /* Check for security violations. */
464 error = cpu_mcontext_validate(l, mcp); 464 error = cpu_mcontext_validate(l, mcp);
465 if (error) 465 if (error)
466 return error; 466 return error;
467 467
468 tf->tf_gbr = gr[_REG_GBR]; 468 /* done in lwp_setprivate */
 469 /* tf->tf_gbr = gr[_REG_GBR]; */
469 tf->tf_spc = gr[_REG_PC]; 470 tf->tf_spc = gr[_REG_PC];
470 tf->tf_ssr = gr[_REG_SR]; 471 tf->tf_ssr = gr[_REG_SR];
471 tf->tf_macl = gr[_REG_MACL]; 472 tf->tf_macl = gr[_REG_MACL];
472 tf->tf_mach = gr[_REG_MACH]; 473 tf->tf_mach = gr[_REG_MACH];
473 tf->tf_pr = gr[_REG_PR]; 474 tf->tf_pr = gr[_REG_PR];
474 tf->tf_r14 = gr[_REG_R14]; 475 tf->tf_r14 = gr[_REG_R14];
475 tf->tf_r13 = gr[_REG_R13]; 476 tf->tf_r13 = gr[_REG_R13];
476 tf->tf_r12 = gr[_REG_R12]; 477 tf->tf_r12 = gr[_REG_R12];
477 tf->tf_r11 = gr[_REG_R11]; 478 tf->tf_r11 = gr[_REG_R11];
478 tf->tf_r10 = gr[_REG_R10]; 479 tf->tf_r10 = gr[_REG_R10];
479 tf->tf_r9 = gr[_REG_R9]; 480 tf->tf_r9 = gr[_REG_R9];
480 tf->tf_r8 = gr[_REG_R8]; 481 tf->tf_r8 = gr[_REG_R8];
481 tf->tf_r7 = gr[_REG_R7]; 482 tf->tf_r7 = gr[_REG_R7];
482 tf->tf_r6 = gr[_REG_R6]; 483 tf->tf_r6 = gr[_REG_R6];
483 tf->tf_r5 = gr[_REG_R5]; 484 tf->tf_r5 = gr[_REG_R5];
484 tf->tf_r4 = gr[_REG_R4]; 485 tf->tf_r4 = gr[_REG_R4];
485 tf->tf_r3 = gr[_REG_R3]; 486 tf->tf_r3 = gr[_REG_R3];
486 tf->tf_r2 = gr[_REG_R2]; 487 tf->tf_r2 = gr[_REG_R2];
487 tf->tf_r1 = gr[_REG_R1]; 488 tf->tf_r1 = gr[_REG_R1];
488 tf->tf_r0 = gr[_REG_R0]; 489 tf->tf_r0 = gr[_REG_R0];
489 tf->tf_r15 = gr[_REG_R15]; 490 tf->tf_r15 = gr[_REG_R15];
490 491
491 lwp_setprivate(l, (void *)(uintptr_t)gr[_REG_GBR]); 492 if (flags & _UC_TLSBASE)
 493 lwp_setprivate(l, (void *)(uintptr_t)gr[_REG_GBR]);
492 } 494 }
493 495
494#if 0 496#if 0
495 /* XXX: FPU context is currently not handled by the kernel. */ 497 /* XXX: FPU context is currently not handled by the kernel. */
496 if (flags & _UC_FPU) { 498 if (flags & _UC_FPU) {
497 /* TODO */; 499 /* TODO */;
498 } 500 }
499#endif 501#endif
500 502
501 mutex_enter(p->p_lock); 503 mutex_enter(p->p_lock);
502 if (flags & _UC_SETSTACK) 504 if (flags & _UC_SETSTACK)
503 l->l_sigstk.ss_flags |= SS_ONSTACK; 505 l->l_sigstk.ss_flags |= SS_ONSTACK;
504 if (flags & _UC_CLRSTACK) 506 if (flags & _UC_CLRSTACK)