 @@ -1,14 +1,14 @@
-/*	$NetBSD: armreg.h,v 1.66 2012/09/22 00:33:37 matt Exp $	*/
+/*	$NetBSD: armreg.h,v 1.67 2012/09/22 01:44:12 matt Exp $	*/
 /*
  * Copyright (c) 1998, 2001 Ben Harris
  * Copyright (c) 1994-1996 Mark Brinicombe.
  * Copyright (c) 1994 Brini.
  * All rights reserved.
+ *
  * This code is derived from software written for Brini by Mark Brinicombe
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
 @@ -559,26 +559,29 @@ ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c
 ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */
 ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */
 ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */
 ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */
 ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */
 ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */
 ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */
 ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */
 ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */
 ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
 ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
 ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
 ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
 /* c1 registers */
 ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
 ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Register */
 /* c2 registers */
 ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
 ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */
 ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
 ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */
 ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
 ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
 /* c5 registers */
 ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */
 ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */
 /* c6 registers */
 ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */
 ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */

 @@ -1,14 +1,14 @@
-/*      $NetBSD: vfpreg.h,v 1.4 2012/08/16 07:24:25 matt Exp $ */
+/*      $NetBSD: vfpreg.h,v 1.5 2012/09/22 01:44:12 matt Exp $ */
 /*
  * Copyright (c) 2008 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -38,33 +38,35 @@
 #define VFP_FPSID_IMP_ARM	0x41000000	/* Implementer: ARM */
 #define VFP_FPSID_SW		0x00800000	/* VFP implemented in SW */
 #define VFP_FPSID_FMT_MSK	0x00600000	/* FLDMX/FSTMX Format */
 #define VFP_FPSID_FMT_1		0x00000000	/* Standard format 1 */
 #define VFP_FPSID_FMT_2		0x00200000	/* Standard format 2 */
 #define VFP_FPSID_FMT_WEIRD	0x00600000	/* Non-standard format */
 #define VFP_FPSID_SP		0x00100000	/* Only single precision */
 #define VFP_FPSID_ARCH_MSK	0x000f0000	/* Architecture */
 #define VFP_FPSID_ARCH_V1	0x00000000	/* Arch VFPv1 */
 #define VFP_FPSID_ARCH_V2	0x00010000	/* Arch VFPv2 */
 #define VFP_FPSID_PART_MSK	0x0000ff00	/* Part number */
 #define VFP_FPSID_PART_VFP10	0x00001000	/* VFP10 */
 #define VFP_FPSID_PART_VFP11	0x00002000	/* VFP11 */
 #define VFP_FPSID_PART_VFP30	0x00003000	/* VFP30 */
 #define VFP_FPSID_VAR_MSK	0x000000f0	/* Variant */
 #define VFP_FPSID_VAR_ARM10	0x000000a0	/* Variant ARM10 */
 #define VFP_FPSID_VAR_ARM11	0x000000b0	/* Variant ARM11 */
 #define VFP_FPSID_REV_MSK	0x0000000f	/* Revision */
 #define FPU_VFP10_ARM10E	0x410001a0	/* Really a VFPv2 part */
 #define FPU_VFP11_ARM11		0x410120b0
 #define FPU_VFP30_CORTEXA9	0x41033090
 #define VFP_FPEXC_EX		0x80000000	/* Exception status bit */
 #define VFP_FPEXC_EN		0x40000000	/* VFP Enable bit */
 #define VFP_FPEXC_FP2V		0x10000000	/* FPINST2 instruction valid */
 #define VFP_FPEXC_VECITR	0x00000700	/* Vector iteration count */
 #define VFP_FPEXC_INV		0x00000080	/* Input exception flag */
 #define VFP_FPEXC_UFC		0x00000080	/* Potential underflow flag */
 #define VFP_FPEXC_OFC		0x00000080	/* Potential overflow flag */
 #define VFP_FPEXC_IOC		0x00000080	/* Potential inv. op. flag */
 #define VFP_FPSCR_N	0x80000000	/* set if compare <= result */
 #define VFP_FPSCR_Z	0x40000000	/* set if compare = result */
 #define VFP_FPSCR_C	0x20000000	/* set if compare (=,>=,UNORD) result */

 @@ -1,14 +1,14 @@
-/*      $NetBSD: vfp_init.c,v 1.5 2012/08/16 18:16:25 matt Exp $ */
+/*      $NetBSD: vfp_init.c,v 1.6 2012/09/22 01:44:12 matt Exp $ */
 /*
  * Copyright (c) 2008 ARM Ltd
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -212,55 +212,75 @@ vfp_attach(void)
 #else
 void
 vfp_attach(void)
+{
 	struct cpu_info * const ci = curcpu();
 	const char *model = NULL;
 	void *uh;
 	uh = install_coproc_handler(VFP_COPROC, vfp_test);
 	undefined_test = 0;
 #ifdef FPU_VFP
 	uint32_t cpacr = armreg_cpacr_read();
 	cpacr &= ~__BITS(21,20);
 	cpacr &= ~__BITS(23,22);
 	cpacr |= __SHIFTIN(1, __BITS(21,20));
 	cpacr |= __SHIFTIN(1, __BITS(23,22));
 	armreg_cpacr_write(cpacr);
 	cpacr = armreg_cpacr_read();
 	if ((cpacr & __BITS(23,22)) == 0) {
 		aprint_normal_dev(ci->ci_dev, "NEON not present\n");
+	}
 	if ((cpacr & __BITS(21,20)) == 0) {
 		aprint_normal_dev(ci->ci_dev, "VFP not present\n");
+	}
 #endif
 	const uint32_t fpsid = read_fpsid();
 	remove_coproc_handler(uh);
 	if (undefined_test != 0) {
 		aprint_normal_dev(ci->ci_dev, "No VFP detected\n");
 		install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
 		ci->ci_vfp_id = 0;
 		return;
+	}
 	ci->ci_vfp_id = fpsid;
 	switch (fpsid & ~ VFP_FPSID_REV_MSK) {
 	case FPU_VFP10_ARM10E:
 		model = "VFP10 R1";
 		break;
 	case FPU_VFP11_ARM11:
 		model = "VFP11";
 		break;
 	case FPU_VFP30_CORTEXA9:
 		model = "NEON MPE w/ VFP 3.0";
 		break;
 	default:
 		aprint_normal_dev(ci->ci_dev, "unrecognized VFP version %x\n",
 		    fpsid);
 		install_coproc_handler(VFP_COPROC, vfp_fpscr_handler);
 		return;
+	}
 	if (fpsid != 0) {
 		aprint_normal("vfp%d at %s: %s\n",
-		    curcpu()->ci_dev->dv_unit, curcpu()->ci_dev->dv_xname,
+		    device_unit(curcpu()->ci_dev), device_xname(curcpu()->ci_dev),
 		    model);
+	}
 	evcnt_attach_dynamic(&vfpevent_use, EVCNT_TYPE_MISC, NULL,
 	    "VFP", "proc use");
 	evcnt_attach_dynamic(&vfpevent_reuse, EVCNT_TYPE_MISC, NULL,
 	    "VFP", "proc re-use");
 	install_coproc_handler(VFP_COPROC, vfp_handler);
 	install_coproc_handler(VFP_COPROC2, vfp_handler);
+}
 /* The real handler for VFP bounces.  */
 static int
 vfp_handler(u_int address, u_int insn, trapframe_t *frame,