| @@ -476,26 +476,29 @@ | | | @@ -476,26 +476,29 @@ |
| 476 | #define PCIE_LINK_IN_L1 __BIT(0) | | 476 | #define PCIE_LINK_IN_L1 __BIT(0) |
| 477 | #define PCIE_STRAP_STATUS 0xf10 | | 477 | #define PCIE_STRAP_STATUS 0xf10 |
| 478 | #define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4) | | 478 | #define STRAP_PCIE_REPLAY_BUF_TM __BITS(8,4) |
| 479 | #define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3) | | 479 | #define STRAP_PCIE_USER_FOR_CE_GEN1 __BIT(3) |
| 480 | #define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2) | | 480 | #define STRAP_PCIE_USER_FOR_CE_1LANE __BIT(2) |
| 481 | #define STRAP_PCIE_IF_ENABLE __BIT(1) | | 481 | #define STRAP_PCIE_IF_ENABLE __BIT(1) |
| 482 | #define STRAP_PCIE_USER_RC_MODE __BIT(0) | | 482 | #define STRAP_PCIE_USER_RC_MODE __BIT(0) |
| 483 | #define PCIE_RESET_STATUS 0xf14 | | 483 | #define PCIE_RESET_STATUS 0xf14 |
| 484 | | | 484 | |
| 485 | #define PCIE_RESET_ENABLE_IN_PCIE_LINK_DOWN 0xf18 | | 485 | #define PCIE_RESET_ENABLE_IN_PCIE_LINK_DOWN 0xf18 |
| 486 | | | 486 | |
| 487 | #define PCIE_MISC_INTR_EN 0xf1c | | 487 | #define PCIE_MISC_INTR_EN 0xf1c |
| 488 | #define PCIE_TX_DEBUG_CFG 0xf20 | | 488 | #define PCIE_TX_DEBUG_CFG 0xf20 |
| | | 489 | #define PCIE_ERROR_INTR_EN 0xf30 |
| | | 490 | #define PCIE_ERROR_INTR_CLR 0xf34 |
| | | 491 | #define PCIE_ERROR_INTR_STS 0xf38 |
| 489 | | | 492 | |
| 490 | | | 493 | |
| 491 | // PCIE_SYS_MSI_INTR_EN | | 494 | // PCIE_SYS_MSI_INTR_EN |
| 492 | #define MSI_INTR_EN_EQ_5 __BIT(5) | | 495 | #define MSI_INTR_EN_EQ_5 __BIT(5) |
| 493 | #define MSI_INTR_EN_EQ_4 __BIT(4) | | 496 | #define MSI_INTR_EN_EQ_4 __BIT(4) |
| 494 | #define MSI_INTR_EN_EQ_3 __BIT(3) | | 497 | #define MSI_INTR_EN_EQ_3 __BIT(3) |
| 495 | #define MSI_INTR_EN_EQ_2 __BIT(2) | | 498 | #define MSI_INTR_EN_EQ_2 __BIT(2) |
| 496 | #define MSI_INTR_EN_EQ_1 __BIT(1) | | 499 | #define MSI_INTR_EN_EQ_1 __BIT(1) |
| 497 | #define MSI_INTR_EN_EQ_0 __BIT(0) | | 500 | #define MSI_INTR_EN_EQ_0 __BIT(0) |
| 498 | | | 501 | |
| 499 | // PCIE_SYS_MSI_CTRL<n> | | 502 | // PCIE_SYS_MSI_CTRL<n> |
| 500 | #define INT_N_DELAY __BITS(9,6) | | 503 | #define INT_N_DELAY __BITS(9,6) |
| 501 | #define INT_N_EVENT __BITS(1,1) | | 504 | #define INT_N_EVENT __BITS(1,1) |
| @@ -517,27 +520,48 @@ | | | @@ -517,27 +520,48 @@ |
| 517 | // PCIE_SYS_RC_INTRX_CSR | | 520 | // PCIE_SYS_RC_INTRX_CSR |
| 518 | #define RC_INTD __BIT(3) | | 521 | #define RC_INTD __BIT(3) |
| 519 | #define RC_INTC __BIT(2) | | 522 | #define RC_INTC __BIT(2) |
| 520 | #define RC_INTB __BIT(1) | | 523 | #define RC_INTB __BIT(1) |
| 521 | #define RC_INTA __BIT(0) | | 524 | #define RC_INTA __BIT(0) |
| 522 | | | 525 | |
| 523 | // PCIE_IARR_0_LOWER / UPPER | | 526 | // PCIE_IARR_0_LOWER / UPPER |
| 524 | #define IARR0_ADDR __BIT(31,15) | | 527 | #define IARR0_ADDR __BIT(31,15) |
| 525 | #define IARR0_VALID __BIT(0) | | 528 | #define IARR0_VALID __BIT(0) |
| 526 | | | 529 | |
| 527 | // PCIE_IARR_1_LOWER / UPPER | | 530 | // PCIE_IARR_1_LOWER / UPPER |
| 528 | #define IARR1_ADDR __BIT(31,20) | | 531 | #define IARR1_ADDR __BIT(31,20) |
| 529 | #define IARR1_SIZE __BIT(7,0) | | 532 | #define IARR1_SIZE __BIT(7,0) |
| 530 | #define IARR0_VALID __BIT(0) | | 533 | |
| | | 534 | // PCIE_IARR_2_LOWER / UPPER |
| | | 535 | #define IARR2_ADDR __BIT(31,20) |
| | | 536 | #define IARR2_SIZE __BIT(7,0) |
| | | 537 | |
| | | 538 | // PCIE_MISC_INTR_EN |
| | | 539 | #define INTR_EN_PCIE_ERR_ATTN __BIT(2) |
| | | 540 | #define INTR_EN_PAXB_ECC_2B_ATTN __BIT(1) |
| | | 541 | #define INTR_EN_PCIE_IN_WAKE_B __BIT(0) |
| | | 542 | |
| | | 543 | // PCIE_ERR_INTR_{EN,CLR,STS} |
| | | 544 | #define PCIE_OVERFLOW_UNDERFLOW_INTR __BIT(10) |
| | | 545 | #define PCIE_AXI_MASTER_RRESP_SLV_ERR_INTR __BIT(9) |
| | | 546 | #define PCIE_AXI_MASTER_RRESP_DECERR_INTR __BIT(8) |
| | | 547 | #define PCIE_ECRC_ERR_INTR __BIT(7) |
| | | 548 | #define PCIE_CMPL_TIMEROUT_INTR __BIT(6) |
| | | 549 | #define PCIE_ERR_ATTN_INTR __BIT(5) |
| | | 550 | #define PCIE_IN_WAKE_B_INTR __BIT(4) |
| | | 551 | #define PCIE_REPLAY_BUF_2B_ECC_ERR_INTR __BIT(3) |
| | | 552 | #define PCIE_RD_CMPL_BUF_1_2B_ECC_ERR_INTR __BIT(2) |
| | | 553 | #define PCIE_RD_CMPL_BUF_0_2B_ECC_ERR_INTR __BIT(1) |
| | | 554 | #define PCIE_WR_DATA_BUF_2B_ECC_ERR_INTR __BIT(0) |
| 531 | | | 555 | |
| 532 | #define REGS_DEVICE_CAPACITY 0x04d4 | | 556 | #define REGS_DEVICE_CAPACITY 0x04d4 |
| 533 | #define REGS_LINK_CAPACITY 0x03dc | | 557 | #define REGS_LINK_CAPACITY 0x03dc |
| 534 | #define REGS_TL_CONTROL_0 0x0800 | | 558 | #define REGS_TL_CONTROL_0 0x0800 |
| 535 | #define REGS_DL_STATUS 0x1048 | | 559 | #define REGS_DL_STATUS 0x1048 |
| 536 | | | 560 | |
| 537 | #endif /* PCIE_PRIVATE */ | | 561 | #endif /* PCIE_PRIVATE */ |
| 538 | | | 562 | |
| 539 | #define ARMCORE_SCU_BASE 0x20000 /* CBAR is 19020000 */ | | 563 | #define ARMCORE_SCU_BASE 0x20000 /* CBAR is 19020000 */ |
| 540 | #define ARMCORE_L2C_BASE 0x22000 | | 564 | #define ARMCORE_L2C_BASE 0x22000 |
| 541 | | | 565 | |
| 542 | #ifdef ARMCORE_PRIVATE | | 566 | #ifdef ARMCORE_PRIVATE |
| 543 | | | 567 | |