 @@ -1,881 +1,897 @@
-/*	$NetBSD: aac_pci.c,v 1.33 2011/09/29 12:51:28 is Exp $	*/
+/*	$NetBSD: aac_pci.c,v 1.34 2012/09/23 01:10:59 chs Exp $	*/
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Andrew Doran.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 2000 Michael Smith
  * Copyright (c) 2000 BSDi
  * Copyright (c) 2000 Niklas Hallqvist
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * from FreeBSD: aac_pci.c,v 1.1 2000/09/13 03:20:34 msmith Exp
  * via OpenBSD: aac_pci.c,v 1.7 2002/03/14 01:26:58 millert Exp
  */
 /*
  * PCI front-end for the `aac' driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.33 2011/09/29 12:51:28 is Exp $");
+__KERNEL_RCSID(0, "$NetBSD: aac_pci.c,v 1.34 2012/09/23 01:10:59 chs Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 #include <sys/kernel.h>
 #include <sys/malloc.h>
 #include <sys/queue.h>
 #include <sys/bus.h>
 #include <machine/endian.h>
 #include <sys/intr.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/ic/aacreg.h>
 #include <dev/ic/aacvar.h>
 struct aac_pci_softc {
 	struct aac_softc	sc_aac;
 	pci_chipset_tag_t	sc_pc;
 	pci_intr_handle_t	sc_ih;
 };
 /* i960Rx interface */
 static int	aac_rx_get_fwstatus(struct aac_softc *);
 static void	aac_rx_qnotify(struct aac_softc *, int);
 static int	aac_rx_get_istatus(struct aac_softc *);
 static void	aac_rx_clear_istatus(struct aac_softc *, int);
 static void	aac_rx_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t,
 			   u_int32_t, u_int32_t, u_int32_t);
 static uint32_t aac_rx_get_mailbox(struct aac_softc *, int);
 static void	aac_rx_set_interrupts(struct aac_softc *, int);
 static int	aac_rx_send_command(struct aac_softc *, struct aac_ccb *);
 static int	aac_rx_get_outb_queue(struct aac_softc *);
 static void	aac_rx_set_outb_queue(struct aac_softc *, int);
 /* StrongARM interface */
 static int	aac_sa_get_fwstatus(struct aac_softc *);
 static void	aac_sa_qnotify(struct aac_softc *, int);
 static int	aac_sa_get_istatus(struct aac_softc *);
 static void	aac_sa_clear_istatus(struct aac_softc *, int);
 static void	aac_sa_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t,
 			   u_int32_t, u_int32_t, u_int32_t);
 static uint32_t aac_sa_get_mailbox(struct aac_softc *, int);
 static void	aac_sa_set_interrupts(struct aac_softc *, int);
 /* Rocket/MIPS interface */
 static int	aac_rkt_get_fwstatus(struct aac_softc *);
 static void	aac_rkt_qnotify(struct aac_softc *, int);
 static int	aac_rkt_get_istatus(struct aac_softc *);
 static void	aac_rkt_clear_istatus(struct aac_softc *, int);
 static void	aac_rkt_set_mailbox(struct aac_softc *, u_int32_t, u_int32_t,
 			   u_int32_t, u_int32_t, u_int32_t);
 static uint32_t aac_rkt_get_mailbox(struct aac_softc *, int);
 static void	aac_rkt_set_interrupts(struct aac_softc *, int);
 static int	aac_rkt_send_command(struct aac_softc *, struct aac_ccb *);
 static int	aac_rkt_get_outb_queue(struct aac_softc *);
 static void	aac_rkt_set_outb_queue(struct aac_softc *, int);
 static const struct aac_interface aac_rx_interface = {
 	aac_rx_get_fwstatus,
 	aac_rx_qnotify,
 	aac_rx_get_istatus,
 	aac_rx_clear_istatus,
 	aac_rx_set_mailbox,
 	aac_rx_get_mailbox,
 	aac_rx_set_interrupts,
 	aac_rx_send_command,
 	aac_rx_get_outb_queue,
 	aac_rx_set_outb_queue
 };
 static const struct aac_interface aac_sa_interface = {
 	aac_sa_get_fwstatus,
 	aac_sa_qnotify,
 	aac_sa_get_istatus,
 	aac_sa_clear_istatus,
 	aac_sa_set_mailbox,
 	aac_sa_get_mailbox,
 	aac_sa_set_interrupts,
 	NULL, NULL, NULL
 };
 static const struct aac_interface aac_rkt_interface = {
 	aac_rkt_get_fwstatus,
 	aac_rkt_qnotify,
 	aac_rkt_get_istatus,
 	aac_rkt_clear_istatus,
 	aac_rkt_set_mailbox,
 	aac_rkt_get_mailbox,
 	aac_rkt_set_interrupts,
 	aac_rkt_send_command,
 	aac_rkt_get_outb_queue,
 	aac_rkt_set_outb_queue
 };
 static struct aac_ident {
 	u_short	vendor;
 	u_short	device;
 	u_short	subvendor;
 	u_short	subdevice;
 	u_short	hwif;
 	u_short	quirks;
 	const char	*prodstr;
 } const aac_ident[] = {
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_2SI,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_2SI,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 2/Si"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_SUB2,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_SUB3,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_2,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_2_SUB,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+        {
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3_SUB,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3_SUB2,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3DI_3_SUB3,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Di"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3SI,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3SI,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Si"
 	},
+	{
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3SI_2,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_PERC_3SI_2_SUB,
 		AAC_HWIF_I960RX,
 ,
 		"Dell PERC 3/Si"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_DELL_CERC_1_5,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB,
 		"Dell CERC SATA RAID 1.5/6ch"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_AAC2622,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_AAC2622,
 		AAC_HWIF_I960RX,
 ,
 		"Adaptec ADP-2622"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S_SUB2M,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS,
 		"Adaptec ASR-2200S"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_DELL,
 		PCI_PRODUCT_ADP2_ASR2200S_SUB2M,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS,
 		"Dell PERC 320/DC"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS,
 		"Adaptec ASR-2200S"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_AAR2810SA,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB,
 		"Adaptec AAR-2810SA"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2120S,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB | AAC_QUIRK_256FIBS,
 		"Adaptec ASR-2120S"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2410SA,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB,
 		"Adaptec ASR-2410SA"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_HP,
 		PCI_PRODUCT_ADP2_HP_M110_G2,
 		AAC_HWIF_I960RX,
 		AAC_QUIRK_NO4GB,
 		"HP ML110 G2 (Adaptec ASR-2610SA)"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2120S,
 		PCI_VENDOR_IBM,
 		PCI_PRODUCT_IBM_SERVERAID8K,
 		AAC_HWIF_RKT,
 ,
 		"IBM ServeRAID 8k"
 	},
 	{	PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_2405,
 		AAC_HWIF_I960RX,
 ,
 		"Adaptec RAID 2405"
 	},
 	{	PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_3405,
 		AAC_HWIF_I960RX,
 ,
 		"Adaptec RAID 3405"
 	},
 	{	PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_3805,
 		AAC_HWIF_I960RX,
 ,
 		"Adaptec RAID 3805"
 	},
+	{
 		PCI_VENDOR_DEC,
 		PCI_PRODUCT_DEC_21554,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_AAC364,
 		AAC_HWIF_STRONGARM,
 ,
 		"Adaptec AAC-364"
 	},
+	{
 		PCI_VENDOR_DEC,
 		PCI_PRODUCT_DEC_21554,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR5400S,
 		AAC_HWIF_STRONGARM,
 		AAC_QUIRK_BROKEN_MMAP,
 		"Adaptec ASR-5400S"
 	},
+	{
 		PCI_VENDOR_DEC,
 		PCI_PRODUCT_DEC_21554,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_PERC_2QC,
 		AAC_HWIF_STRONGARM,
 		AAC_QUIRK_PERC2QC,
 		"Dell PERC 2/QC"
 	},
+	{
 		PCI_VENDOR_DEC,
 		PCI_PRODUCT_DEC_21554,
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_PERC_3QC,
 		AAC_HWIF_STRONGARM,
 ,
 		"Dell PERC 3/QC"
 	},
+	{
 		PCI_VENDOR_DEC,
 		PCI_PRODUCT_DEC_21554,
 		PCI_VENDOR_HP,
 		PCI_PRODUCT_HP_NETRAID_4M,
 		AAC_HWIF_STRONGARM,
 ,
 		"HP NetRAID-4M"
 	},
+	{
 		PCI_VENDOR_ADP2,
 		PCI_PRODUCT_ADP2_ASR2200S,
 		PCI_VENDOR_SUN,
 		PCI_PRODUCT_ADP2_ASR2120S,
 		AAC_HWIF_I960RX,
 ,
 		"SG-XPCIESAS-R-IN"
 	},
 };
 static const struct aac_ident *
 aac_find_ident(struct pci_attach_args *pa)
+{
 	const struct aac_ident *m, *mm;
 	u_int32_t subsysid;
 	m = aac_ident;
 	mm = aac_ident + (sizeof(aac_ident) / sizeof(aac_ident[0]));
 	while (m < mm) {
 		if (m->vendor == PCI_VENDOR(pa->pa_id) &&
 		    m->device == PCI_PRODUCT(pa->pa_id)) {
 			subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag,
 			    PCI_SUBSYS_ID_REG);
 			if (m->subvendor == PCI_VENDOR(subsysid) &&
 			    m->subdevice == PCI_PRODUCT(subsysid))
 				return (m);
+		}
 		m++;
+	}
 	return (NULL);
+}
 static int
 aac_pci_intr_set(struct aac_softc *sc, int (*hand)(void*), void *arg)
+{
 	struct aac_pci_softc	*pcisc;
 	pcisc = (struct aac_pci_softc *) sc;
 	pci_intr_disestablish(pcisc->sc_pc, sc->sc_ih);
 	sc->sc_ih = pci_intr_establish(pcisc->sc_pc, pcisc->sc_ih,
 				       IPL_BIO, hand, arg);
 	if (sc->sc_ih == NULL) {
 		return ENXIO;
+	}
 	return 0;
+}
 static int
 aac_pci_match(device_t parent, cfdata_t match, void *aux)
+{
 	struct pci_attach_args *pa;
 	pa = aux;
 	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O)
 		return (0);
 	return (aac_find_ident(pa) != NULL);
+}
 static void
 aac_pci_attach(device_t parent, device_t self, void *aux)
+{
 	struct pci_attach_args *pa;
 	pci_chipset_tag_t pc;
 	struct aac_pci_softc *pcisc;
 	struct aac_softc *sc;
 	u_int16_t command;
 	bus_addr_t membase;
 	bus_size_t memsize;
 	const char *intrstr;
 	int state;
 	const struct aac_ident *m;
 	pa = aux;
 	pc = pa->pa_pc;
 	pcisc = device_private(self);
 	pcisc->sc_pc = pc;
 	sc = &pcisc->sc_aac;
 	state = 0;
 	aprint_naive(": RAID controller\n");
 	aprint_normal(": ");
 	/*
 	 * Verify that the adapter is correctly set up in PCI space.
 	 */
 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	command |= PCI_COMMAND_MASTER_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
 	command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	AAC_DPRINTF(AAC_D_MISC, ("pci command status reg 0x08x "));
 	if ((command & PCI_COMMAND_MASTER_ENABLE) == 0) {
 		aprint_error("can't enable bus-master feature\n");
 		goto bail_out;
+	}
 	if ((command & PCI_COMMAND_MEM_ENABLE) == 0) {
 		aprint_error("memory window not available\n");
 		goto bail_out;
+	}
 	/*
 	 * Map control/status registers.
 	 */
 	if (pci_mapreg_map(pa, PCI_MAPREG_START,
 	    PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->sc_memt,
 	    &sc->sc_memh, &membase, &memsize)) {
 		aprint_error("can't find mem space\n");
 		goto bail_out;
+	}
 	state++;
 	if (pci_intr_map(pa, &pcisc->sc_ih)) {
 		aprint_error("couldn't map interrupt\n");
 		goto bail_out;
+	}
 	intrstr = pci_intr_string(pc, pcisc->sc_ih);
 	sc->sc_ih = pci_intr_establish(pc, pcisc->sc_ih, IPL_BIO, aac_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error("couldn't establish interrupt");
 		if (intrstr != NULL)
 			aprint_error(" at %s", intrstr);
 		aprint_error("\n");
 		goto bail_out;
+	}
 	state++;
 	sc->sc_dmat = pa->pa_dmat;
 	m = aac_find_ident(pa);
 	aprint_normal("%s\n", m->prodstr);
 	if (intrstr != NULL)
 		aprint_normal_dev(&sc->sc_dv, "interrupting at %s\n",
 		    intrstr);
 	sc->sc_hwif = m->hwif;
 	sc->sc_quirks = m->quirks;
 	switch (sc->sc_hwif) {
 		case AAC_HWIF_I960RX:
 			AAC_DPRINTF(AAC_D_MISC,
 			    ("set hardware up for i960Rx"));
 			sc->sc_if = aac_rx_interface;
 			break;
 		case AAC_HWIF_STRONGARM:
 			AAC_DPRINTF(AAC_D_MISC,
 			    ("set hardware up for StrongARM"));
 			sc->sc_if = aac_sa_interface;
 			break;
 		case AAC_HWIF_RKT:
 			AAC_DPRINTF(AAC_D_MISC,
 			    ("set hardware up for MIPS/Rocket"));
 			sc->sc_if = aac_rkt_interface;
 			break;
+	}
 	sc->sc_regsize = memsize;
 	sc->sc_intr_set = aac_pci_intr_set;
 	if (!aac_attach(sc))
 		return;
  bail_out:
 	if (state > 1)
 		pci_intr_disestablish(pc, sc->sc_ih);
 	if (state > 0)
 		bus_space_unmap(sc->sc_memt, sc->sc_memh, memsize);
+}
 CFATTACH_DECL(aac_pci, sizeof(struct aac_pci_softc),
     aac_pci_match, aac_pci_attach, NULL, NULL);
 /*
  * Read the current firmware status word.
  */
 static int
 aac_sa_get_fwstatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG4(sc, AAC_SA_FWSTATUS));
+}
 static int
 aac_rx_get_fwstatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG4(sc, AAC_RX_FWSTATUS));
+}
 static int
 aac_rkt_get_fwstatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG4(sc, AAC_RKT_FWSTATUS));
+}
 /*
  * Notify the controller of a change in a given queue
  */
 static void
 aac_sa_qnotify(struct aac_softc *sc, int qbit)
+{
 	AAC_SETREG2(sc, AAC_SA_DOORBELL1_SET, qbit);
+}
 static void
 aac_rx_qnotify(struct aac_softc *sc, int qbit)
+{
 	AAC_SETREG4(sc, AAC_RX_IDBR, qbit);
+}
 static void
 aac_rkt_qnotify(struct aac_softc *sc, int qbit)
+{
 	AAC_SETREG4(sc, AAC_RKT_IDBR, qbit);
+}
 /*
  * Get the interrupt reason bits
  */
 static int
 aac_sa_get_istatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG2(sc, AAC_SA_DOORBELL0));
+}
 static int
 aac_rx_get_istatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG4(sc, AAC_RX_ODBR));
+}
 static int
 aac_rkt_get_istatus(struct aac_softc *sc)
+{
 	return (AAC_GETREG4(sc, AAC_RKT_ODBR));
+}
 /*
  * Clear some interrupt reason bits
  */
 static void
 aac_sa_clear_istatus(struct aac_softc *sc, int mask)
+{
 	AAC_SETREG2(sc, AAC_SA_DOORBELL0_CLEAR, mask);
+}
 static void
 aac_rx_clear_istatus(struct aac_softc *sc, int mask)
+{
 	AAC_SETREG4(sc, AAC_RX_ODBR, mask);
+}
 static void
 aac_rkt_clear_istatus(struct aac_softc *sc, int mask)
+{
 	AAC_SETREG4(sc, AAC_RKT_ODBR, mask);
+}
 /*
  * Populate the mailbox and set the command word
  */
 static void
 aac_sa_set_mailbox(struct aac_softc *sc, u_int32_t command,
 		   u_int32_t arg0, u_int32_t arg1, u_int32_t arg2,
 		   u_int32_t arg3)
+{
 	AAC_SETREG4(sc, AAC_SA_MAILBOX, command);
 	AAC_SETREG4(sc, AAC_SA_MAILBOX + 4, arg0);
 	AAC_SETREG4(sc, AAC_SA_MAILBOX + 8, arg1);
 	AAC_SETREG4(sc, AAC_SA_MAILBOX + 12, arg2);
 	AAC_SETREG4(sc, AAC_SA_MAILBOX + 16, arg3);
+}
 static void
 aac_rx_set_mailbox(struct aac_softc *sc, u_int32_t command,
 		   u_int32_t arg0, u_int32_t arg1, u_int32_t arg2,
 		   u_int32_t arg3)
+{
 	AAC_SETREG4(sc, AAC_RX_MAILBOX, command);
 	AAC_SETREG4(sc, AAC_RX_MAILBOX + 4, arg0);
 	AAC_SETREG4(sc, AAC_RX_MAILBOX + 8, arg1);
 	AAC_SETREG4(sc, AAC_RX_MAILBOX + 12, arg2);
 	AAC_SETREG4(sc, AAC_RX_MAILBOX + 16, arg3);
+}
 static void
 aac_rkt_set_mailbox(struct aac_softc *sc, u_int32_t command,
 		    u_int32_t arg0, u_int32_t arg1, u_int32_t arg2,
 		    u_int32_t arg3)
+{
 	AAC_SETREG4(sc, AAC_RKT_MAILBOX, command);
 	AAC_SETREG4(sc, AAC_RKT_MAILBOX + 4, arg0);
 	AAC_SETREG4(sc, AAC_RKT_MAILBOX + 8, arg1);
 	AAC_SETREG4(sc, AAC_RKT_MAILBOX + 12, arg2);
 	AAC_SETREG4(sc, AAC_RKT_MAILBOX + 16, arg3);
+}
 /*
  * Fetch the specified mailbox
  */
 static uint32_t
 aac_sa_get_mailbox(struct aac_softc *sc, int mb)
+{
 	return (AAC_GETREG4(sc, AAC_SA_MAILBOX + (mb * 4)));
+}
 static uint32_t
 aac_rx_get_mailbox(struct aac_softc *sc, int mb)
+{
 	return (AAC_GETREG4(sc, AAC_RX_MAILBOX + (mb * 4)));
+}
 static uint32_t
 aac_rkt_get_mailbox(struct aac_softc *sc, int mb)
+{
 	return (AAC_GETREG4(sc, AAC_RKT_MAILBOX + (mb * 4)));
+}
 /*
  * Set/clear interrupt masks
  */
 static void
 aac_sa_set_interrupts(struct aac_softc *sc, int enable)
+{
 	if (enable)
 		AAC_SETREG2((sc), AAC_SA_MASK0_CLEAR, AAC_DB_INTERRUPTS);
 	else
 		AAC_SETREG2((sc), AAC_SA_MASK0_SET, ~0);
+}
 static void
 aac_rx_set_interrupts(struct aac_softc *sc, int enable)
+{
 	if (enable) {
 		if (sc->sc_quirks & AAC_QUIRK_NEW_COMM)
 			AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INT_NEW_COMM);
 		else
 			AAC_SETREG4(sc, AAC_RX_OIMR, ~AAC_DB_INTERRUPTS);
 	} else {
 		AAC_SETREG4(sc, AAC_RX_OIMR, ~0);
+	}
+}
 static void
 aac_rkt_set_interrupts(struct aac_softc *sc, int enable)
+{
 	if (enable) {
 		if (sc->sc_quirks & AAC_QUIRK_NEW_COMM)
 			AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INT_NEW_COMM);
 		else
 			AAC_SETREG4(sc, AAC_RKT_OIMR, ~AAC_DB_INTERRUPTS);
 	} else {
 		AAC_SETREG4(sc, AAC_RKT_OIMR, ~0);
+	}
+}
 /*
  * New comm. interface: Send command functions
  */
 static int
 aac_rx_send_command(struct aac_softc *sc, struct aac_ccb *ac)
+{
 	u_int32_t	index, device;
 	index = AAC_GETREG4(sc, AAC_RX_IQUE);
 	if (index == 0xffffffffL)
 		index = AAC_GETREG4(sc, AAC_RX_IQUE);
 	if (index == 0xffffffffL)
 		return index;
 #ifdef notyet
 	aac_enqueue_busy(ac);
 #endif
 	device = index;
 	AAC_SETREG4(sc, device,
 	    htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL)));
 	device += 4;
 	if (sizeof(bus_addr_t) > 4) {
 		AAC_SETREG4(sc, device,
 		    htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32)));
 	} else {
 		AAC_SETREG4(sc, device, 0);
+	}
 	device += 4;
 	AAC_SETREG4(sc, device, ac->ac_fib->Header.Size);
 	AAC_SETREG4(sc, AAC_RX_IQUE, index);
 	return 0;
+}
 static int
 aac_rkt_send_command(struct aac_softc *sc, struct aac_ccb *ac)
+{
 	u_int32_t	index, device;
 	index = AAC_GETREG4(sc, AAC_RKT_IQUE);
 	if (index == 0xffffffffL)
 		index = AAC_GETREG4(sc, AAC_RKT_IQUE);
 	if (index == 0xffffffffL)
 		return index;
 #ifdef notyet
 	aac_enqueue_busy(ac);
 #endif
 	device = index;
 	AAC_SETREG4(sc, device,
 	    htole32((u_int32_t)(ac->ac_fibphys & 0xffffffffUL)));
 	device += 4;
 	if (sizeof(bus_addr_t) > 4) {
 		AAC_SETREG4(sc, device,
 		    htole32((u_int32_t)((u_int64_t)ac->ac_fibphys >> 32)));
 	} else {
 		AAC_SETREG4(sc, device, 0);
+	}
 	device += 4;
 	AAC_SETREG4(sc, device, ac->ac_fib->Header.Size);
 	AAC_SETREG4(sc, AAC_RKT_IQUE, index);
 	return 0;
+}
 /*
  * New comm. interface: get, set outbound queue index
  */
 static int
 aac_rx_get_outb_queue(struct aac_softc *sc)
+{
 	return AAC_GETREG4(sc, AAC_RX_OQUE);
+}
 static int
 aac_rkt_get_outb_queue(struct aac_softc *sc)
+{
 	return AAC_GETREG4(sc, AAC_RKT_OQUE);
+}
 static void
 aac_rx_set_outb_queue(struct aac_softc *sc, int index)
+{
 	AAC_SETREG4(sc, AAC_RX_OQUE, index);
+}
 static void
 aac_rkt_set_outb_queue(struct aac_softc *sc, int index)
+{
 	AAC_SETREG4(sc, AAC_RKT_OQUE, index);
+}

 @@ -1,1742 +1,1745 @@
-/*	$NetBSD: if_sip.c,v 1.154 2012/07/22 14:33:03 matt Exp $	*/
+/*	$NetBSD: if_sip.c,v 1.155 2012/09/23 01:10:59 chs Exp $	*/
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*-
  * Copyright (c) 1999 Network Computer, Inc.
  * All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. Neither the name of Network Computer, Inc. nor the names of its
  *    contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY NETWORK COMPUTER, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * Device driver for the Silicon Integrated Systems SiS 900,
  * SiS 7016 10/100, National Semiconductor DP83815 10/100, and
  * National Semiconductor DP83820 10/100/1000 PCI Ethernet
  * controllers.
+ *
  * Originally written to support the SiS 900 by Jason R. Thorpe for
  * Network Computer, Inc.
+ *
  * TODO:
+ *
  *	- Reduce the Rx interrupt load.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.154 2012/07/22 14:33:03 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_sip.c,v 1.155 2012/09/23 01:10:59 chs Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/rnd.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_sipreg.h>
 /*
  * Transmit descriptor list size.  This is arbitrary, but allocate
  * enough descriptors for 128 pending transmissions, and 8 segments
  * per packet (64 for DP83820 for jumbo frames).
+ *
  * This MUST work out to a power of 2.
  */
 #define	GSIP_NTXSEGS_ALLOC 16
 #define	SIP_NTXSEGS_ALLOC 8
 #define	SIP_TXQUEUELEN		256
 #define	MAX_SIP_NTXDESC	\
     (SIP_TXQUEUELEN * MAX(SIP_NTXSEGS_ALLOC, GSIP_NTXSEGS_ALLOC))
 /*
  * Receive descriptor list size.  We have one Rx buffer per incoming
  * packet, so this logic is a little simpler.
+ *
  * Actually, on the DP83820, we allow the packet to consume more than
  * one buffer, in order to support jumbo Ethernet frames.  In that
  * case, a packet may consume up to 5 buffers (assuming a 2048 byte
  * mbuf cluster).  256 receive buffers is only 51 maximum size packets,
  * so we'd better be quick about handling receive interrupts.
  */
 #define	GSIP_NRXDESC		256
 #define	SIP_NRXDESC		128
 #define	MAX_SIP_NRXDESC	MAX(GSIP_NRXDESC, SIP_NRXDESC)
 /*
  * Control structures are DMA'd to the SiS900 chip.  We allocate them in
  * a single clump that maps to a single DMA segment to make several things
  * easier.
  */
 struct sip_control_data {
 	/*
 	 * The transmit descriptors.
 	 */
 	struct sip_desc scd_txdescs[MAX_SIP_NTXDESC];
 	/*
 	 * The receive descriptors.
 	 */
 	struct sip_desc scd_rxdescs[MAX_SIP_NRXDESC];
 };
 #define	SIP_CDOFF(x)	offsetof(struct sip_control_data, x)
 #define	SIP_CDTXOFF(x)	SIP_CDOFF(scd_txdescs[(x)])
 #define	SIP_CDRXOFF(x)	SIP_CDOFF(scd_rxdescs[(x)])
 /*
  * Software state for transmit jobs.
  */
 struct sip_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	SIMPLEQ_ENTRY(sip_txsoft) txs_q;
 };
 SIMPLEQ_HEAD(sip_txsq, sip_txsoft);
 /*
  * Software state for receive jobs.
  */
 struct sip_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 enum sip_attach_stage {
 	  SIP_ATTACH_FIN = 0
 	, SIP_ATTACH_CREATE_RXMAP
 	, SIP_ATTACH_CREATE_TXMAP
 	, SIP_ATTACH_LOAD_MAP
 	, SIP_ATTACH_CREATE_MAP
 	, SIP_ATTACH_MAP_MEM
 	, SIP_ATTACH_ALLOC_MEM
 	, SIP_ATTACH_INTR
 	, SIP_ATTACH_MAP
 };
 /*
  * Software state per device.
  */
 struct sip_softc {
 	device_t sc_dev;		/* generic device information */
 	device_suspensor_t		sc_suspensor;
 	pmf_qual_t			sc_qual;
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_sz;		/* bus space size */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	pci_chipset_tag_t sc_pc;
 	bus_dma_segment_t sc_seg;
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	const struct sip_product *sc_model; /* which model are we? */
 	int sc_gigabit;			/* 1: 83820, 0: other */
 	int sc_rev;			/* chip revision */
 	void *sc_ih;			/* interrupt cookie */
 	struct mii_data sc_mii;		/* MII/media information */
 	callout_t sc_tick_ch;		/* tick callout */
 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
 	/*
 	 * Software state for transmit and receive descriptors.
 	 */
 	struct sip_txsoft sc_txsoft[SIP_TXQUEUELEN];
 	struct sip_rxsoft sc_rxsoft[MAX_SIP_NRXDESC];
 	/*
 	 * Control data structures.
 	 */
 	struct sip_control_data *sc_control_data;
 #define	sc_txdescs	sc_control_data->scd_txdescs
 #define	sc_rxdescs	sc_control_data->scd_rxdescs
 #ifdef SIP_EVENT_COUNTERS
 	/*
 	 * Event counters.
 	 */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txforceintr;	/* Tx interrupts forced */
 	struct evcnt sc_ev_txdintr;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txiintr;	/* Tx idle interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_hiberr;	/* HIBERR interrupts */
 	struct evcnt sc_ev_rxpause;	/* PAUSE received */
 	/* DP83820 only */
 	struct evcnt sc_ev_txpause;	/* PAUSE transmitted */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtcpsum;	/* TCP checksums checked in-bound */
 	struct evcnt sc_ev_rxudpsum;	/* UDP checksums checked in-boudn */
 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
 	struct evcnt sc_ev_txtcpsum;	/* TCP checksums comp. out-bound */
 	struct evcnt sc_ev_txudpsum;	/* UDP checksums comp. out-bound */
 #endif /* SIP_EVENT_COUNTERS */
 	u_int32_t sc_txcfg;		/* prototype TXCFG register */
 	u_int32_t sc_rxcfg;		/* prototype RXCFG register */
 	u_int32_t sc_imr;		/* prototype IMR register */
 	u_int32_t sc_rfcr;		/* prototype RFCR register */
 	u_int32_t sc_cfg;		/* prototype CFG register */
 	u_int32_t sc_gpior;		/* prototype GPIOR register */
 	u_int32_t sc_tx_fill_thresh;	/* transmit fill threshold */
 	u_int32_t sc_tx_drain_thresh;	/* transmit drain threshold */
 	u_int32_t sc_rx_drain_thresh;	/* receive drain threshold */
 	int	sc_flowflags;		/* 802.3x flow control flags */
 	int	sc_rx_flow_thresh;	/* Rx FIFO threshold for flow control */
 	int	sc_paused;		/* paused indication */
 	int	sc_txfree;		/* number of free Tx descriptors */
 	int	sc_txnext;		/* next ready Tx descriptor */
 	int	sc_txwin;		/* Tx descriptors since last intr */
 	struct sip_txsq sc_txfreeq;	/* free Tx descsofts */
 	struct sip_txsq sc_txdirtyq;	/* dirty Tx descsofts */
 	/* values of interface state at last init */
 	struct {
 		/* if_capenable */
 		uint64_t	if_capenable;
 		/* ec_capenable */
 		int		ec_capenable;
 		/* VLAN_ATTACHED */
 		int		is_vlan;
 	}	sc_prev;
 	short	sc_if_flags;
 	int	sc_rxptr;		/* next ready Rx descriptor/descsoft */
 	int	sc_rxdiscard;
 	int	sc_rxlen;
 	struct mbuf *sc_rxhead;
 	struct mbuf *sc_rxtail;
 	struct mbuf **sc_rxtailp;
 	int sc_ntxdesc;
 	int sc_ntxdesc_mask;
 	int sc_nrxdesc_mask;
 	const struct sip_parm {
 		const struct sip_regs {
 			int r_rxcfg;
 			int r_txcfg;
 		} p_regs;
 		const struct sip_bits {
 			uint32_t b_txcfg_mxdma_8;
 			uint32_t b_txcfg_mxdma_16;
 			uint32_t b_txcfg_mxdma_32;
 			uint32_t b_txcfg_mxdma_64;
 			uint32_t b_txcfg_mxdma_128;
 			uint32_t b_txcfg_mxdma_256;
 			uint32_t b_txcfg_mxdma_512;
 			uint32_t b_txcfg_flth_mask;
 			uint32_t b_txcfg_drth_mask;
 			uint32_t b_rxcfg_mxdma_8;
 			uint32_t b_rxcfg_mxdma_16;
 			uint32_t b_rxcfg_mxdma_32;
 			uint32_t b_rxcfg_mxdma_64;
 			uint32_t b_rxcfg_mxdma_128;
 			uint32_t b_rxcfg_mxdma_256;
 			uint32_t b_rxcfg_mxdma_512;
 			uint32_t b_isr_txrcmp;
 			uint32_t b_isr_rxrcmp;
 			uint32_t b_isr_dperr;
 			uint32_t b_isr_sserr;
 			uint32_t b_isr_rmabt;
 			uint32_t b_isr_rtabt;
 			uint32_t b_cmdsts_size_mask;
 		} p_bits;
 		int		p_filtmem;
 		int		p_rxbuf_len;
 		bus_size_t	p_tx_dmamap_size;
 		int		p_ntxsegs;
 		int		p_ntxsegs_alloc;
 		int		p_nrxdesc;
 	} *sc_parm;
 	void (*sc_rxintr)(struct sip_softc *);
 	krndsource_t rnd_source;	/* random source */
 };
 #define	sc_bits	sc_parm->p_bits
 #define	sc_regs	sc_parm->p_regs
 static const struct sip_parm sip_parm = {
 	  .p_filtmem = OTHER_RFCR_NS_RFADDR_FILTMEM
 	, .p_rxbuf_len = MCLBYTES - 1	/* field width */
 	, .p_tx_dmamap_size = MCLBYTES
 	, .p_ntxsegs = 16
 	, .p_ntxsegs_alloc = SIP_NTXSEGS_ALLOC
 	, .p_nrxdesc = SIP_NRXDESC
 	, .p_bits = {
 		  .b_txcfg_mxdma_8	= 0x00200000	/*       8 bytes */
 		, .b_txcfg_mxdma_16	= 0x00300000	/*      16 bytes */
 		, .b_txcfg_mxdma_32	= 0x00400000	/*      32 bytes */
 		, .b_txcfg_mxdma_64	= 0x00500000	/*      64 bytes */
 		, .b_txcfg_mxdma_128	= 0x00600000	/*     128 bytes */
 		, .b_txcfg_mxdma_256	= 0x00700000	/*     256 bytes */
 		, .b_txcfg_mxdma_512	= 0x00000000	/*     512 bytes */
 		, .b_txcfg_flth_mask	= 0x00003f00	/* Tx fill threshold */
 		, .b_txcfg_drth_mask	= 0x0000003f	/* Tx drain threshold */
 		, .b_rxcfg_mxdma_8	= 0x00200000	/*       8 bytes */
 		, .b_rxcfg_mxdma_16	= 0x00300000	/*      16 bytes */
 		, .b_rxcfg_mxdma_32	= 0x00400000	/*      32 bytes */
 		, .b_rxcfg_mxdma_64	= 0x00500000	/*      64 bytes */
 		, .b_rxcfg_mxdma_128	= 0x00600000	/*     128 bytes */
 		, .b_rxcfg_mxdma_256	= 0x00700000	/*     256 bytes */
 		, .b_rxcfg_mxdma_512	= 0x00000000	/*     512 bytes */
 		, .b_isr_txrcmp	= 0x02000000	/* transmit reset complete */
 		, .b_isr_rxrcmp	= 0x01000000	/* receive reset complete */
 		, .b_isr_dperr	= 0x00800000	/* detected parity error */
 		, .b_isr_sserr	= 0x00400000	/* signalled system error */
 		, .b_isr_rmabt	= 0x00200000	/* received master abort */
 		, .b_isr_rtabt	= 0x00100000	/* received target abort */
 		, .b_cmdsts_size_mask = OTHER_CMDSTS_SIZE_MASK
+	}
 	, .p_regs = {
 		.r_rxcfg = OTHER_SIP_RXCFG,
 		.r_txcfg = OTHER_SIP_TXCFG
+	}
 }, gsip_parm = {
 	  .p_filtmem = DP83820_RFCR_NS_RFADDR_FILTMEM
 	, .p_rxbuf_len = MCLBYTES - 8
 	, .p_tx_dmamap_size = ETHER_MAX_LEN_JUMBO
 	, .p_ntxsegs = 64
 	, .p_ntxsegs_alloc = GSIP_NTXSEGS_ALLOC
 	, .p_nrxdesc = GSIP_NRXDESC
 	, .p_bits = {
 		  .b_txcfg_mxdma_8	= 0x00100000	/*       8 bytes */
 		, .b_txcfg_mxdma_16	= 0x00200000	/*      16 bytes */
 		, .b_txcfg_mxdma_32	= 0x00300000	/*      32 bytes */
 		, .b_txcfg_mxdma_64	= 0x00400000	/*      64 bytes */
 		, .b_txcfg_mxdma_128	= 0x00500000	/*     128 bytes */
 		, .b_txcfg_mxdma_256	= 0x00600000	/*     256 bytes */
 		, .b_txcfg_mxdma_512	= 0x00700000	/*     512 bytes */
 		, .b_txcfg_flth_mask	= 0x0000ff00	/* Fx fill threshold */
 		, .b_txcfg_drth_mask	= 0x000000ff	/* Tx drain threshold */
 		, .b_rxcfg_mxdma_8	= 0x00100000	/*       8 bytes */
 		, .b_rxcfg_mxdma_16	= 0x00200000	/*      16 bytes */
 		, .b_rxcfg_mxdma_32	= 0x00300000	/*      32 bytes */
 		, .b_rxcfg_mxdma_64	= 0x00400000	/*      64 bytes */
 		, .b_rxcfg_mxdma_128	= 0x00500000	/*     128 bytes */
 		, .b_rxcfg_mxdma_256	= 0x00600000	/*     256 bytes */
 		, .b_rxcfg_mxdma_512	= 0x00700000	/*     512 bytes */
 		, .b_isr_txrcmp	= 0x00400000	/* transmit reset complete */
 		, .b_isr_rxrcmp	= 0x00200000	/* receive reset complete */
 		, .b_isr_dperr	= 0x00100000	/* detected parity error */
 		, .b_isr_sserr	= 0x00080000	/* signalled system error */
 		, .b_isr_rmabt	= 0x00040000	/* received master abort */
 		, .b_isr_rtabt	= 0x00020000	/* received target abort */
 		, .b_cmdsts_size_mask = DP83820_CMDSTS_SIZE_MASK
+	}
 	, .p_regs = {
 		.r_rxcfg = DP83820_SIP_RXCFG,
 		.r_txcfg = DP83820_SIP_TXCFG
+	}
 };
 static inline int
 sip_nexttx(const struct sip_softc *sc, int x)
+{
 	return (x + 1) & sc->sc_ntxdesc_mask;
+}
 static inline int
 sip_nextrx(const struct sip_softc *sc, int x)
+{
 	return (x + 1) & sc->sc_nrxdesc_mask;
+}
 /* 83820 only */
 static inline void
 sip_rxchain_reset(struct sip_softc *sc)
+{
 	sc->sc_rxtailp = &sc->sc_rxhead;
 	*sc->sc_rxtailp = NULL;
 	sc->sc_rxlen = 0;
+}
 /* 83820 only */
 static inline void
 sip_rxchain_link(struct sip_softc *sc, struct mbuf *m)
+{
 	*sc->sc_rxtailp = sc->sc_rxtail = m;
 	sc->sc_rxtailp = &m->m_next;
+}
 #ifdef SIP_EVENT_COUNTERS
 #define	SIP_EVCNT_INCR(ev)	(ev)->ev_count++
 #else
 #define	SIP_EVCNT_INCR(ev)	/* nothing */
 #endif
 #define	SIP_CDTXADDR(sc, x)	((sc)->sc_cddma + SIP_CDTXOFF((x)))
 #define	SIP_CDRXADDR(sc, x)	((sc)->sc_cddma + SIP_CDRXOFF((x)))
 static inline void
 sip_cdtxsync(struct sip_softc *sc, const int x0, const int n0, const int ops)
+{
 	int x, n;
 	x = x0;
 	n = n0;
 	/* If it will wrap around, sync to the end of the ring. */
 	if (x + n > sc->sc_ntxdesc) {
 		bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
 		    SIP_CDTXOFF(x), sizeof(struct sip_desc) *
 		    (sc->sc_ntxdesc - x), ops);
 		n -= (sc->sc_ntxdesc - x);
 		x = 0;
+	}
 	/* Now sync whatever is left. */
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
 	    SIP_CDTXOFF(x), sizeof(struct sip_desc) * n, ops);
+}
 static inline void
 sip_cdrxsync(struct sip_softc *sc, int x, int ops)
+{
 	bus_dmamap_sync(sc->sc_dmat, sc->sc_cddmamap,
 	    SIP_CDRXOFF(x), sizeof(struct sip_desc), ops);
+}
 #if 0
 #ifdef DP83820
 	u_int32_t	sipd_bufptr;	/* pointer to DMA segment */
 	u_int32_t	sipd_cmdsts;	/* command/status word */
 #else
 	u_int32_t	sipd_cmdsts;	/* command/status word */
 	u_int32_t	sipd_bufptr;	/* pointer to DMA segment */
 #endif /* DP83820 */
 #endif /* 0 */
 static inline volatile uint32_t *
 sipd_cmdsts(struct sip_softc *sc, struct sip_desc *sipd)
+{
 	return &sipd->sipd_cbs[(sc->sc_gigabit) ? 1 : 0];
+}
 static inline volatile uint32_t *
 sipd_bufptr(struct sip_softc *sc, struct sip_desc *sipd)
+{
 	return &sipd->sipd_cbs[(sc->sc_gigabit) ? 0 : 1];
+}
 static inline void
 sip_init_rxdesc(struct sip_softc *sc, int x)
+{
 	struct sip_rxsoft *rxs = &sc->sc_rxsoft[x];
 	struct sip_desc *sipd = &sc->sc_rxdescs[x];
 	sipd->sipd_link = htole32(SIP_CDRXADDR(sc, sip_nextrx(sc, x)));
 	*sipd_bufptr(sc, sipd) = htole32(rxs->rxs_dmamap->dm_segs[0].ds_addr);
 	*sipd_cmdsts(sc, sipd) = htole32(CMDSTS_INTR |
 	    (sc->sc_parm->p_rxbuf_len & sc->sc_bits.b_cmdsts_size_mask));
 	sipd->sipd_extsts = 0;
 	sip_cdrxsync(sc, x, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+}
 #define	SIP_CHIP_VERS(sc, v, p, r)					\
 	((sc)->sc_model->sip_vendor == (v) &&				\
 	 (sc)->sc_model->sip_product == (p) &&				\
 	 (sc)->sc_rev == (r))
 #define	SIP_CHIP_MODEL(sc, v, p)					\
 	((sc)->sc_model->sip_vendor == (v) &&				\
 	 (sc)->sc_model->sip_product == (p))
 #define	SIP_SIS900_REV(sc, rev)						\
 	SIP_CHIP_VERS((sc), PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, (rev))
 #define SIP_TIMEOUT 1000
 static int	sip_ifflags_cb(struct ethercom *);
 static void	sipcom_start(struct ifnet *);
 static void	sipcom_watchdog(struct ifnet *);
 static int	sipcom_ioctl(struct ifnet *, u_long, void *);
 static int	sipcom_init(struct ifnet *);
 static void	sipcom_stop(struct ifnet *, int);
 static bool	sipcom_reset(struct sip_softc *);
 static void	sipcom_rxdrain(struct sip_softc *);
 static int	sipcom_add_rxbuf(struct sip_softc *, int);
 static void	sipcom_read_eeprom(struct sip_softc *, int, int,
 				      u_int16_t *);
 static void	sipcom_tick(void *);
 static void	sipcom_sis900_set_filter(struct sip_softc *);
 static void	sipcom_dp83815_set_filter(struct sip_softc *);
 static void	sipcom_dp83820_read_macaddr(struct sip_softc *,
 		    const struct pci_attach_args *, u_int8_t *);
 static void	sipcom_sis900_eeprom_delay(struct sip_softc *sc);
 static void	sipcom_sis900_read_macaddr(struct sip_softc *,
 		    const struct pci_attach_args *, u_int8_t *);
 static void	sipcom_dp83815_read_macaddr(struct sip_softc *,
 		    const struct pci_attach_args *, u_int8_t *);
 static int	sipcom_intr(void *);
 static void	sipcom_txintr(struct sip_softc *);
 static void	sip_rxintr(struct sip_softc *);
 static void	gsip_rxintr(struct sip_softc *);
 static int	sipcom_dp83820_mii_readreg(device_t, int, int);
 static void	sipcom_dp83820_mii_writereg(device_t, int, int, int);
 static void	sipcom_dp83820_mii_statchg(struct ifnet *);
 static int	sipcom_sis900_mii_readreg(device_t, int, int);
 static void	sipcom_sis900_mii_writereg(device_t, int, int, int);
 static void	sipcom_sis900_mii_statchg(struct ifnet *);
 static int	sipcom_dp83815_mii_readreg(device_t, int, int);
 static void	sipcom_dp83815_mii_writereg(device_t, int, int, int);
 static void	sipcom_dp83815_mii_statchg(struct ifnet *);
 static void	sipcom_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	sipcom_match(device_t, cfdata_t, void *);
 static void	sipcom_attach(device_t, device_t, void *);
 static void	sipcom_do_detach(device_t, enum sip_attach_stage);
 static int	sipcom_detach(device_t, int);
 static bool	sipcom_resume(device_t, const pmf_qual_t *);
 static bool	sipcom_suspend(device_t, const pmf_qual_t *);
 int	gsip_copy_small = 0;
 int	sip_copy_small = 0;
 CFATTACH_DECL3_NEW(gsip, sizeof(struct sip_softc),
     sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL,
     DVF_DETACH_SHUTDOWN);
 CFATTACH_DECL3_NEW(sip, sizeof(struct sip_softc),
     sipcom_match, sipcom_attach, sipcom_detach, NULL, NULL, NULL,
     DVF_DETACH_SHUTDOWN);
 /*
  * Descriptions of the variants of the SiS900.
  */
 struct sip_variant {
 	int	(*sipv_mii_readreg)(device_t, int, int);
 	void	(*sipv_mii_writereg)(device_t, int, int, int);
 	void	(*sipv_mii_statchg)(struct ifnet *);
 	void	(*sipv_set_filter)(struct sip_softc *);
 	void	(*sipv_read_macaddr)(struct sip_softc *,
 		    const struct pci_attach_args *, u_int8_t *);
 };
 static u_int32_t sipcom_mii_bitbang_read(device_t);
 static void	sipcom_mii_bitbang_write(device_t, u_int32_t);
 static const struct mii_bitbang_ops sipcom_mii_bitbang_ops = {
 	sipcom_mii_bitbang_read,
 	sipcom_mii_bitbang_write,
+	{
 		EROMAR_MDIO,		/* MII_BIT_MDO */
 		EROMAR_MDIO,		/* MII_BIT_MDI */
 		EROMAR_MDC,		/* MII_BIT_MDC */
 		EROMAR_MDDIR,		/* MII_BIT_DIR_HOST_PHY */
 ,			/* MII_BIT_DIR_PHY_HOST */
+	}
 };
 static const struct sip_variant sipcom_variant_dp83820 = {
 	sipcom_dp83820_mii_readreg,
 	sipcom_dp83820_mii_writereg,
 	sipcom_dp83820_mii_statchg,
 	sipcom_dp83815_set_filter,
 	sipcom_dp83820_read_macaddr,
 };
 static const struct sip_variant sipcom_variant_sis900 = {
 	sipcom_sis900_mii_readreg,
 	sipcom_sis900_mii_writereg,
 	sipcom_sis900_mii_statchg,
 	sipcom_sis900_set_filter,
 	sipcom_sis900_read_macaddr,
 };
 static const struct sip_variant sipcom_variant_dp83815 = {
 	sipcom_dp83815_mii_readreg,
 	sipcom_dp83815_mii_writereg,
 	sipcom_dp83815_mii_statchg,
 	sipcom_dp83815_set_filter,
 	sipcom_dp83815_read_macaddr,
 };
 /*
  * Devices supported by this driver.
  */
 static const struct sip_product {
 	pci_vendor_id_t		sip_vendor;
 	pci_product_id_t	sip_product;
 	const char		*sip_name;
 	const struct sip_variant *sip_variant;
 	int			sip_gigabit;
 } sipcom_products[] = {
 	{ PCI_VENDOR_NS,	PCI_PRODUCT_NS_DP83820,
 	  "NatSemi DP83820 Gigabit Ethernet",
 	  &sipcom_variant_dp83820, 1 },
 	{ PCI_VENDOR_SIS,	PCI_PRODUCT_SIS_900,
 	  "SiS 900 10/100 Ethernet",
 	  &sipcom_variant_sis900, 0 },
 	{ PCI_VENDOR_SIS,	PCI_PRODUCT_SIS_7016,
 	  "SiS 7016 10/100 Ethernet",
 	  &sipcom_variant_sis900, 0 },
 	{ PCI_VENDOR_NS,	PCI_PRODUCT_NS_DP83815,
 	  "NatSemi DP83815 10/100 Ethernet",
 	  &sipcom_variant_dp83815, 0 },
 	{ 0,			0,
 	  NULL,
 	  NULL, 0 },
 };
 static const struct sip_product *
 sipcom_lookup(const struct pci_attach_args *pa, bool gigabit)
+{
 	const struct sip_product *sip;
 	for (sip = sipcom_products; sip->sip_name != NULL; sip++) {
 		if (PCI_VENDOR(pa->pa_id) == sip->sip_vendor &&
 		    PCI_PRODUCT(pa->pa_id) == sip->sip_product &&
 		    sip->sip_gigabit == gigabit)
 			return sip;
+	}
 	return NULL;
+}
 /*
  * I really hate stupid hardware vendors.  There's a bit in the EEPROM
  * which indicates if the card can do 64-bit data transfers.  Unfortunately,
  * several vendors of 32-bit cards fail to clear this bit in the EEPROM,
  * which means we try to use 64-bit data transfers on those cards if we
  * happen to be plugged into a 32-bit slot.
+ *
  * What we do is use this table of cards known to be 64-bit cards.  If
  * you have a 64-bit card who's subsystem ID is not listed in this table,
  * send the output of "pcictl dump ..." of the device to me so that your
  * card will use the 64-bit data path when plugged into a 64-bit slot.
+ *
  *	-- Jason R. Thorpe <thorpej@NetBSD.org>
  *	   June 30, 2002
  */
 static int
 sipcom_check_64bit(const struct pci_attach_args *pa)
+{
 	static const struct {
 		pci_vendor_id_t c64_vendor;
 		pci_product_id_t c64_product;
 	} card64[] = {
 		/* Asante GigaNIX */
 		{ 0x128a,	0x0002 },
 		/* Accton EN1407-T, Planex GN-1000TE */
 		{ 0x1113,	0x1407 },
-		/* Netgear GA-621 */
+		/* Netgear GA621 */
 		{ 0x1385,	0x621a },
-		/* SMC EZ Card */
+		/* Netgear GA622 */
 		{ 0x1385,	0x622a },
 		/* SMC EZ Card 1000 (9462TX) */
 		{ 0x10b8,	0x9462 },
 		{ 0, 0}
 	};
 	pcireg_t subsys;
 	int i;
 	subsys = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
 	for (i = 0; card64[i].c64_vendor != 0; i++) {
 		if (PCI_VENDOR(subsys) == card64[i].c64_vendor &&
 		    PCI_PRODUCT(subsys) == card64[i].c64_product)
 			return (1);
+	}
 	return (0);
+}
 static int
 sipcom_match(device_t parent, cfdata_t cf, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	if (sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0) != NULL)
 		return 1;
 	return 0;
+}
 static void
 sipcom_dp83820_attach(struct sip_softc *sc, struct pci_attach_args *pa)
+{
 	u_int32_t reg;
 	int i;
 	/*
 	 * Cause the chip to load configuration data from the EEPROM.
 	 */
 	bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_PTSCR, PTSCR_EELOAD_EN);
 	for (i = 0; i < 10000; i++) {
 		delay(10);
 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
 		    PTSCR_EELOAD_EN) == 0)
 			break;
+	}
 	if (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_PTSCR) &
 	    PTSCR_EELOAD_EN) {
 		printf("%s: timeout loading configuration from EEPROM\n",
 		    device_xname(sc->sc_dev));
 		return;
+	}
 	sc->sc_gpior = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_GPIOR);
 	reg = bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG);
 	if (reg & CFG_PCI64_DET) {
 		printf("%s: 64-bit PCI slot detected", device_xname(sc->sc_dev));
 		/*
 		 * Check to see if this card is 64-bit.  If so, enable 64-bit
 		 * data transfers.
+		 *
 		 * We can't use the DATA64_EN bit in the EEPROM, because
 		 * vendors of 32-bit cards fail to clear that bit in many
 		 * cases (yet the card still detects that it's in a 64-bit
 		 * slot; go figure).
 		 */
 		if (sipcom_check_64bit(pa)) {
 			sc->sc_cfg |= CFG_DATA64_EN;
 			printf(", using 64-bit data transfers");
+		}
 		printf("\n");
+	}
 	/*
 	 * XXX Need some PCI flags indicating support for
 	 * XXX 64-bit addressing.
 	 */
 #if 0
 	if (reg & CFG_M64ADDR)
 		sc->sc_cfg |= CFG_M64ADDR;
 	if (reg & CFG_T64ADDR)
 		sc->sc_cfg |= CFG_T64ADDR;
 #endif
 	if (reg & (CFG_TBI_EN|CFG_EXT_125)) {
 		const char *sep = "";
 		printf("%s: using ", device_xname(sc->sc_dev));
 		if (reg & CFG_EXT_125) {
 			sc->sc_cfg |= CFG_EXT_125;
 			printf("%s125MHz clock", sep);
 			sep = ", ";
+		}
 		if (reg & CFG_TBI_EN) {
 			sc->sc_cfg |= CFG_TBI_EN;
 			printf("%sten-bit interface", sep);
 			sep = ", ";
+		}
 		printf("\n");
+	}
 	if ((pa->pa_flags & PCI_FLAGS_MRM_OKAY) == 0 ||
 	    (reg & CFG_MRM_DIS) != 0)
 		sc->sc_cfg |= CFG_MRM_DIS;
 	if ((pa->pa_flags & PCI_FLAGS_MWI_OKAY) == 0 ||
 	    (reg & CFG_MWI_DIS) != 0)
 		sc->sc_cfg |= CFG_MWI_DIS;
 	/*
 	 * Use the extended descriptor format on the DP83820.  This
 	 * gives us an interface to VLAN tagging and IPv4/TCP/UDP
 	 * checksumming.
 	 */
 	sc->sc_cfg |= CFG_EXTSTS_EN;
+}
 static int
 sipcom_detach(device_t self, int flags)
+{
 	int s;
 	s = splnet();
 	sipcom_do_detach(self, SIP_ATTACH_FIN);
 	splx(s);
 	return 0;
+}
 static void
 sipcom_do_detach(device_t self, enum sip_attach_stage stage)
+{
 	int i;
 	struct sip_softc *sc = device_private(self);
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	/*
 	 * Free any resources we've allocated during attach.
 	 * Do this in reverse order and fall through.
 	 */
 	switch (stage) {
 	case SIP_ATTACH_FIN:
 		sipcom_stop(ifp, 1);
 		pmf_device_deregister(self);
 #ifdef SIP_EVENT_COUNTERS
 		/*
 		 * Attach event counters.
 		 */
 		evcnt_detach(&sc->sc_ev_txforceintr);
 		evcnt_detach(&sc->sc_ev_txdstall);
 		evcnt_detach(&sc->sc_ev_txsstall);
 		evcnt_detach(&sc->sc_ev_hiberr);
 		evcnt_detach(&sc->sc_ev_rxintr);
 		evcnt_detach(&sc->sc_ev_txiintr);
 		evcnt_detach(&sc->sc_ev_txdintr);
 		if (!sc->sc_gigabit) {
 			evcnt_detach(&sc->sc_ev_rxpause);
 		} else {
 			evcnt_detach(&sc->sc_ev_txudpsum);
 			evcnt_detach(&sc->sc_ev_txtcpsum);
 			evcnt_detach(&sc->sc_ev_txipsum);
 			evcnt_detach(&sc->sc_ev_rxudpsum);
 			evcnt_detach(&sc->sc_ev_rxtcpsum);
 			evcnt_detach(&sc->sc_ev_rxipsum);
 			evcnt_detach(&sc->sc_ev_txpause);
 			evcnt_detach(&sc->sc_ev_rxpause);
+		}
 #endif /* SIP_EVENT_COUNTERS */
 		rnd_detach_source(&sc->rnd_source);
 		ether_ifdetach(ifp);
 		if_detach(ifp);
 		mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_CREATE_RXMAP:
 		for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
 			if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
 				bus_dmamap_destroy(sc->sc_dmat,
 				    sc->sc_rxsoft[i].rxs_dmamap);
+		}
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_CREATE_TXMAP:
 		for (i = 0; i < SIP_TXQUEUELEN; i++) {
 			if (sc->sc_txsoft[i].txs_dmamap != NULL)
 				bus_dmamap_destroy(sc->sc_dmat,
 				    sc->sc_txsoft[i].txs_dmamap);
+		}
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_LOAD_MAP:
 		bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_CREATE_MAP:
 		bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_MAP_MEM:
 		bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
 		    sizeof(struct sip_control_data));
 		/*FALLTHROUGH*/
 	case SIP_ATTACH_ALLOC_MEM:
 		bus_dmamem_free(sc->sc_dmat, &sc->sc_seg, 1);
 		/* FALLTHROUGH*/
 	case SIP_ATTACH_INTR:
 		pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
 		/* FALLTHROUGH*/
 	case SIP_ATTACH_MAP:
 		bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_sz);
 		break;
 	default:
 		break;
+	}
 	return;
+}
 static bool
 sipcom_resume(device_t self, const pmf_qual_t *qual)
+{
 	struct sip_softc *sc = device_private(self);
 	return sipcom_reset(sc);
+}
 static bool
 sipcom_suspend(device_t self, const pmf_qual_t *qual)
+{
 	struct sip_softc *sc = device_private(self);
 	sipcom_rxdrain(sc);
 	return true;
+}
 static void
 sipcom_attach(device_t parent, device_t self, void *aux)
+{
 	struct sip_softc *sc = device_private(self);
 	struct pci_attach_args *pa = aux;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	pci_intr_handle_t ih;
 	const char *intrstr = NULL;
 	bus_space_tag_t iot, memt;
 	bus_space_handle_t ioh, memh;
 	bus_size_t iosz, memsz;
 	int ioh_valid, memh_valid;
 	int i, rseg, error;
 	const struct sip_product *sip;
 	u_int8_t enaddr[ETHER_ADDR_LEN];
 	pcireg_t csr;
 	pcireg_t memtype;
 	bus_size_t tx_dmamap_size;
 	int ntxsegs_alloc;
 	cfdata_t cf = device_cfdata(self);
 	callout_init(&sc->sc_tick_ch, 0);
 	sip = sipcom_lookup(pa, strcmp(cf->cf_name, "gsip") == 0);
 	if (sip == NULL) {
 		printf("\n");
 		panic("%s: impossible", __func__);
+	}
 	sc->sc_dev = self;
 	sc->sc_gigabit = sip->sip_gigabit;
 	pmf_self_suspensor_init(self, &sc->sc_suspensor, &sc->sc_qual);
 	sc->sc_pc = pc;
 	if (sc->sc_gigabit) {
 		sc->sc_rxintr = gsip_rxintr;
 		sc->sc_parm = &gsip_parm;
 	} else {
 		sc->sc_rxintr = sip_rxintr;
 		sc->sc_parm = &sip_parm;
+	}
 	tx_dmamap_size = sc->sc_parm->p_tx_dmamap_size;
 	ntxsegs_alloc = sc->sc_parm->p_ntxsegs_alloc;
 	sc->sc_ntxdesc = SIP_TXQUEUELEN * ntxsegs_alloc;
 	sc->sc_ntxdesc_mask = sc->sc_ntxdesc - 1;
 	sc->sc_nrxdesc_mask = sc->sc_parm->p_nrxdesc - 1;
 	sc->sc_rev = PCI_REVISION(pa->pa_class);
 	printf(": %s, rev %#02x\n", sip->sip_name, sc->sc_rev);
 	sc->sc_model = sip;
 	/*
 	 * XXX Work-around broken PXE firmware on some boards.
+	 *
 	 * The DP83815 shares an address decoder with the MEM BAR
 	 * and the ROM BAR.  Make sure the ROM BAR is disabled,
 	 * so that memory mapped access works.
 	 */
 	pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
 	    pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) &
 	    ~PCI_MAPREG_ROM_ENABLE);
 	/*
 	 * Map the device.
 	 */
 	ioh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGIOA,
 	    PCI_MAPREG_TYPE_IO, 0,
 	    &iot, &ioh, NULL, &iosz) == 0);
 	if (sc->sc_gigabit) {
 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIP_PCI_CFGMA);
 		switch (memtype) {
 		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 		case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 			memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
 			    memtype, 0, &memt, &memh, NULL, &memsz) == 0);
 			break;
 		default:
 			memh_valid = 0;
+		}
 	} else {
 		memh_valid = (pci_mapreg_map(pa, SIP_PCI_CFGMA,
 		    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
 		    &memt, &memh, NULL, &memsz) == 0);
+	}
 	if (memh_valid) {
 		sc->sc_st = memt;
 		sc->sc_sh = memh;
 		sc->sc_sz = memsz;
 	} else if (ioh_valid) {
 		sc->sc_st = iot;
 		sc->sc_sh = ioh;
 		sc->sc_sz = iosz;
 	} else {
 		printf("%s: unable to map device registers\n",
 		    device_xname(sc->sc_dev));
 		return;
+	}
 	sc->sc_dmat = pa->pa_dmat;
 	/*
 	 * Make sure bus mastering is enabled.  Also make sure
 	 * Write/Invalidate is enabled if we're allowed to use it.
 	 */
 	csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
 	if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
 		csr |= PCI_COMMAND_INVALIDATE_ENABLE;
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
 	    csr | PCI_COMMAND_MASTER_ENABLE);
 	/* power up chip */
 	error = pci_activate(pa->pa_pc, pa->pa_tag, self, pci_activate_null);
 	if (error != 0 && error != EOPNOTSUPP) {
 		aprint_error_dev(sc->sc_dev, "cannot activate %d\n", error);
 		return;
+	}
 	/*
 	 * Map and establish our interrupt.
 	 */
 	if (pci_intr_map(pa, &ih)) {
 		aprint_error_dev(sc->sc_dev, "unable to map interrupt\n");
 		return;
+	}
 	intrstr = pci_intr_string(pc, ih);
 	sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sipcom_intr, sc);
 	if (sc->sc_ih == NULL) {
 		aprint_error_dev(sc->sc_dev, "unable to establish interrupt");
 		if (intrstr != NULL)
 			aprint_error(" at %s", intrstr);
 		aprint_error("\n");
 		sipcom_do_detach(self, SIP_ATTACH_MAP);
 		return;
+	}
 	aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
 	SIMPLEQ_INIT(&sc->sc_txfreeq);
 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
 	/*
 	 * Allocate the control data structures, and create and load the
 	 * DMA map for it.
 	 */
 	if ((error = bus_dmamem_alloc(sc->sc_dmat,
 	    sizeof(struct sip_control_data), PAGE_SIZE, 0, &sc->sc_seg, 1,
 	    &rseg, 0)) != 0) {
 		aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n",
 		    error);
 		sipcom_do_detach(self, SIP_ATTACH_INTR);
 		return;
+	}
 	if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, rseg,
 	    sizeof(struct sip_control_data), (void **)&sc->sc_control_data,
 	    BUS_DMA_COHERENT)) != 0) {
 		aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n",
 		    error);
 		sipcom_do_detach(self, SIP_ATTACH_ALLOC_MEM);
+	}
 	if ((error = bus_dmamap_create(sc->sc_dmat,
 	    sizeof(struct sip_control_data), 1,
 	    sizeof(struct sip_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
 		aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
 		    "error = %d\n", error);
 		sipcom_do_detach(self, SIP_ATTACH_MAP_MEM);
+	}
 	if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
 	    sc->sc_control_data, sizeof(struct sip_control_data), NULL,
 )) != 0) {
 		aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, error = %d\n",
 		    error);
 		sipcom_do_detach(self, SIP_ATTACH_CREATE_MAP);
+	}
 	/*
 	 * Create the transmit buffer DMA maps.
 	 */
 	for (i = 0; i < SIP_TXQUEUELEN; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, tx_dmamap_size,
 		    sc->sc_parm->p_ntxsegs, MCLBYTES, 0, 0,
 		    &sc->sc_txsoft[i].txs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev, "unable to create tx DMA map %d, "
 			    "error = %d\n", i, error);
 			sipcom_do_detach(self, SIP_ATTACH_CREATE_TXMAP);
+		}
+	}
 	/*
 	 * Create the receive buffer DMA maps.
 	 */
 	for (i = 0; i < sc->sc_parm->p_nrxdesc; i++) {
 		if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
 			aprint_error_dev(sc->sc_dev, "unable to create rx DMA map %d, "
 			    "error = %d\n", i, error);
 			sipcom_do_detach(self, SIP_ATTACH_CREATE_RXMAP);
+		}
 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
+	}
 	/*
 	 * Reset the chip to a known state.
 	 */
 	sipcom_reset(sc);
 	/*
 	 * Read the Ethernet address from the EEPROM.  This might
 	 * also fetch other stuff from the EEPROM and stash it
 	 * in the softc.
 	 */
 	sc->sc_cfg = 0;
 	if (!sc->sc_gigabit) {
 		if (SIP_SIS900_REV(sc,SIS_REV_635) ||
 		    SIP_SIS900_REV(sc,SIS_REV_900B))
 			sc->sc_cfg |= (CFG_PESEL | CFG_RNDCNT);
 		if (SIP_SIS900_REV(sc,SIS_REV_635) ||
 		    SIP_SIS900_REV(sc,SIS_REV_960) ||
 		    SIP_SIS900_REV(sc,SIS_REV_900B))
 			sc->sc_cfg |=
 			    (bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CFG) &
 			     CFG_EDBMASTEN);
+	}
 	(*sip->sip_variant->sipv_read_macaddr)(sc, pa, enaddr);
 	printf("%s: Ethernet address %s\n", device_xname(sc->sc_dev),
 	    ether_sprintf(enaddr));
 	/*
 	 * Initialize the configuration register: aggressive PCI
 	 * bus request algorithm, default backoff, default OW timer,
 	 * default parity error detection.
+	 *
 	 * NOTE: "Big endian mode" is useless on the SiS900 and
 	 * friends -- it affects packet data, not descriptors.
 	 */
 	if (sc->sc_gigabit)
 		sipcom_dp83820_attach(sc, pa);
 	/*
 	 * Initialize our media structures and probe the MII.
 	 */
 	sc->sc_mii.mii_ifp = ifp;
 	sc->sc_mii.mii_readreg = sip->sip_variant->sipv_mii_readreg;
 	sc->sc_mii.mii_writereg = sip->sip_variant->sipv_mii_writereg;
 	sc->sc_mii.mii_statchg = sip->sip_variant->sipv_mii_statchg;
 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, ether_mediachange,
 	    sipcom_mediastatus);
 	/*
 	 * XXX We cannot handle flow control on the DP83815.
 	 */
 	if (SIP_CHIP_MODEL(sc, PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815))
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 			   MII_OFFSET_ANY, 0);
 	else
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 			   MII_OFFSET_ANY, MIIF_DOPAUSE);
 	if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
 	} else
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
 	ifp = &sc->sc_ethercom.ec_if;
 	strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
 	ifp->if_softc = sc;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	sc->sc_if_flags = ifp->if_flags;
 	ifp->if_ioctl = sipcom_ioctl;
 	ifp->if_start = sipcom_start;
 	ifp->if_watchdog = sipcom_watchdog;
 	ifp->if_init = sipcom_init;
 	ifp->if_stop = sipcom_stop;
 	IFQ_SET_READY(&ifp->if_snd);
 	/*
 	 * We can support 802.1Q VLAN-sized frames.
 	 */
 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
 	if (sc->sc_gigabit) {
 		/*
 		 * And the DP83820 can do VLAN tagging in hardware, and
 		 * support the jumbo Ethernet MTU.
 		 */
 		sc->sc_ethercom.ec_capabilities |=
 		    ETHERCAP_VLAN_HWTAGGING | ETHERCAP_JUMBO_MTU;
 		/*
 		 * The DP83820 can do IPv4, TCPv4, and UDPv4 checksums
 		 * in hardware.
 		 */
 		ifp->if_capabilities |=
 		    IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
 		    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
 		    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx;
+	}
 	/*
 	 * Attach the interface.
 	 */
 	if_attach(ifp);
 	ether_ifattach(ifp, enaddr);
 	ether_set_ifflags_cb(&sc->sc_ethercom, sip_ifflags_cb);
 	sc->sc_prev.ec_capenable = sc->sc_ethercom.ec_capenable;
 	sc->sc_prev.is_vlan = VLAN_ATTACHED(&(sc)->sc_ethercom);
 	sc->sc_prev.if_capenable = ifp->if_capenable;
 	rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
 	    RND_TYPE_NET, 0);
 	/*
 	 * The number of bytes that must be available in
 	 * the Tx FIFO before the bus master can DMA more
 	 * data into the FIFO.
 	 */
 	sc->sc_tx_fill_thresh = 64 / 32;
 	/*
 	 * Start at a drain threshold of 512 bytes.  We will
 	 * increase it if a DMA underrun occurs.
+	 *
 	 * XXX The minimum value of this variable should be
 	 * tuned.  We may be able to improve performance
 	 * by starting with a lower value.  That, however,
 	 * may trash the first few outgoing packets if the
 	 * PCI bus is saturated.
 	 */
 	if (sc->sc_gigabit)
 		sc->sc_tx_drain_thresh = 6400 / 32; /* from FreeBSD nge(4) */
 	else
 		sc->sc_tx_drain_thresh = 1504 / 32;
 	/*
 	 * Initialize the Rx FIFO drain threshold.
+	 *
 	 * This is in units of 8 bytes.
+	 *
 	 * We should never set this value lower than 2; 14 bytes are
 	 * required to filter the packet.
 	 */
 	sc->sc_rx_drain_thresh = 128 / 8;
 #ifdef SIP_EVENT_COUNTERS
 	/*
 	 * Attach event counters.
 	 */
 	evcnt_attach_dynamic(&sc->sc_ev_txsstall, EVCNT_TYPE_MISC,
 	    NULL, device_xname(sc->sc_dev), "txsstall");
 	evcnt_attach_dynamic(&sc->sc_ev_txdstall, EVCNT_TYPE_MISC,
 	    NULL, device_xname(sc->sc_dev), "txdstall");
 	evcnt_attach_dynamic(&sc->sc_ev_txforceintr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(sc->sc_dev), "txforceintr");
 	evcnt_attach_dynamic(&sc->sc_ev_txdintr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(sc->sc_dev), "txdintr");
 	evcnt_attach_dynamic(&sc->sc_ev_txiintr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(sc->sc_dev), "txiintr");
 	evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(sc->sc_dev), "rxintr");
 	evcnt_attach_dynamic(&sc->sc_ev_hiberr, EVCNT_TYPE_INTR,
 	    NULL, device_xname(sc->sc_dev), "hiberr");
 	if (!sc->sc_gigabit) {
 		evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_INTR,
 		    NULL, device_xname(sc->sc_dev), "rxpause");
 	} else {
 		evcnt_attach_dynamic(&sc->sc_ev_rxpause, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "rxpause");
 		evcnt_attach_dynamic(&sc->sc_ev_txpause, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "txpause");
 		evcnt_attach_dynamic(&sc->sc_ev_rxipsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "rxipsum");
 		evcnt_attach_dynamic(&sc->sc_ev_rxtcpsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "rxtcpsum");
 		evcnt_attach_dynamic(&sc->sc_ev_rxudpsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "rxudpsum");
 		evcnt_attach_dynamic(&sc->sc_ev_txipsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "txipsum");
 		evcnt_attach_dynamic(&sc->sc_ev_txtcpsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "txtcpsum");
 		evcnt_attach_dynamic(&sc->sc_ev_txudpsum, EVCNT_TYPE_MISC,
 		    NULL, device_xname(sc->sc_dev), "txudpsum");
+	}
 #endif /* SIP_EVENT_COUNTERS */
 	if (pmf_device_register(self, sipcom_suspend, sipcom_resume))
 		pmf_class_network_register(self, ifp);
 	else
 		aprint_error_dev(self, "couldn't establish power handler\n");
+}
 static inline void
 sipcom_set_extsts(struct sip_softc *sc, int lasttx, struct mbuf *m0,
     uint64_t capenable)
+{
 	struct m_tag *mtag;
 	u_int32_t extsts;
 #ifdef DEBUG
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 #endif
 	/*
 	 * If VLANs are enabled and the packet has a VLAN tag, set
 	 * up the descriptor to encapsulate the packet for us.
+	 *
 	 * This apparently has to be on the last descriptor of
 	 * the packet.
 	 */
 	/*
 	 * Byte swapping is tricky. We need to provide the tag
 	 * in a network byte order. On a big-endian machine,
 	 * the byteorder is correct, but we need to swap it
 	 * anyway, because this will be undone by the outside
 	 * htole32(). That's why there must be an
 	 * unconditional swap instead of htons() inside.
 	 */
 	if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
 		sc->sc_txdescs[lasttx].sipd_extsts |=
 		    htole32(EXTSTS_VPKT |
 				(bswap16(VLAN_TAG_VALUE(mtag)) &
 				 EXTSTS_VTCI));
+	}
 	/*
 	 * If the upper-layer has requested IPv4/TCPv4/UDPv4
 	 * checksumming, set up the descriptor to do this work
 	 * for us.
+	 *
 	 * This apparently has to be on the first descriptor of
 	 * the packet.
+	 *
 	 * Byte-swap constants so the compiler can optimize.
 	 */
 	extsts = 0;
 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
 		KDASSERT(ifp->if_capenable & IFCAP_CSUM_IPv4_Tx);
 		SIP_EVCNT_INCR(&sc->sc_ev_txipsum);
 		extsts |= htole32(EXTSTS_IPPKT);
+	}
 	if (m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
 		KDASSERT(ifp->if_capenable & IFCAP_CSUM_TCPv4_Tx);
 		SIP_EVCNT_INCR(&sc->sc_ev_txtcpsum);
 		extsts |= htole32(EXTSTS_TCPPKT);
 	} else if (m0->m_pkthdr.csum_flags & M_CSUM_UDPv4) {
 		KDASSERT(ifp->if_capenable & IFCAP_CSUM_UDPv4_Tx);
 		SIP_EVCNT_INCR(&sc->sc_ev_txudpsum);
 		extsts |= htole32(EXTSTS_UDPPKT);
+	}
 	sc->sc_txdescs[sc->sc_txnext].sipd_extsts |= extsts;
+}
 /*
  * sip_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface.
  */
 static void
 sipcom_start(struct ifnet *ifp)
+{
 	struct sip_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	struct mbuf *m;
 	struct sip_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, nexttx, lasttx, seg;
 	int ofree = sc->sc_txfree;
 #if 0
 	int firsttx = sc->sc_txnext;
 #endif
 	/*
 	 * If we've been told to pause, don't transmit any more packets.
 	 */
 	if (!sc->sc_gigabit && sc->sc_paused)
 		ifp->if_flags |= IFF_OACTIVE;
 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	for (;;) {
 		/* Get a work queue entry. */
 		if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) {
 			SIP_EVCNT_INCR(&sc->sc_ev_txsstall);
 			break;
+		}
 		/*
 		 * Grab a packet off the queue.
 		 */
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		m = NULL;
 		dmamap = txs->txs_dmamap;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the alloted number of segments, or we
 		 * were short on resources.
 		 */
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 		/* In the non-gigabit case, we'll copy and try again. */
 		if (error != 0 && !sc->sc_gigabit) {
 			MGETHDR(m, M_DONTWAIT, MT_DATA);
 			if (m == NULL) {
 				printf("%s: unable to allocate Tx mbuf\n",
 				    device_xname(sc->sc_dev));
 				break;
+			}
 			MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
 			if (m0->m_pkthdr.len > MHLEN) {
 				MCLGET(m, M_DONTWAIT);
 				if ((m->m_flags & M_EXT) == 0) {
 					printf("%s: unable to allocate Tx "
 					    "cluster\n", device_xname(sc->sc_dev));
 					m_freem(m);
 					break;
+				}
+			}
 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
 			error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 			if (error) {
 				printf("%s: unable to load Tx buffer, "
 				    "error = %d\n", device_xname(sc->sc_dev), error);
 				break;
+			}
 		} else if (error == EFBIG) {
 			/*
 			 * For the too-many-segments case, we simply
 			 * report an error and drop the packet,
 			 * since we can't sanely copy a jumbo packet
 			 * to a single buffer.
 			 */
 			printf("%s: Tx packet consumes too many "
 			    "DMA segments, dropping...\n", device_xname(sc->sc_dev));
 			IFQ_DEQUEUE(&ifp->if_snd, m0);
 			m_freem(m0);
 			continue;
 		} else if (error != 0) {
 			/*
 			 * Short on resources, just stop for now.
 			 */
 			break;
+		}
 		/*
 		 * Ensure we have enough descriptors free to describe
 		 * the packet.  Note, we always reserve one descriptor
 		 * at the end of the ring as a termination point, to
 		 * prevent wrap-around.
 		 */
 		if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed anything yet,
 			 * so just unload the DMA map, put the packet
 			 * back on the queue, and punt.  Notify the upper
 			 * layer that there are not more slots left.
+			 *
 			 * XXX We could allocate an mbuf and copy, but
 			 * XXX is it worth it?
 			 */
 			ifp->if_flags |= IFF_OACTIVE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			if (m != NULL)
 				m_freem(m);
 			SIP_EVCNT_INCR(&sc->sc_ev_txdstall);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		if (m != NULL) {
 			m_freem(m0);
 			m0 = m;
+		}
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Initialize the transmit descriptors.
 		 */
 		for (nexttx = lasttx = sc->sc_txnext, seg = 0;
 		     seg < dmamap->dm_nsegs;
 		     seg++, nexttx = sip_nexttx(sc, nexttx)) {
 			/*
 			 * If this is the first descriptor we're
 			 * enqueueing, don't set the OWN bit just
 			 * yet.  That could cause a race condition.
 			 * We'll do it below.
 			 */
 			*sipd_bufptr(sc, &sc->sc_txdescs[nexttx]) =
 			    htole32(dmamap->dm_segs[seg].ds_addr);
 			*sipd_cmdsts(sc, &sc->sc_txdescs[nexttx]) =
 			    htole32((nexttx == sc->sc_txnext ? 0 : CMDSTS_OWN) |
 			    CMDSTS_MORE | dmamap->dm_segs[seg].ds_len);
 			sc->sc_txdescs[nexttx].sipd_extsts = 0;
 			lasttx = nexttx;
+		}
 		/* Clear the MORE bit on the last segment. */
 		*sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) &=
 		    htole32(~CMDSTS_MORE);
 		/*
 		 * If we're in the interrupt delay window, delay the
 		 * interrupt.
 		 */
 		if (++sc->sc_txwin >= (SIP_TXQUEUELEN * 2 / 3)) {
 			SIP_EVCNT_INCR(&sc->sc_ev_txforceintr);
 			*sipd_cmdsts(sc, &sc->sc_txdescs[lasttx]) |=
 			    htole32(CMDSTS_INTR);
 			sc->sc_txwin = 0;
+		}
 		if (sc->sc_gigabit)
 			sipcom_set_extsts(sc, lasttx, m0, ifp->if_capenable);
 		/* Sync the descriptors we're using. */
 		sip_cdtxsync(sc, sc->sc_txnext, dmamap->dm_nsegs,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/*
 		 * The entire packet is set up.  Give the first descrptor
 		 * to the chip now.
 		 */
 		*sipd_cmdsts(sc, &sc->sc_txdescs[sc->sc_txnext]) |=
 		    htole32(CMDSTS_OWN);
 		sip_cdtxsync(sc, sc->sc_txnext, 1,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/*
 		 * Store a pointer to the packet so we can free it later,
 		 * and remember what txdirty will be once the packet is
 		 * done.
 		 */
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = sc->sc_txnext;
 		txs->txs_lastdesc = lasttx;
 		/* Advance the tx pointer. */
 		sc->sc_txfree -= dmamap->dm_nsegs;
 		sc->sc_txnext = nexttx;
 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
 		/*
 		 * Pass the packet to any BPF listeners.
 		 */
 		bpf_mtap(ifp, m0);
+	}
 	if (txs == NULL || sc->sc_txfree == 0) {
 		/* No more slots left; notify upper layer. */
 		ifp->if_flags |= IFF_OACTIVE;
+	}
 	if (sc->sc_txfree != ofree) {
 		/*
 		 * Start the transmit process.  Note, the manual says
 		 * that if there are no pending transmissions in the
 		 * chip's internal queue (indicated by TXE being clear),
 		 * then the driver software must set the TXDP to the
 		 * first descriptor to be transmitted.  However, if we
 		 * do this, it causes serious performance degredation on
 		 * the DP83820 under load, not setting TXDP doesn't seem
 		 * to adversely affect the SiS 900 or DP83815.
+		 *
 		 * Well, I guess it wouldn't be the first time a manual
 		 * has lied -- and they could be speaking of the NULL-
 		 * terminated descriptor list case, rather than OWN-
 		 * terminated rings.
 		 */
 #if 0
 		if ((bus_space_read_4(sc->sc_st, sc->sc_sh, SIP_CR) &
 		     CR_TXE) == 0) {
 			bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_TXDP,
 			    SIP_CDTXADDR(sc, firsttx));
 			bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
+		}
 #else
 		bus_space_write_4(sc->sc_st, sc->sc_sh, SIP_CR, CR_TXE);
 #endif
 		/* Set a watchdog timer in case the chip flakes out. */
 		/* Gigabit autonegotiation takes 5 seconds. */
 		ifp->if_timer = (sc->sc_gigabit) ? 10 : 5;
+	}
+}
 /*
  * sip_watchdog:	[ifnet interface function]
+ *
  *	Watchdog timer handler.
  */
 static void
 sipcom_watchdog(struct ifnet *ifp)
+{
 	struct sip_softc *sc = ifp->if_softc;
 	/*
 	 * The chip seems to ignore the CMDSTS_INTR bit sometimes!
 	 * If we get a timeout, try and sweep up transmit descriptors.
 	 * If we manage to sweep them all up, ignore the lack of
 	 * interrupt.
 	 */
 	sipcom_txintr(sc);
 	if (sc->sc_txfree != sc->sc_ntxdesc) {
 		printf("%s: device timeout\n", device_xname(sc->sc_dev));
 		ifp->if_oerrors++;
 		/* Reset the interface. */
 		(void) sipcom_init(ifp);
 	} else if (ifp->if_flags & IFF_DEBUG)
 		printf("%s: recovered from device timeout\n",
 		    device_xname(sc->sc_dev));
 	/* Try to get more packets going. */
 	sipcom_start(ifp);
+}
 /* If the interface is up and running, only modify the receive
  * filter when setting promiscuous or debug mode.  Otherwise fall
  * through to ether_ioctl, which will reset the chip.
  */
 static int
 sip_ifflags_cb(struct ethercom *ec)
+{
 #define COMPARE_EC(sc) (((sc)->sc_prev.ec_capenable			\
 			 == (sc)->sc_ethercom.ec_capenable)		\
 			&& ((sc)->sc_prev.is_vlan ==			\
 			    VLAN_ATTACHED(&(sc)->sc_ethercom) ))
 #define COMPARE_IC(sc, ifp) ((sc)->sc_prev.if_capenable == (ifp)->if_capenable)
 	struct ifnet *ifp = &ec->ec_if;
 	struct sip_softc *sc = ifp->if_softc;
 	int change = ifp->if_flags ^ sc->sc_if_flags;
 	if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0 || !COMPARE_EC(sc) ||
 	    !COMPARE_IC(sc, ifp))
 		return ENETRESET;
 	/* Set up the receive filter. */
 	(*sc->sc_model->sip_variant->sipv_set_filter)(sc);
 	return 0;
+}
 /*
  * sip_ioctl:		[ifnet interface function]
+ *

 @@ -1,1707 +1,1714 @@
-/*	$NetBSD: if_tlp_pci.c,v 1.121 2011/11/11 23:01:59 jakllsch Exp $	*/
+/*	$NetBSD: if_tlp_pci.c,v 1.122 2012/09/23 01:10:59 chs Exp $	*/
 /*-
  * Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
  * All rights reserved.
+ *
  * This code is derived from software contributed to The NetBSD Foundation
  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
  * NASA Ames Research Center; and Charles M. Hannum.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*
  * PCI bus front-end for the Digital Semiconductor ``Tulip'' (21x4x)
  * Ethernet controller family driver.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_tlp_pci.c,v 1.121 2011/11/11 23:01:59 jakllsch Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_tlp_pci.c,v 1.122 2012/09/23 01:10:59 chs Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <machine/endian.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/ic/tulipreg.h>
 #include <dev/ic/tulipvar.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcidevs.h>
 /*
  * PCI configuration space registers used by the Tulip.
  */
 #define TULIP_PCI_IOBA PCI_BAR(0)	/* i/o mapped base */
 #define TULIP_PCI_MMBA PCI_BAR(1)	/* memory mapped base */
 #define	TULIP_PCI_CFDA		0x40	/* configuration driver area */
 #define	CFDA_SLEEP		0x80000000	/* sleep mode */
 #define	CFDA_SNOOZE		0x40000000	/* snooze mode */
 struct tulip_pci_softc {
 	struct tulip_softc sc_tulip;	/* real Tulip softc */
 	/* PCI-specific goo. */
 	void	*sc_ih;			/* interrupt handle */
 	bus_size_t sc_mapsize;
 	pci_chipset_tag_t sc_pc;	/* our PCI chipset */
 	pcitag_t sc_pcitag;		/* our PCI tag */
 	int	sc_flags;		/* flags; see below */
 	LIST_HEAD(, tulip_pci_softc) sc_intrslaves;
 	LIST_ENTRY(tulip_pci_softc) sc_intrq;
 	/* Our {ROM,interrupt} master. */
 	struct tulip_pci_softc *sc_master;
 };
 /* sc_flags */
 #define	TULIP_PCI_SHAREDINTR	0x01	/* interrupt is shared */
 #define	TULIP_PCI_SLAVEINTR	0x02	/* interrupt is slave */
 #define	TULIP_PCI_SHAREDROM	0x04	/* ROM is shared */
 #define	TULIP_PCI_SLAVEROM	0x08	/* slave of shared ROM */
 static int	tlp_pci_match(device_t, cfdata_t, void *);
 static void	tlp_pci_attach(device_t, device_t, void *);
 static int	tlp_pci_detach(device_t, int);
 CFATTACH_DECL3_NEW(tlp_pci, sizeof(struct tulip_pci_softc),
     tlp_pci_match, tlp_pci_attach, tlp_pci_detach, NULL, NULL, NULL,
     DVF_DETACH_SHUTDOWN);
 static const struct tulip_pci_product {
 	uint32_t	tpp_vendor;	/* PCI vendor ID */
 	uint32_t	tpp_product;	/* PCI product ID */
 	tulip_chip_t	tpp_chip;	/* base Tulip chip type */
 } tlp_pci_products[] = {
 	{ PCI_VENDOR_DEC,		PCI_PRODUCT_DEC_21040,
 	  TULIP_CHIP_21040 },
 	{ PCI_VENDOR_DEC,		PCI_PRODUCT_DEC_21041,
 	  TULIP_CHIP_21041 },
 	{ PCI_VENDOR_DEC,		PCI_PRODUCT_DEC_21140,
 	  TULIP_CHIP_21140 },
 	{ PCI_VENDOR_DEC,		PCI_PRODUCT_DEC_21142,
 	  TULIP_CHIP_21142 },
 	{ PCI_VENDOR_LITEON,		PCI_PRODUCT_LITEON_82C168,
 	  TULIP_CHIP_82C168 },
 	/*
 	 * Note: This is like a MX98725 with Wake-On-LAN and a
 	 * 128-bit multicast hash table.
 	 */
 	{ PCI_VENDOR_LITEON,		PCI_PRODUCT_LITEON_82C115,
 	  TULIP_CHIP_82C115 },
 	{ PCI_VENDOR_MACRONIX,		PCI_PRODUCT_MACRONIX_MX98713,
 	  TULIP_CHIP_MX98713 },
 	{ PCI_VENDOR_MACRONIX,		PCI_PRODUCT_MACRONIX_MX987x5,
 	  TULIP_CHIP_MX98715 },
 	{ PCI_VENDOR_COMPEX,		PCI_PRODUCT_COMPEX_RL100TX,
 	  TULIP_CHIP_MX98713 },
 	{ PCI_VENDOR_WINBOND,		PCI_PRODUCT_WINBOND_W89C840F,
 	  TULIP_CHIP_WB89C840F },
 	{ PCI_VENDOR_COMPEX,		PCI_PRODUCT_COMPEX_RL100ATX,
 	  TULIP_CHIP_WB89C840F },
 	{ PCI_VENDOR_DAVICOM,		PCI_PRODUCT_DAVICOM_DM9102,
 	  TULIP_CHIP_DM9102 },
 	{ PCI_VENDOR_ADMTEK,		PCI_PRODUCT_ADMTEK_AL981,
 	  TULIP_CHIP_AL981 },
 	{ PCI_VENDOR_ADMTEK,		PCI_PRODUCT_ADMTEK_AN983,
 	  TULIP_CHIP_AN985 },
 	{ PCI_VENDOR_ADMTEK,		PCI_PRODUCT_ADMTEK_ADM9511,
 	  TULIP_CHIP_AN985 },
 	{ PCI_VENDOR_ADMTEK,		PCI_PRODUCT_ADMTEK_ADM9513,
 	  TULIP_CHIP_AN985 },
 	{ PCI_VENDOR_ACCTON,		PCI_PRODUCT_ACCTON_EN2242,
 	  TULIP_CHIP_AN985 },
 	{ PCI_VENDOR_3COM,		PCI_PRODUCT_3COM_3C910SOHOB,
 	  TULIP_CHIP_AN985 },
 	{ PCI_VENDOR_ASIX,		PCI_PRODUCT_ASIX_AX88140A,
 	  TULIP_CHIP_AX88140 },
 	{ PCI_VENDOR_CONEXANT,		PCI_PRODUCT_CONEXANT_LANFINITY,
 	  TULIP_CHIP_RS7112 },
 	{ 0,				0,
 	  TULIP_CHIP_INVALID },
 };
 struct tlp_pci_quirks {
 	void		(*tpq_func)(struct tulip_pci_softc *,
 			    const uint8_t *);
 	uint8_t		tpq_oui[3];
 };
 static void	tlp_pci_dec_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_znyx_21040_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_smc_21040_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_cogent_21040_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_accton_21040_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_cobalt_21142_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_algor_21142_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_netwinder_21142_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_phobos_21142_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_znyx_21142_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_adaptec_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static const struct tlp_pci_quirks tlp_pci_21040_quirks[] = {
 	{ tlp_pci_znyx_21040_quirks,	{ 0x00, 0xc0, 0x95 } },
 	{ tlp_pci_smc_21040_quirks,	{ 0x00, 0x00, 0xc0 } },
 	{ tlp_pci_cogent_21040_quirks,	{ 0x00, 0x00, 0x92 } },
 	{ tlp_pci_accton_21040_quirks,	{ 0x00, 0x00, 0xe8 } },
 	{ NULL,				{ 0, 0, 0 } }
 };
 static const struct tlp_pci_quirks tlp_pci_21041_quirks[] = {
 	{ tlp_pci_dec_quirks,		{ 0x08, 0x00, 0x2b } },
 	{ tlp_pci_dec_quirks,		{ 0x00, 0x00, 0xf8 } },
 	{ NULL,				{ 0, 0, 0 } }
 };
 static void	tlp_pci_asante_21140_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_e100_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_phobos_21140_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_smc_21140_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static void	tlp_pci_vpc_21140_quirks(struct tulip_pci_softc *,
 		    const uint8_t *);
 static const struct tlp_pci_quirks tlp_pci_21140_quirks[] = {
 	{ tlp_pci_dec_quirks,		{ 0x08, 0x00, 0x2b } },
 	{ tlp_pci_dec_quirks,		{ 0x00, 0x00, 0xf8 } },
 	{ tlp_pci_e100_quirks,		{ 0x00, 0xa0, 0x59 } },
 	{ tlp_pci_asante_21140_quirks,	{ 0x00, 0x00, 0x94 } },
 	{ tlp_pci_adaptec_quirks,	{ 0x00, 0x00, 0x92 } },
 	{ tlp_pci_adaptec_quirks,	{ 0x00, 0x00, 0xd1 } },
 	{ tlp_pci_phobos_21140_quirks,	{ 0x00, 0x60, 0xf5 } },
 	{ tlp_pci_smc_21140_quirks,	{ 0x00, 0x00, 0xc0 } },
 	{ tlp_pci_vpc_21140_quirks,	{ 0x00, 0x03, 0xff } },
 	{ NULL,				{ 0, 0, 0 } }
 };
 static const struct tlp_pci_quirks tlp_pci_21142_quirks[] = {
 	{ tlp_pci_dec_quirks,		{ 0x08, 0x00, 0x2b } },
 	{ tlp_pci_dec_quirks,		{ 0x00, 0x00, 0xf8 } },
 	{ tlp_pci_cobalt_21142_quirks,	{ 0x00, 0x10, 0xe0 } },
 	{ tlp_pci_algor_21142_quirks,	{ 0x00, 0x40, 0xbc } },
 	{ tlp_pci_adaptec_quirks,	{ 0x00, 0x00, 0xd1 } },
 	{ tlp_pci_netwinder_21142_quirks,{ 0x00, 0x10, 0x57 } },
 	{ tlp_pci_phobos_21142_quirks,	{ 0x00, 0x60, 0xf5 } },
 	{ tlp_pci_znyx_21142_quirks,	{ 0x00, 0xc0, 0x95 } },
 	{ NULL,				{ 0, 0, 0 } }
 };
 static int	tlp_pci_shared_intr(void *);
 static const struct tulip_pci_product *
 tlp_pci_lookup(const struct pci_attach_args *pa)
+{
 	const struct tulip_pci_product *tpp;
 	/* Don't match lmc cards */
 	if (PCI_VENDOR(pci_conf_read(pa->pa_pc, pa->pa_tag,
 	    PCI_SUBSYS_ID_REG)) == PCI_VENDOR_LMC)
 		return NULL;
 	for (tpp = tlp_pci_products; tpp->tpp_chip != TULIP_CHIP_INVALID;
 	    tpp++) {
 		if (PCI_VENDOR(pa->pa_id) == tpp->tpp_vendor &&
 		    PCI_PRODUCT(pa->pa_id) == tpp->tpp_product)
 			return tpp;
+	}
 	return NULL;
+}
 static void
 tlp_pci_get_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr,
     const struct tlp_pci_quirks *tpq)
+{
 	for (; tpq->tpq_func != NULL; tpq++) {
 		if (tpq->tpq_oui[0] == enaddr[0] &&
 		    tpq->tpq_oui[1] == enaddr[1] &&
 		    tpq->tpq_oui[2] == enaddr[2]) {
 			(*tpq->tpq_func)(psc, enaddr);
 			return;
+		}
+	}
+}
 static void
 tlp_pci_check_slaved(struct tulip_pci_softc *psc, int shared, int slaved)
+{
 	extern struct cfdriver tlp_cd;
 	struct tulip_pci_softc *cur, *best = NULL;
 	struct tulip_softc *sc = &psc->sc_tulip;
 	int i;
 	/*
 	 * First of all, find the lowest pcidev numbered device on our
 	 * bus marked as shared.  That should be our master.
 	 */
 	for (i = 0; i < tlp_cd.cd_ndevs; i++) {
 		if ((cur = device_lookup_private(&tlp_cd, i)) == NULL)
 			continue;
 		if (device_parent(cur->sc_tulip.sc_dev) !=
 		    device_parent(sc->sc_dev))
 			continue;
 		if ((cur->sc_flags & shared) == 0)
 			continue;
 		if (cur == psc)
 			continue;
 		if (best == NULL ||
 		    best->sc_tulip.sc_devno > cur->sc_tulip.sc_devno)
 			best = cur;
+	}
 	if (best != NULL) {
 		psc->sc_master = best;
 		psc->sc_flags |= (shared | slaved);
+	}
+}
 static int
 tlp_pci_match(device_t parent, cfdata_t match, void *aux)
+{
 	struct pci_attach_args *pa = aux;
 	if (tlp_pci_lookup(pa) != NULL)
 		return 10;	/* beat if_de.c */
 	return 0;
+}
 static void
 tlp_pci_attach(device_t parent, device_t self, void *aux)
+{
 	struct tulip_pci_softc *psc = device_private(self);
 	struct tulip_softc *sc = &psc->sc_tulip;
 	struct pci_attach_args *pa = aux;
 	pci_chipset_tag_t pc = pa->pa_pc;
 	pci_intr_handle_t ih;
 	const char *intrstr = NULL;
 	bus_space_tag_t iot, memt;
 	bus_space_handle_t ioh, memh;
 	int ioh_valid, memh_valid, i, j;
 	const struct tulip_pci_product *tpp;
 	prop_data_t ea;
 	uint8_t enaddr[ETHER_ADDR_LEN];
 	uint32_t val = 0;
 	pcireg_t reg;
 	int error;
 	bus_size_t iosize = 0, memsize = 0;
 	sc->sc_dev = self;
 	sc->sc_devno = pa->pa_device;
 	psc->sc_pc = pa->pa_pc;
 	psc->sc_pcitag = pa->pa_tag;
 	LIST_INIT(&psc->sc_intrslaves);
 	tpp = tlp_pci_lookup(pa);
 	if (tpp == NULL) {
 		printf("\n");
 		panic("tlp_pci_attach: impossible");
+	}
 	sc->sc_chip = tpp->tpp_chip;
 	/*
 	 * By default, Tulip registers are 8 bytes long (4 bytes
 	 * followed by a 4 byte pad).
 	 */
 	sc->sc_regshift = 3;
 	/*
 	 * No power management hooks.
 	 * XXX Maybe we should add some!
 	 */
 	sc->sc_flags |= TULIPF_ENABLED;
 	/*
 	 * Get revision info, and set some chip-specific variables.
 	 */
 	sc->sc_rev = PCI_REVISION(pa->pa_class);
 	switch (sc->sc_chip) {
 	case TULIP_CHIP_21140:
 		if (sc->sc_rev >= 0x20)
 			sc->sc_chip = TULIP_CHIP_21140A;
 		break;
 	case TULIP_CHIP_21142:
 		if (sc->sc_rev >= 0x20)
 			sc->sc_chip = TULIP_CHIP_21143;
 		break;
 	case TULIP_CHIP_82C168:
 		if (sc->sc_rev >= 0x20)
 			sc->sc_chip = TULIP_CHIP_82C169;
 		break;
 	case TULIP_CHIP_MX98713:
 		if (sc->sc_rev >= 0x10)
 			sc->sc_chip = TULIP_CHIP_MX98713A;
 		break;
 	case TULIP_CHIP_MX98715:
 		if (sc->sc_rev >= 0x20)
 			sc->sc_chip = TULIP_CHIP_MX98715A;
 		if (sc->sc_rev >= 0x25)
 			sc->sc_chip = TULIP_CHIP_MX98715AEC_X;
 		if (sc->sc_rev >= 0x30)
 			sc->sc_chip = TULIP_CHIP_MX98725;
 		break;
 	case TULIP_CHIP_WB89C840F:
 		sc->sc_regshift = 2;
 		break;
 	case TULIP_CHIP_AN985:
 		/*
 		 * The AN983 and AN985 are very similar, and are
 		 * differentiated by a "signature" register that
 		 * is like, but not identical, to a PCI ID register.
 		 */
 		reg = pci_conf_read(pc, pa->pa_tag, 0x80);
 		switch (reg) {
 		case 0x09811317:
 			sc->sc_chip = TULIP_CHIP_AN985;
 			break;
 		case 0x09851317:
 			sc->sc_chip = TULIP_CHIP_AN983;
 			break;
 		default:
 			/* Unknown -- use default. */
 			break;
+		}
 		break;
 	case TULIP_CHIP_AX88140:
 		if (sc->sc_rev >= 0x10)
 			sc->sc_chip = TULIP_CHIP_AX88141;
 		break;
 	case TULIP_CHIP_DM9102:
 		if (sc->sc_rev >= 0x30)
 			sc->sc_chip = TULIP_CHIP_DM9102A;
 		break;
 	default:
 		/* Nothing. */
 		break;
+	}
 	aprint_normal(": %s Ethernet, pass %d.%d\n",
 	    tlp_chip_name(sc->sc_chip),
 	    (sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf);
 	switch (sc->sc_chip) {
 	case TULIP_CHIP_21040:
 		if (sc->sc_rev < 0x20) {
 			aprint_normal_dev(self,
 			    "21040 must be at least pass 2.0\n");
 			return;
+		}
 		break;
 	case TULIP_CHIP_21140:
 		if (sc->sc_rev < 0x11) {
 			aprint_normal_dev(self,
 			    "21140 must be at least pass 1.1\n");
 			return;
+		}
 		break;
 	default:
 		/* Nothing. */
 		break;
+	}
 	/*
 	 * Check to see if the device is in power-save mode, and
 	 * being it out if necessary.
 	 */
 	switch (sc->sc_chip) {
 	case TULIP_CHIP_21140:
 	case TULIP_CHIP_21140A:
 	case TULIP_CHIP_21142:
 	case TULIP_CHIP_21143:
 	case TULIP_CHIP_MX98713A:
 	case TULIP_CHIP_MX98715:
 	case TULIP_CHIP_MX98715A:
 	case TULIP_CHIP_MX98715AEC_X:
 	case TULIP_CHIP_MX98725:
 	case TULIP_CHIP_DM9102:
 	case TULIP_CHIP_DM9102A:
 	case TULIP_CHIP_AX88140:
 	case TULIP_CHIP_AX88141:
 	case TULIP_CHIP_RS7112:
 		/*
 		 * Clear the "sleep mode" bit in the CFDA register.
 		 */
 		reg = pci_conf_read(pc, pa->pa_tag, TULIP_PCI_CFDA);
 		if (reg & (CFDA_SLEEP|CFDA_SNOOZE))
 			pci_conf_write(pc, pa->pa_tag, TULIP_PCI_CFDA,
 			    reg & ~(CFDA_SLEEP|CFDA_SNOOZE));
 		break;
 	default:
 		/* Nothing. */
 		break;
+	}
 	/* power up chip */
 	if ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
 	    NULL)) && error != EOPNOTSUPP) {
 		aprint_error_dev(self, "cannot activate %d\n",
 		    error);
 		return;
+	}
 	/*
 	 * Map the device.
 	 */
 	ioh_valid = (pci_mapreg_map(pa, TULIP_PCI_IOBA,
 	    PCI_MAPREG_TYPE_IO, 0,
 	    &iot, &ioh, NULL, &iosize) == 0);
 	memh_valid = (pci_mapreg_map(pa, TULIP_PCI_MMBA,
 	    PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
 	    &memt, &memh, NULL, &memsize) == 0);
 	if (memh_valid) {
 		sc->sc_st = memt;
 		sc->sc_sh = memh;
 		psc->sc_mapsize = memsize;
 		if (ioh_valid) {
 			bus_space_unmap(iot, ioh, iosize);
 			ioh_valid = 0;
+		}
 	} else if (ioh_valid) {
 		sc->sc_st = iot;
 		sc->sc_sh = ioh;
 		psc->sc_mapsize = iosize;
 		if (memh_valid) {
 			bus_space_unmap(memt, memh, memsize);
 			memh_valid = 0;
+		}
 	} else {
 		aprint_error_dev(self, "unable to map device registers\n");
 		goto fail;
+	}
 	sc->sc_dmat = pa->pa_dmat;
 	/*
 	 * Make sure bus mastering is enabled.
 	 */
 	pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
 	    pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
 	    PCI_COMMAND_MASTER_ENABLE);
 	/*
 	 * Get the cacheline size.
 	 */
 	sc->sc_cacheline = PCI_CACHELINE(pci_conf_read(pc, pa->pa_tag,
 	    PCI_BHLC_REG));
 	/*
 	 * Get PCI data moving command info.
 	 */
 	if (pa->pa_flags & PCI_FLAGS_MRL_OKAY)
 		sc->sc_flags |= TULIPF_MRL;
 	if (pa->pa_flags & PCI_FLAGS_MRM_OKAY)
 		sc->sc_flags |= TULIPF_MRM;
 	if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
 		sc->sc_flags |= TULIPF_MWI;
 	/*
 	 * Read the contents of the Ethernet Address ROM/SROM.
 	 */
 	switch (sc->sc_chip) {
 	case TULIP_CHIP_21040:
 		sc->sc_srom_addrbits = 6;
 		sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF, M_NOWAIT);
 		TULIP_WRITE(sc, CSR_MIIROM, MIIROM_SROMCS);
 		for (i = 0; i < TULIP_ROM_SIZE(6); i++) {
 			for (j = 0; j < 10000; j++) {
 				val = TULIP_READ(sc, CSR_MIIROM);
 				if ((val & MIIROM_DN) == 0)
 					break;
+			}
 			sc->sc_srom[i] = val & MIIROM_DATA;
+		}
 		break;
 	case TULIP_CHIP_82C168:
 	case TULIP_CHIP_82C169:
+	    {
 		sc->sc_srom_addrbits = 2;
 		sc->sc_srom = malloc(TULIP_ROM_SIZE(2), M_DEVBUF, M_NOWAIT);
 		/*
 		 * The Lite-On PNIC stores the Ethernet address in
 		 * the first 3 words of the EEPROM.  EEPROM access
 		 * is not like the other Tulip chips.
 		 */
 		for (i = 0; i < 6; i += 2) {
 			TULIP_WRITE(sc, CSR_PNIC_SROMCTL,
 			    PNIC_SROMCTL_READ | (i >> 1));
 			for (j = 0; j < 500; j++) {
 				delay(2);
 				val = TULIP_READ(sc, CSR_MIIROM);
 				if ((val & PNIC_MIIROM_BUSY) == 0)
 					break;
+			}
 			if (val & PNIC_MIIROM_BUSY) {
 				aprint_error_dev(self, "EEPROM timed out\n");
 				goto fail;
+			}
 			val &= PNIC_MIIROM_DATA;
 			sc->sc_srom[i] = val >> 8;
 			sc->sc_srom[i + 1] = val & 0xff;
+		}
 		break;
+	    }
 	default:
 		/*
 		 * XXX This isn't quite the right way to do this; we should
 		 * XXX be attempting to fetch the mac-addr property in the
 		 * XXX bus-agnostic part of the driver independently.  But
 		 * XXX that requires a larger change in the SROM handling
 		 * XXX logic, and for now we can at least remove a machine-
 		 * XXX dependent wart from the PCI front-end.
 		 */
 		ea = prop_dictionary_get(device_properties(self),
 					 "mac-address");
 		if (ea != NULL) {
 			extern int tlp_srom_debug;
 			KASSERT(prop_object_type(ea) == PROP_TYPE_DATA);
 			KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN);
 			memcpy(enaddr, prop_data_data_nocopy(ea),
 			       ETHER_ADDR_LEN);
 			sc->sc_srom_addrbits = 6;
 			sc->sc_srom = malloc(TULIP_ROM_SIZE(6), M_DEVBUF,
 			    M_NOWAIT|M_ZERO);
 			memcpy(sc->sc_srom, enaddr, sizeof(enaddr));
 			if (tlp_srom_debug) {
 				aprint_normal("SROM CONTENTS:");
 				for (i = 0; i < TULIP_ROM_SIZE(6); i++) {
 					if ((i % 8) == 0)
 						aprint_normal("\n\t");
 					aprint_normal("0x%02x ", sc->sc_srom[i]);
+				}
 				aprint_normal("\n");
+			}
 			break;
+		}
 		/* Check for a slaved ROM on a multi-port board. */
 		tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDROM,
 		    TULIP_PCI_SLAVEROM);
 		if (psc->sc_flags & TULIP_PCI_SLAVEROM) {
 			sc->sc_srom_addrbits =
 			    psc->sc_master->sc_tulip.sc_srom_addrbits;
 			sc->sc_srom = psc->sc_master->sc_tulip.sc_srom;
 			enaddr[5] +=
 			    sc->sc_devno - psc->sc_master->sc_tulip.sc_devno;
+		}
 		else if (tlp_read_srom(sc) == 0)
 			goto cant_cope;
 		break;
+	}
 	/*
 	 * Deal with chip/board quirks.  This includes setting up
 	 * the mediasw, and extracting the Ethernet address from
 	 * the rombuf.
 	 */
 	switch (sc->sc_chip) {
 	case TULIP_CHIP_21040:
 		/*
 		 * Parse the Ethernet Address ROM.
 		 */
 		if (tlp_parse_old_srom(sc, enaddr) == 0)
 			goto cant_cope;
 		/*
 		 * All 21040 boards start out with the same
 		 * media switch.
 		 */
 		sc->sc_mediasw = &tlp_21040_mediasw;
 		/*
 		 * Deal with any quirks this board might have.
 		 */
 		tlp_pci_get_quirks(psc, enaddr, tlp_pci_21040_quirks);
 		break;
 	case TULIP_CHIP_21041:
 		/* Check for new format SROM. */
 		if (tlp_isv_srom_enaddr(sc, enaddr) == 0) {
 			/*
 			 * Not an ISV SROM; try the old DEC Ethernet Address
 			 * ROM format.
 			 */
 			if (tlp_parse_old_srom(sc, enaddr) == 0)
 				goto cant_cope;
+		}
 		/*
 		 * All 21041 boards use the same media switch; they all
 		 * work basically the same!  Yippee!
 		 */
 		sc->sc_mediasw = &tlp_21041_mediasw;
 		/*
 		 * Deal with any quirks this board might have.
 		 */
 		tlp_pci_get_quirks(psc, enaddr, tlp_pci_21041_quirks);
 		break;
 	case TULIP_CHIP_21140:
 	case TULIP_CHIP_21140A:
 		/* Check for new format SROM. */
 		if (tlp_isv_srom_enaddr(sc, enaddr) == 0) {
 			/*
 			 * Not an ISV SROM; try the old DEC Ethernet Address
 			 * ROM format.
 			 */
 			if (tlp_parse_old_srom(sc, enaddr) == 0)
 				goto cant_cope;
 		} else {
 			/*
 			 * We start out with the 2114x ISV media switch.
 			 * When we search for quirks, we may change to
 			 * a different switch.
 			 */
 			sc->sc_mediasw = &tlp_2114x_isv_mediasw;
+		}
 		/*
 		 * Deal with any quirks this board might have.
 		 */
 		tlp_pci_get_quirks(psc, enaddr, tlp_pci_21140_quirks);
 		/*
 		 * Bail out now if we can't deal with this board.
 		 */
 		if (sc->sc_mediasw == NULL)
 			goto cant_cope;
 		break;
 	case TULIP_CHIP_21142:
 	case TULIP_CHIP_21143:
 		/* Check for new format SROM. */
 		if (tlp_isv_srom_enaddr(sc, enaddr) == 0) {
 			/*
 			 * Not an ISV SROM; try the old DEC Ethernet Address
 			 * ROM format.
 			 */
 			if (tlp_parse_old_srom(sc, enaddr) == 0) {
 				/*
 				 * One last try: just copy the address
 				 * from offset 20 and try to look
 				 * up quirks.
 				 */
 				memcpy(enaddr, &sc->sc_srom[20],
 				    ETHER_ADDR_LEN);
+			}
 		} else {
 			/*
 			 * We start out with the 2114x ISV media switch.
 			 * When we search for quirks, we may change to
 			 * a different switch.
 			 */
 			sc->sc_mediasw = &tlp_2114x_isv_mediasw;
+		}
 		/*
 		 * Deal with any quirks this board might have.
 		 */
 		tlp_pci_get_quirks(psc, enaddr, tlp_pci_21142_quirks);
 		/*
 		 * Bail out now if we can't deal with this board.
 		 */
 		if (sc->sc_mediasw == NULL)
 			goto cant_cope;
 		break;
 	case TULIP_CHIP_82C168:
 	case TULIP_CHIP_82C169:
 		/*
 		 * Lite-On PNIC's Ethernet address is the first 6
 		 * bytes of its EEPROM.
 		 */
 		memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN);
 		/*
 		 * Lite-On PNICs always use the same mediasw; we
 		 * select MII vs. internal NWAY automatically.
 		 */
 		sc->sc_mediasw = &tlp_pnic_mediasw;
 		break;
 	case TULIP_CHIP_MX98713:
 		/*
 		 * The Macronix MX98713 has an MII and GPIO, but no
 		 * internal Nway block.  This chip is basically a
 		 * perfect 21140A clone, with the exception of the
 		 * a magic register frobbing in order to make the
 		 * interface function.
 		 */
 		if (tlp_isv_srom_enaddr(sc, enaddr)) {
 			sc->sc_mediasw = &tlp_2114x_isv_mediasw;
 			break;
+		}
 		/* FALLTHROUGH */
 	case TULIP_CHIP_82C115:
 		/*
 		 * Yippee!  The Lite-On 82C115 is a clone of
 		 * the MX98725 (the data sheet even says `MXIC'
 		 * on it)!  Imagine that, a clone of a clone.
+		 *
 		 * The differences are really minimal:
+		 *
 		 *	- Wake-On-LAN support
 		 *	- 128-bit multicast hash table, rather than
 		 *	  the standard 512-bit hash table
 		 */
 		/* FALLTHROUGH */
 	case TULIP_CHIP_MX98713A:
 	case TULIP_CHIP_MX98715A:
 	case TULIP_CHIP_MX98715AEC_X:
 	case TULIP_CHIP_MX98725:
 		/*
 		 * The MX98713A has an MII as well as an internal Nway block,
 		 * but no GPIO.  The MX98715 and MX98725 have an internal
 		 * Nway block only.
+		 *
 		 * The internal Nway block, unlike the Lite-On PNIC's, does
 		 * just that - performs Nway.  Once autonegotiation completes,
 		 * we must program the GPR media information into the chip.
+		 *
 		 * The byte offset of the Ethernet address is stored at
 		 * offset 0x70.
 		 */
 		memcpy(enaddr, &sc->sc_srom[sc->sc_srom[0x70]], ETHER_ADDR_LEN);
 		sc->sc_mediasw = &tlp_pmac_mediasw;
 		break;
 	case TULIP_CHIP_WB89C840F:
 		/*
 		 * Winbond 89C840F's Ethernet address is the first
 		 * 6 bytes of its EEPROM.
 		 */
 		memcpy(enaddr, sc->sc_srom, ETHER_ADDR_LEN);
 		/*
 		 * Winbond 89C840F has an MII attached to the SIO.
 		 */
 		sc->sc_mediasw = &tlp_sio_mii_mediasw;
 		break;
 	case TULIP_CHIP_AL981:
 		/*
 		 * The ADMtek AL981's Ethernet address is located
 		 * at offset 8 of its EEPROM.
 		 */
 		memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN);
 		/*
 		 * ADMtek AL981 has a built-in PHY accessed through
 		 * special registers.
 		 */
 		sc->sc_mediasw = &tlp_al981_mediasw;
 		break;
 	case TULIP_CHIP_AN983:
 	case TULIP_CHIP_AN985:
 		/*
 		 * The ADMtek AN985's Ethernet address is located
 		 * at offset 8 of its EEPROM.
 		 */
 		memcpy(enaddr, &sc->sc_srom[8], ETHER_ADDR_LEN);
 		/*
 		 * The ADMtek AN985 can be configured in Single-Chip
 		 * mode or MAC-only mode.  Single-Chip uses the built-in
 		 * PHY, MAC-only has an external PHY (usually HomePNA).
 		 * The selection is based on an EEPROM setting, and both
 		 * PHYs are accessed via MII attached to SIO.
+		 *
 		 * The AN985 "ghosts" the internal PHY onto all
 		 * MII addresses, so we have to use a media init
 		 * routine that limits the search.
 		 * XXX How does this work with MAC-only mode?
 		 */
 		sc->sc_mediasw = &tlp_an985_mediasw;
 		break;
 	case TULIP_CHIP_DM9102:
 	case TULIP_CHIP_DM9102A:
 		/*
 		 * Some boards with the Davicom chip have an ISV
 		 * SROM (mostly DM9102A boards -- trying to describe
 		 * the HomePNA PHY, probably) although the data in
 		 * them is generally wrong.  Check for ISV format
 		 * and grab the Ethernet address that way, and if
 		 * that fails, fall back on grabbing it from an
 		 * observed offset of 20 (which is where it would
 		 * be in an ISV SROM anyhow, tho ISV can cope with
 		 * multi-port boards).
 		 */
 		if (!tlp_isv_srom_enaddr(sc, enaddr)) {
 			prop_data_t eaddrprop;
 			eaddrprop = prop_dictionary_get(
 				device_properties(self), "mac-address");
 			if (eaddrprop != NULL
 			    && prop_data_size(eaddrprop) == ETHER_ADDR_LEN)
 				memcpy(enaddr,
 				    prop_data_data_nocopy(eaddrprop),
 				    ETHER_ADDR_LEN);
 			else
 				memcpy(enaddr, &sc->sc_srom[20],
 				    ETHER_ADDR_LEN);
+		}
 		/*
 		 * Davicom chips all have an internal MII interface
 		 * and a built-in PHY.  DM9102A also has a an external
 		 * MII interface, usually with a HomePNA PHY attached
 		 * to it.
 		 */
 		sc->sc_mediasw = &tlp_dm9102_mediasw;
 		break;
 	case TULIP_CHIP_AX88140:
 	case TULIP_CHIP_AX88141:
 		/*
 		 * ASIX AX88140/AX88141 Ethernet Address is located at offset
 		 * 20 of the SROM.
 		 */
 		memcpy(enaddr, &sc->sc_srom[20], ETHER_ADDR_LEN);
 		/*
 		 * ASIX AX88140A/AX88141 chip can have a built-in PHY or
 		 * an external MII interface.
 		 */
 		sc->sc_mediasw = &tlp_asix_mediasw;
 		break;
 	case TULIP_CHIP_RS7112:
 		/*
 		 * RS7112 Ethernet Address is located of offset 0x19a
 		 * of the SROM
 		 */
 		memcpy(enaddr, &sc->sc_srom[0x19a], ETHER_ADDR_LEN);
 		/* RS7112 chip has a PHY at MII address 1 */
 		sc->sc_mediasw = &tlp_rs7112_mediasw;
 		break;
 	default:
  cant_cope:
 		aprint_error_dev(self, "sorry, unable to handle your board\n");
 		goto fail;
+	}
 	/*
 	 * Handle shared interrupts.
 	 */
 	if (psc->sc_flags & TULIP_PCI_SHAREDINTR) {
 		if (psc->sc_master)
 			psc->sc_flags |= TULIP_PCI_SLAVEINTR;
 		else {
 			tlp_pci_check_slaved(psc, TULIP_PCI_SHAREDINTR,
 			    TULIP_PCI_SLAVEINTR);
 			if (psc->sc_master == NULL)
 				psc->sc_master = psc;
+		}
 		LIST_INSERT_HEAD(&psc->sc_master->sc_intrslaves,
 		    psc, sc_intrq);
+	}
 	if (psc->sc_flags & TULIP_PCI_SLAVEINTR) {
 		aprint_normal_dev(self, "sharing interrupt with %s\n",
 		    device_xname(psc->sc_master->sc_tulip.sc_dev));
 	} else {
 		/*
 		 * Map and establish our interrupt.
 		 */
 		if (pci_intr_map(pa, &ih)) {
 			aprint_error_dev(self, "unable to map interrupt\n");
 			goto fail;
+		}
 		intrstr = pci_intr_string(pc, ih);
 		psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET,
 		    (psc->sc_flags & TULIP_PCI_SHAREDINTR) ?
 		    tlp_pci_shared_intr : tlp_intr, sc);
 		if (psc->sc_ih == NULL) {
 			aprint_error_dev(self, "unable to establish interrupt");
 			if (intrstr != NULL)
 				aprint_error(" at %s", intrstr);
 			aprint_error("\n");
 			goto fail;
+		}
 		aprint_normal_dev(self, "interrupting at %s\n",
 		    intrstr);
+	}
 	/*
 	 * Finish off the attach.
 	 */
 	error = tlp_attach(sc, enaddr);
 	if (error)
 		goto fail;
 	return;
 fail:
 	if (psc->sc_ih != NULL) {
 		pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
 		psc->sc_ih = NULL;
+	}
 	if (ioh_valid)
 		bus_space_unmap(iot, ioh, iosize);
 	if (memh_valid)
 		bus_space_unmap(memt, memh, memsize);
 	psc->sc_mapsize = 0;
 	return;
+}
 static int
 tlp_pci_detach(device_t self, int flags)
+{
 	struct tulip_pci_softc *psc = device_private(self);
 	struct tulip_softc *sc = &psc->sc_tulip;
 	int rv;
 	rv = tlp_detach(sc);
 	if (rv)
 		return rv;
 	if (psc->sc_ih != NULL) {
 		pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
 		psc->sc_ih = NULL;
+	}
 	if (psc->sc_mapsize) {
 		bus_space_unmap(sc->sc_st, sc->sc_sh, psc->sc_mapsize);
 		psc->sc_mapsize = 0;
+	}
 	return 0;
+}
 static int
 tlp_pci_shared_intr(void *arg)
+{
 	struct tulip_pci_softc *master = arg, *slave;
 	int rv = 0;
 	for (slave = LIST_FIRST(&master->sc_intrslaves);
 	     slave != NULL;
 	     slave = LIST_NEXT(slave, sc_intrq))
 		rv |= tlp_intr(&slave->sc_tulip);
 	return rv;
+}
 static void
 tlp_pci_dec_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * This isn't really a quirk-gathering device, really.  We
 	 * just want to get the spiffy DEC board name from the SROM.
 	 */
 	strcpy(sc->sc_name, "DEC ");
 	if (memcmp(&sc->sc_srom[29], "DE500", 5) == 0 ||
 	    memcmp(&sc->sc_srom[29], "DE450", 5) == 0)
 		memcpy(&sc->sc_name[4], &sc->sc_srom[29], 8);
 	else
 		sc->sc_name[3] = '\0';
+}
 static void
 tlp_pci_znyx_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	uint16_t id = 0;
 	/*
 	 * If we have a slaved ROM, just copy the bits from the master.
 	 * This is in case we fail the ROM ID check (older boards) and
 	 * need to fall back on Ethernet address model checking; that
 	 * will fail for slave chips.
 	 */
 	if (psc->sc_flags & TULIP_PCI_SLAVEROM) {
 		strcpy(sc->sc_name, psc->sc_master->sc_tulip.sc_name);
 		sc->sc_mediasw = psc->sc_master->sc_tulip.sc_mediasw;
 		psc->sc_flags |=
 		    psc->sc_master->sc_flags & TULIP_PCI_SHAREDINTR;
 		return;
+	}
 	if (sc->sc_srom[32] == 0x4a && sc->sc_srom[33] == 0x52) {
 		id = sc->sc_srom[37] | (sc->sc_srom[36] << 8);
 		switch (id) {
  zx312:
 		case 0x0602:	/* ZX312 */
 			strcpy(sc->sc_name, "ZNYX ZX312");
 			return;
 		case 0x0622:	/* ZX312T */
 			strcpy(sc->sc_name, "ZNYX ZX312T");
 			sc->sc_mediasw = &tlp_21040_tp_mediasw;
 			return;
  zx314_inta:
 		case 0x0701:	/* ZX314 INTA */
 			psc->sc_flags |= TULIP_PCI_SHAREDINTR;
 			/* FALLTHROUGH */
 		case 0x0711:	/* ZX314 */
 			strcpy(sc->sc_name, "ZNYX ZX314");
 			psc->sc_flags |= TULIP_PCI_SHAREDROM;
 			sc->sc_mediasw = &tlp_21040_tp_mediasw;
 			return;
  zx315_inta:
 		case 0x0801:	/* ZX315 INTA */
 			psc->sc_flags |= TULIP_PCI_SHAREDINTR;
 			/* FALLTHROUGH */
 		case 0x0811:	/* ZX315 */
 			strcpy(sc->sc_name, "ZNYX ZX315");
 			psc->sc_flags |= TULIP_PCI_SHAREDROM;
 			return;
 		default:
 			id = 0;
 			break;
+		}
+	}
 	/*
 	 * Deal with boards that have broken ROMs.
 	 */
 	if (id == 0) {
 		if ((enaddr[3] & ~3) == 0xf0 && (enaddr[5] & 3) == 0x00)
 			goto zx314_inta;
 		if ((enaddr[3] & ~3) == 0xf4 && (enaddr[5] & 1) == 0x00)
 			goto zx315_inta;
 		if ((enaddr[3] & ~3) == 0xec)
 			goto zx312;
+	}
 	strcpy(sc->sc_name, "ZNYX ZX31x");
+}
 static void	tlp_pci_znyx_21142_qs6611_reset(struct tulip_softc *);
 static void
 tlp_pci_znyx_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	pcireg_t subid;
 	subid = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_SUBSYS_ID_REG);
 	if (PCI_VENDOR(subid) != PCI_VENDOR_ZNYX)
 		return;		/* ? */
 	switch (PCI_PRODUCT(subid) & 0xff) {
 	/*
 	 * ZNYX 21143 boards with QS6611 PHY
 	 */
 	case 0x12:	/* ZX345Q */
 	case 0x13:	/* ZX346Q */
 	case 0x14:	/* ZX348Q */
 	case 0x18:	/* ZX414 */
 	case 0x19:	/* ZX412 */
 	case 0x1a:	/* ZX444 */
 	case 0x1b:	/* ZX442 */
 	case 0x23:	/* ZX212 */
 	case 0x24:	/* ZX214 */
 	case 0x29:	/* ZX374 */
 	case 0x2d:	/* ZX372 */
 	case 0x2b:	/* ZX244 */
 	case 0x2c:	/* ZX424 */
 	case 0x2e:	/* ZX422 */
 		aprint_normal_dev(sc->sc_dev, "QS6611 PHY\n");
 		sc->sc_reset = tlp_pci_znyx_21142_qs6611_reset;
 		break;
+	}
+}
 static void
 tlp_pci_znyx_21142_qs6611_reset(struct tulip_softc *sc)
+{
 	/*
 	 * Reset QS6611 PHY.
 	 */
 	TULIP_WRITE(sc, CSR_SIAGEN,
 	    SIAGEN_CWE | SIAGEN_LGS1 | SIAGEN_ABM | (0xf << 16));
 	delay(200);
 	TULIP_WRITE(sc, CSR_SIAGEN, (0x4 << 16));
 	delay(10000);
+}
 static void
 tlp_pci_smc_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	uint16_t id1, id2, ei;
 	int auibnc = 0, utp = 0;
 	char *cp;
 	id1 = sc->sc_srom[0x60] | (sc->sc_srom[0x61] << 8);
 	id2 = sc->sc_srom[0x62] | (sc->sc_srom[0x63] << 8);
 	ei  = sc->sc_srom[0x66] | (sc->sc_srom[0x67] << 8);
 	strcpy(sc->sc_name, "SMC 8432");
 	cp = &sc->sc_name[8];
 	if ((id1 & 1) == 0) {
 		*cp++ = 'B';
 		auibnc = 1;
+	}
 	if ((id1 & 0xff) > 0x32) {
 		*cp++ = 'T';
 		utp = 1;
+	}
 	if ((id1 & 0x4000) == 0) {
 		*cp++ = 'A';
 		auibnc = 1;
+	}
 	if (id2 == 0x15) {
 		sc->sc_name[7] = '4';
 		*cp++ = '-';
 		*cp++ = 'C';
 		*cp++ = 'H';
 		*cp++ = ei ? '2' : '1';
+	}
 	*cp = '\0';
 	if (utp != 0 && auibnc == 0)
 		sc->sc_mediasw = &tlp_21040_tp_mediasw;
 	else if (utp == 0 && auibnc != 0)
 		sc->sc_mediasw = &tlp_21040_auibnc_mediasw;
+}
 static void
 tlp_pci_cogent_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	strcpy(psc->sc_tulip.sc_name, "Cogent multi-port");
 	psc->sc_flags |= TULIP_PCI_SHAREDINTR|TULIP_PCI_SHAREDROM;
+}
 static void
 tlp_pci_accton_21040_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	strcpy(psc->sc_tulip.sc_name, "ACCTON EN1203");
+}
 static void	tlp_pci_asante_21140_reset(struct tulip_softc *);
 static void
 tlp_pci_asante_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Some Asante boards don't use the ISV SROM format.  For
 	 * those that don't, we initialize the GPIO direction bits,
 	 * and provide our own reset hook, which resets the MII.
+	 *
 	 * All of these boards use SIO-attached-MII media.
 	 */
 	if (sc->sc_mediasw == &tlp_2114x_isv_mediasw)
 		return;
 	strcpy(sc->sc_name, "Asante");
 	sc->sc_gp_dir = 0xbf;
 	sc->sc_reset = tlp_pci_asante_21140_reset;
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
+}
 static void
 tlp_pci_e100_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	if (sc->sc_mediasw == &tlp_2114x_isv_mediasw)
 		return;
 	strcpy(sc->sc_name, "UMAX E100");
 	sc->sc_gp_dir = 0xbf;
 	sc->sc_reset = tlp_pci_asante_21140_reset;
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
+}
 static void
 tlp_pci_asante_21140_reset(struct tulip_softc *sc)
+{
 	TULIP_WRITE(sc, CSR_GPP, GPP_GPC | sc->sc_gp_dir);
 	TULIP_WRITE(sc, CSR_GPP, 0x8);
 	delay(100);
 	TULIP_WRITE(sc, CSR_GPP, 0);
+}
 static void	tlp_pci_phobos_21140_reset(struct tulip_softc *);
 static void
 tlp_pci_phobos_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Phobos boards just use MII-on-SIO.
 	 */
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
 	sc->sc_reset = tlp_pci_phobos_21140_reset;
 	/*
 	 * These boards appear solely on sgimips machines behind a special
 	 * GIO<->PCI ASIC and require the DBO and BLE bits to be set in CSR0.
 	 */
 	sc->sc_flags |= (TULIPF_BLE | TULIPF_DBO);
+}
 static void
 tlp_pci_phobos_21140_reset(struct tulip_softc *sc)
+{
 	TULIP_WRITE(sc, CSR_GPP, GPP_GPC | 0xfd);
 	delay(10);
 	TULIP_WRITE(sc, CSR_GPP, 0xfd);
 	delay(10);
 	TULIP_WRITE(sc, CSR_GPP, 0);
+}
 /*
  * SMC 9332DST media switch.
  */
 static void	tlp_smc9332dst_tmsw_init(struct tulip_softc *);
 static const struct tulip_mediasw tlp_smc9332dst_mediasw = {
 	tlp_smc9332dst_tmsw_init,
 	tlp_21140_gpio_get,
 	tlp_21140_gpio_set
 };
 static void
 tlp_pci_smc_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	strcpy(psc->sc_tulip.sc_name, "SMC 9332DST");
 	sc->sc_mediasw = &tlp_smc9332dst_mediasw;
+}
 static void
 tlp_smc9332dst_tmsw_init(struct tulip_softc *sc)
+{
 	struct tulip_21x4x_media *tm;
 	const char *sep = "";
 	uint32_t reg;
 	int i, cnt;
 	sc->sc_gp_dir = GPP_SMC9332DST_PINS;
 	sc->sc_opmode = OPMODE_MBO | OPMODE_PS;
 	TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode);
 	ifmedia_init(&sc->sc_mii.mii_media, 0, tlp_mediachange,
 	    tlp_mediastatus);
 	aprint_normal_dev(sc->sc_dev, "");
 #define	ADD(m, c) \
 	tm = malloc(sizeof(*tm), M_DEVBUF, M_WAITOK|M_ZERO);		\
 	tm->tm_opmode = (c);						\
 	tm->tm_gpdata = GPP_SMC9332DST_INIT;				\
 	ifmedia_add(&sc->sc_mii.mii_media, (m), 0, tm)
 #define	PRINT(str)	aprint_normal("%s%s", sep, str); sep = ", "
 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, 0), OPMODE_TTM);
 	PRINT("10baseT");
 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, 0),
 	    OPMODE_TTM | OPMODE_FD);
 	PRINT("10baseT-FDX");
 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, 0),
 	    OPMODE_PS | OPMODE_PCS | OPMODE_SCR);
 	PRINT("100baseTX");
 	ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, 0),
 	    OPMODE_PS | OPMODE_PCS | OPMODE_SCR | OPMODE_FD);
 	PRINT("100baseTX-FDX");
 #undef ADD
 #undef PRINT
 	aprint_normal("\n");
 	tlp_reset(sc);
 	TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode | OPMODE_PCS | OPMODE_SCR);
 	TULIP_WRITE(sc, CSR_GPP, GPP_GPC | sc->sc_gp_dir);
 	delay(10);
 	TULIP_WRITE(sc, CSR_GPP, GPP_SMC9332DST_INIT);
 	delay(200000);
 	cnt = 0;
 	for (i = 1000; i > 0; i--) {
 		reg = TULIP_READ(sc, CSR_GPP);
 		if ((~reg & (GPP_SMC9332DST_OK10 |
 			     GPP_SMC9332DST_OK100)) == 0) {
 			if (cnt++ > 100) {
 				break;
+			}
 		} else if ((reg & GPP_SMC9332DST_OK10) == 0) {
 			break;
 		} else {
 			cnt = 0;
+		}
 		delay(1000);
+	}
 	if (cnt > 100) {
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_100_TX);
 	} else {
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T);
+	}
+}
 static void
 tlp_pci_vpc_21140_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	char *p1 = (char *) &sc->sc_srom[32];
 	char *p2 = &sc->sc_name[0];
 	do {
 		if ((unsigned char) *p1 & 0x80)
 			*p2++ = ' ';
 		else
 			*p2++ = *p1;
 	} while (*p1++);
+}
 static void	tlp_pci_cobalt_21142_reset(struct tulip_softc *);
 static void
 tlp_pci_cobalt_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Cobalt Networks interfaces are just MII-on-SIO.
 	 */
 	sc->sc_reset = tlp_pci_cobalt_21142_reset;
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
 	/*
 	 * The Cobalt systems tend to fall back to store-and-forward
 	 * pretty quickly, so we select that from the beginning to
 	 * avoid initial timeouts.
 	 */
 	sc->sc_txthresh = TXTH_SF;
+}
 static void
 tlp_pci_cobalt_21142_reset(struct tulip_softc *sc)
+{
 	/*
 	 * Reset PHY.
 	 */
 	TULIP_WRITE(sc, CSR_SIAGEN, SIAGEN_CWE | (1 << 16));
 	delay(10);
 	TULIP_WRITE(sc, CSR_SIAGEN, SIAGEN_CWE);
 	delay(10);
+}
 static void
 tlp_pci_algor_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Algorithmics boards just have MII-on-SIO.
+	 *
 	 * XXX They also have AUI on the serial interface.
 	 * XXX Deal with this.
 	 */
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
+}
 /*
  * Cogent EM1x0 (aka. Adaptec ANA-6910) media switch.
  */
 static void	tlp_cogent_em1x0_tmsw_init(struct tulip_softc *);
 static const struct tulip_mediasw tlp_cogent_em1x0_mediasw = {
 	tlp_cogent_em1x0_tmsw_init,
 	tlp_21140_gpio_get,
 	tlp_21140_gpio_set
 };
 static void
 tlp_pci_adaptec_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	uint8_t *srom = sc->sc_srom, id0;
 	uint16_t id1, id2;
 	if (sc->sc_mediasw == NULL) {
 		id0 = srom[32];
 		switch (id0) {
 		case 0x12:
 			strcpy(psc->sc_tulip.sc_name, "Cogent EM100TX");
 			sc->sc_mediasw = &tlp_cogent_em1x0_mediasw;
 			break;
 		case 0x13:
 			strcpy(psc->sc_tulip.sc_name, "Cogent ???");
  			sc->sc_mediasw = &tlp_cogent_em1x0_mediasw;
 			psc->sc_flags |= TULIP_PCI_SHAREDINTR |
 			    TULIP_PCI_SHAREDROM;
 			break;
 		case 0x15:
 			strcpy(psc->sc_tulip.sc_name, "Cogent EM100FX");
 			sc->sc_mediasw = &tlp_cogent_em1x0_mediasw;
 			break;
 #if 0
 		case XXX:
 			strcpy(psc->sc_tulip.sc_name, "Cogent EM110TX");
 			sc->sc_mediasw = &tlp_cogent_em1x0_mediasw;
 			break;
 #endif
 		default:
 			printf("%s: unknown Cogent board ID 0x%02x\n",
 			    device_xname(sc->sc_dev), id0);
+		}
 		return;
+	}
 	id1 = TULIP_ROM_GETW(srom, 0);
 	id2 = TULIP_ROM_GETW(srom, 2);
 	if (id1 != 0x1109) {
 		goto unknown;
+	}
 	switch (id2) {
 	case 0x1900:
 		strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6911");
 		break;
 	case 0x2400:
 		strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6944A");
 		psc->sc_flags |= TULIP_PCI_SHAREDINTR|TULIP_PCI_SHAREDROM;
 		break;
 	case 0x2b00:
 		strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6911A");
 		break;
 	case 0x3000:
 		strcpy(psc->sc_tulip.sc_name, "Adaptec ANA-6922");
 		psc->sc_flags |= TULIP_PCI_SHAREDINTR|TULIP_PCI_SHAREDROM;
 		break;
 	default:
  unknown:
 		printf("%s: unknown Adaptec/Cogent board ID 0x%04x/0x%04x\n",
 		    device_xname(sc->sc_dev), id1, id2);
+	}
+}
 static void
 tlp_cogent_em1x0_tmsw_init(struct tulip_softc *sc)
+{
 	struct tulip_21x4x_media *tm;
 	const char *sep = "";
 	sc->sc_gp_dir = GPP_COGENT_EM1x0_PINS;
 	sc->sc_opmode = OPMODE_MBO | OPMODE_PS;
 	TULIP_WRITE(sc, CSR_OPMODE, sc->sc_opmode);
 	ifmedia_init(&sc->sc_mii.mii_media, 0, tlp_mediachange,
 	    tlp_mediastatus);
 	aprint_normal_dev(sc->sc_dev, "");
 #define	ADD(m, c) \
 	tm = malloc(sizeof(*tm), M_DEVBUF, M_WAITOK|M_ZERO);		\
 	tm->tm_opmode = (c);						\
 	tm->tm_gpdata = GPP_COGENT_EM1x0_INIT;				\
 	ifmedia_add(&sc->sc_mii.mii_media, (m), 0, tm)
 #define	PRINT(str)	aprint_normal("%s%s", sep, str); sep = ", "
 	if (sc->sc_srom[32] == 0x15) {
 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, 0, 0),
 		    OPMODE_PS | OPMODE_PCS);
 		PRINT("100baseFX");
 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, IFM_FDX, 0),
 		    OPMODE_PS | OPMODE_PCS | OPMODE_FD);
 		PRINT("100baseFX-FDX");
 		aprint_normal("\n");
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_100_FX);
 	} else {
 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, 0),
 		    OPMODE_PS | OPMODE_PCS | OPMODE_SCR);
 		PRINT("100baseTX");
 		ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_FX, IFM_FDX, 0),
 		    OPMODE_PS | OPMODE_PCS | OPMODE_SCR | OPMODE_FD);
 		PRINT("100baseTX-FDX");
 		aprint_normal("\n");
 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_100_TX);
+	}
 #undef ADD
 #undef PRINT
+}
 static void	tlp_pci_netwinder_21142_reset(struct tulip_softc *);
 static void
 tlp_pci_netwinder_21142_quirks(struct tulip_pci_softc *psc,
     const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Netwinders just use MII-on-SIO.
 	 */
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
 	sc->sc_reset = tlp_pci_netwinder_21142_reset;
+}
 void
 tlp_pci_netwinder_21142_reset(struct tulip_softc *sc)
+{
 	/*
 	 * Reset the PHY.
 	 */
 	TULIP_WRITE(sc, CSR_SIAGEN, 0x0821 << 16);
 	delay(10);
 	TULIP_WRITE(sc, CSR_SIAGEN, 0x0000 << 16);
 	delay(10);
 	TULIP_WRITE(sc, CSR_SIAGEN, 0x0001 << 16);
 	delay(10);
+}
 static void	tlp_pci_phobos_21142_reset(struct tulip_softc *);
 static void
 tlp_pci_phobos_21142_quirks(struct tulip_pci_softc *psc, const uint8_t *enaddr)
+{
 	struct tulip_softc *sc = &psc->sc_tulip;
 	/*
 	 * Phobos boards just use MII-on-SIO.
 	 */
 	sc->sc_mediasw = &tlp_sio_mii_mediasw;
 	sc->sc_reset = tlp_pci_phobos_21142_reset;
 	/*
 	 * These boards appear solely on sgimips machines behind a special
 	 * GIO<->PCI ASIC and require the DBO and BLE bits to be set in CSR0.
 	 */
 	sc->sc_flags |= (TULIPF_BLE | TULIPF_DBO);
+}
 static void
 tlp_pci_phobos_21142_reset(struct tulip_softc *sc)
+{
 	/*
 	 * Reset PHY.
 	 */
 	TULIP_WRITE(sc, CSR_SIAGEN, (0x880f << 16));
 	delay(10);
 	TULIP_WRITE(sc, CSR_SIAGEN, (0x800f << 16));
 	delay(10);
+}