 @@ -158,27 +158,27 @@ R600SetAccelState(ScrnInfoPtr pScrn,
+    {
 	accel_state->vs_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset +
 	    vs_offset;
 	accel_state->ps_mc_addr = info->fbLocation + pScrn->fbOffset + accel_state->shaders->offset +
 	    ps_offset;
+    }
     return TRUE;
+}
 static Bool
 R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     cb_config_t     cb_conf;
     shader_config_t vs_conf, ps_conf;
     uint32_t a, r, g, b;
     float ps_alu_consts[4];
     struct r600_accel_object dst;
     if (!RADEONCheckBPP(pPix->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("R600CheckDatatype failed\n"));
     if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("invalid planemask\n"));
 @@ -313,43 +313,43 @@ R600PrepareSolid(PixmapPtr pPix, int alu
     if (accel_state->vsync)
 	RADEONVlineHelperClear(pScrn);
     accel_state->dst_pix = pPix;
     accel_state->fg = fg;
     return TRUE;
+}
 static void
 R600DoneSolid(PixmapPtr pPix)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     if (accel_state->vsync)
 	r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
 				accel_state->vline_crtc,
 				accel_state->vline_y1,
 				accel_state->vline_y2);
     r600_finish_op(pScrn, 8);
+}
 static void
 R600Solid(PixmapPtr pPix, int x1, int y1, int x2, int y2)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     float *vb;
 #ifdef XF86DRM_MODE
     if (info->cs && CS_FULL(info->cs)) {
 	R600DoneSolid(info->accel_state->dst_pix);
 	radeon_cs_flush_indirect(pScrn);
 	R600PrepareSolid(accel_state->dst_pix,
 			 accel_state->rop,
 			 accel_state->planemask,
 			 accel_state->fg);
+    }
 @@ -507,27 +507,27 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
     r600_set_spi(pScrn, accel_state->ib, (1 - 1), 1);
+}
 static void
 R600DoCopy(ScrnInfoPtr pScrn)
+{
     r600_finish_op(pScrn, 16);
+}
 static void
 R600DoCopyVline(PixmapPtr pPix)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     if (accel_state->vsync)
 	r600_cp_wait_vline_sync(pScrn, accel_state->ib, pPix,
 				accel_state->vline_crtc,
 				accel_state->vline_y1,
 				accel_state->vline_y2);
     r600_finish_op(pScrn, 16);
+}
 static void
 @@ -556,27 +556,27 @@ R600AppendCopyVertex(ScrnInfoPtr pScrn,
     vb[9] = (float)(dstY + h);
     vb[10] = (float)(srcX + w);
     vb[11] = (float)(srcY + h);
     radeon_vbo_commit(pScrn, &accel_state->vbo);
+}
 static Bool
 R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
 		int xdir, int ydir,
 		int rop,
 		Pixel planemask)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     struct r600_accel_object src_obj, dst_obj;
     if (!RADEONCheckBPP(pSrc->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("R600CheckDatatype src failed\n"));
     if (!RADEONCheckBPP(pDst->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("R600CheckDatatype dst failed\n"));
     if (!RADEONValidPM(planemask, pDst->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("Invalid planemask\n"));
     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
 @@ -671,48 +671,48 @@ R600PrepareCopy(PixmapPtr pSrc,   Pixmap
 	RADEONVlineHelperClear(pScrn);
     accel_state->dst_pix = pDst;
     accel_state->src_pix = pSrc;
     accel_state->xdir = xdir;
     accel_state->ydir = ydir;
     return TRUE;
+}
 static void
 R600DoneCopy(PixmapPtr pDst)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     if (!accel_state->same_surface)
 	R600DoCopyVline(pDst);
     if (accel_state->copy_area) {
 	if (!info->cs)
 	    exaOffscreenFree(pDst->drawable.pScreen, accel_state->copy_area);
 	accel_state->copy_area = NULL;
+    }
+}
 static void
 R600Copy(PixmapPtr pDst,
 	 int srcX, int srcY,
 	 int dstX, int dstY,
 	 int w, int h)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     if (accel_state->same_surface && (srcX == dstX) && (srcY == dstY))
 	return;
 #ifdef XF86DRM_MODE
     if (info->cs && CS_FULL(info->cs)) {
 	R600DoneCopy(info->accel_state->dst_pix);
 	radeon_cs_flush_indirect(pScrn);
 	R600PrepareCopy(accel_state->src_pix,
 			accel_state->dst_pix,
 			accel_state->xdir,
 @@ -891,37 +891,28 @@ static Bool R600GetDestFormat(PicturePtr
 	break;
     default:
 	RADEON_FALLBACK(("Unsupported dest format 0x%x\n",
 	       (int)pDstPicture->format));
+    }
     return TRUE;
+}
 static Bool R600CheckCompositeTexture(PicturePtr pPict,
 				      PicturePtr pDstPict,
 				      int op,
 				      int unit)
+{
     int w = pPict->pDrawable->width;
     int h = pPict->pDrawable->height;
     unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone;
     unsigned int i;
     int max_tex_w, max_tex_h;
     max_tex_w = 8192;
     max_tex_h = 8192;
     if ((w > max_tex_w) || (h > max_tex_h))
 	RADEON_FALLBACK(("Picture w/h too large (%dx%d)\n", w, h));
     for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) {
 	if (R600TexFormats[i].fmt == pPict->format)
 	    break;
+    }
     if (i == sizeof(R600TexFormats) / sizeof(R600TexFormats[0]))
 	RADEON_FALLBACK(("Unsupported picture format 0x%x\n",
 			 (int)pPict->format));
     if (pPict->filter != PictFilterNearest &&
 	pPict->filter != PictFilterBilinear)
 	RADEON_FALLBACK(("Unsupported filter 0x%x\n", pPict->filter));
 @@ -938,50 +929,55 @@ static Bool R600CheckCompositeTexture(Pi
 	if (!(((op == PictOpSrc) || (op == PictOpClear)) && (PICT_FORMAT_A(pDstPict->format) == 0)))
 	    RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB source\n"));
+    }
     if (!radeon_transform_is_affine_or_scaled(pPict->transform))
 	RADEON_FALLBACK(("non-affine transforms not supported\n"));
     return TRUE;
+}
 static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr pPix,
 					int unit)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
-    int w = pPict->pDrawable->width;
+    unsigned int repeatType;
     int h = pPict->pDrawable->height;
     unsigned int repeatType = pPict->repeat ? pPict->repeatType : RepeatNone;
     unsigned int i;
     tex_resource_t  tex_res;
     tex_sampler_t   tex_samp;
     int pix_r, pix_g, pix_b, pix_a;
     float vs_alu_consts[8];
     CLEAR (tex_res);
     CLEAR (tex_samp);
     for (i = 0; i < sizeof(R600TexFormats) / sizeof(R600TexFormats[0]); i++) {
 	if (R600TexFormats[i].fmt == pPict->format)
 	    break;
+    }
     /* Texture */
     if (pPict->pDrawable) {
 	tex_res.w               = pPict->pDrawable->width;
 	tex_res.h               = pPict->pDrawable->height;
 	repeatType              = pPict->repeat ? pPict->repeatType : RepeatNone;
     } else {
 	tex_res.w               = 1;
 	tex_res.h               = 1;
 	repeatType              = RepeatNormal;
+    }
     tex_res.id                  = unit;
     tex_res.w                   = w;
     tex_res.h                   = h;
     tex_res.pitch               = accel_state->src_obj[unit].pitch;
     tex_res.depth               = 0;
     tex_res.dim                 = SQ_TEX_DIM_2D;
     tex_res.base                = accel_state->src_obj[unit].offset;
     tex_res.mip_base            = accel_state->src_obj[unit].offset;
     tex_res.size                = accel_state->src_size[unit];
     tex_res.format              = R600TexFormats[i].card_fmt;
     tex_res.bo                  = accel_state->src_obj[unit].bo;
     tex_res.mip_bo              = accel_state->src_obj[unit].bo;
 #ifdef XF86DRM_MODE
     tex_res.surface             = accel_state->src_obj[unit].surface;
 #endif
     tex_res.request_size        = 1;
 @@ -1160,179 +1156,189 @@ static Bool R600TextureSetup(PicturePtr
     tex_samp.clamp_z            = SQ_TEX_WRAP;
     tex_samp.z_filter           = SQ_TEX_Z_FILTER_NONE;
     tex_samp.mip_filter         = 0;			/* no mipmap */
     r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
     if (pPict->transform != 0) {
 	accel_state->is_transform[unit] = TRUE;
 	accel_state->transform[unit] = pPict->transform;
 	vs_alu_consts[0] = xFixedToFloat(pPict->transform->matrix[0][0]);
 	vs_alu_consts[1] = xFixedToFloat(pPict->transform->matrix[0][1]);
 	vs_alu_consts[2] = xFixedToFloat(pPict->transform->matrix[0][2]);
-	vs_alu_consts[3] = 1.0 / w;
+	vs_alu_consts[3] = 1.0 / tex_res.w;
 	vs_alu_consts[4] = xFixedToFloat(pPict->transform->matrix[1][0]);
 	vs_alu_consts[5] = xFixedToFloat(pPict->transform->matrix[1][1]);
 	vs_alu_consts[6] = xFixedToFloat(pPict->transform->matrix[1][2]);
-	vs_alu_consts[7] = 1.0 / h;
+	vs_alu_consts[7] = 1.0 / tex_res.h;
     } else {
 	accel_state->is_transform[unit] = FALSE;
 	vs_alu_consts[0] = 1.0;
 	vs_alu_consts[1] = 0.0;
 	vs_alu_consts[2] = 0.0;
-	vs_alu_consts[3] = 1.0 / w;
+	vs_alu_consts[3] = 1.0 / tex_res.w;
 	vs_alu_consts[4] = 0.0;
 	vs_alu_consts[5] = 1.0;
 	vs_alu_consts[6] = 0.0;
-	vs_alu_consts[7] = 1.0 / h;
+	vs_alu_consts[7] = 1.0 / tex_res.h;
+    }
     /* VS alu constants */
     r600_set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_vs + (unit * 2),
 			sizeof(vs_alu_consts) / SQ_ALU_CONSTANT_offset, vs_alu_consts);
     return TRUE;
+}
 static Bool R600CheckComposite(int op, PicturePtr pSrcPicture, PicturePtr pMaskPicture,
 			       PicturePtr pDstPicture)
+{
     uint32_t tmp1;
     PixmapPtr pSrcPixmap, pDstPixmap;
     int max_tex_w, max_tex_h, max_dst_w, max_dst_h;
     /* Check for unsupported compositing operations. */
     if (op >= (int) (sizeof(R600BlendOp) / sizeof(R600BlendOp[0])))
 	RADEON_FALLBACK(("Unsupported Composite op 0x%x\n", op));
-    if (!pSrcPicture->pDrawable)
+    if (pSrcPicture->pDrawable) {
-	RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
+	pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
-    pSrcPixmap = RADEONGetDrawablePixmap(pSrcPicture->pDrawable);
+	if (pSrcPixmap->drawable.width >= 8192 ||
 	    pSrcPixmap->drawable.height >= 8192) {
 	    RADEON_FALLBACK(("Source w/h too large (%d,%d).\n",
 			     pSrcPixmap->drawable.width,
 			     pSrcPixmap->drawable.height));
+	}
-    max_tex_w = 8192;
+	if (!R600CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0))
-    max_tex_h = 8192;
+	    return FALSE;
-    max_dst_w = 8192;
+    } else if (pSrcPicture->pSourcePict->type != SourcePictTypeSolidFill)
-    max_dst_h = 8192;
+	RADEON_FALLBACK(("Gradient pictures not supported yet\n"));
     if (pSrcPixmap->drawable.width >= max_tex_w ||
 	pSrcPixmap->drawable.height >= max_tex_h) {
 	RADEON_FALLBACK(("Source w/h too large (%d,%d).\n",
 			 pSrcPixmap->drawable.width,
 			 pSrcPixmap->drawable.height));
     pDstPixmap = RADEONGetDrawablePixmap(pDstPicture->pDrawable);
-    if (pDstPixmap->drawable.width >= max_dst_w ||
+    if (pDstPixmap->drawable.width >= 8192 ||
-	pDstPixmap->drawable.height >= max_dst_h) {
+	pDstPixmap->drawable.height >= 8192) {
 	RADEON_FALLBACK(("Dest w/h too large (%d,%d).\n",
 			 pDstPixmap->drawable.width,
 			 pDstPixmap->drawable.height));
+    }
     if (pMaskPicture) {
 	PixmapPtr pMaskPixmap;
-	if (!pMaskPicture->pDrawable)
+	if (pMaskPicture->pDrawable) {
-	    RADEON_FALLBACK(("Solid or gradient pictures not supported yet\n"));
+	    pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
-	pMaskPixmap = RADEONGetDrawablePixmap(pMaskPicture->pDrawable);
+	    if (pMaskPixmap->drawable.width >= 8192 ||
 		pMaskPixmap->drawable.height >= 8192) {
-	if (pMaskPixmap->drawable.width >= max_tex_w ||
+	      RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
-	    pMaskPixmap->drawable.height >= max_tex_h) {
+			       pMaskPixmap->drawable.width,
-	    RADEON_FALLBACK(("Mask w/h too large (%d,%d).\n",
+			       pMaskPixmap->drawable.height));
 			     pMaskPixmap->drawable.width,
 			     pMaskPixmap->drawable.height));
-	if (pMaskPicture->componentAlpha) {
+	    if (pMaskPicture->componentAlpha) {
-	    /* Check if it's component alpha that relies on a source alpha and
+		/* Check if it's component alpha that relies on a source alpha and
-	     * on the source value.  We can only get one of those into the
+		 * on the source value.  We can only get one of those into the
-	     * single source value that we get to blend with.
+		 * single source value that we get to blend with.
-	     */
+		 */
-	    if (R600BlendOp[op].src_alpha &&
+		if (R600BlendOp[op].src_alpha &&
-		(R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) !=
+		    (R600BlendOp[op].blend_cntl & COLOR_SRCBLEND_mask) !=
-		(BLEND_ZERO << COLOR_SRCBLEND_shift)) {
+		    (BLEND_ZERO << COLOR_SRCBLEND_shift)) {
-		RADEON_FALLBACK(("Component alpha not supported with source "
+		    RADEON_FALLBACK(("Component alpha not supported with source "
-				 "alpha and source value blending.\n"));
+				     "alpha and source value blending.\n"));
+		}
+	    }
-	if (!R600CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1))
+	    if (!R600CheckCompositeTexture(pMaskPicture, pDstPicture, op, 1))
-	    return FALSE;
+		return FALSE;
 	} else if (pMaskPicture->pSourcePict->type != SourcePictTypeSolidFill)
 	    RADEON_FALLBACK(("Gradient pictures not supported yet\n"));
+    }
     if (!R600CheckCompositeTexture(pSrcPicture, pDstPicture, op, 0))
 	return FALSE;
     if (!R600GetDestFormat(pDstPicture, &tmp1))
 	return FALSE;
     return TRUE;
+}
 static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
 				 PicturePtr pMaskPicture, PicturePtr pDstPicture,
 				 PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
+    ScreenPtr pScreen = pDst->drawable.pScreen;
     ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     uint32_t dst_format;
     cb_config_t cb_conf;
     shader_config_t vs_conf, ps_conf;
     struct r600_accel_object src_obj, mask_obj, dst_obj;
-    if (pDst->drawable.bitsPerPixel < 8 || pSrc->drawable.bitsPerPixel < 8)
+    if (pDst->drawable.bitsPerPixel < 8 || (pSrc && pSrc->drawable.bitsPerPixel < 8))
 	return FALSE;
     if (!pSrc) {
 	pSrc = RADEONSolidPixmap(pScreen, pSrcPicture->pSourcePict->solidFill.color);
 	if (!pSrc)
 	    RADEON_FALLBACK("Failed to create solid scratch pixmap\n");
+    }
 #if defined(XF86DRM_MODE)
     if (info->cs) {
 	src_obj.offset = 0;
 	dst_obj.offset = 0;
 	src_obj.bo = radeon_get_pixmap_bo(pSrc);
 	dst_obj.bo = radeon_get_pixmap_bo(pDst);
 	src_obj.bo = radeon_get_pixmap_bo(pSrc);
 	dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
 	src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
 	dst_obj.surface = radeon_get_pixmap_surface(pDst);
 	src_obj.surface = radeon_get_pixmap_surface(pSrc);
     } else
 #endif
+    {
 	src_obj.offset = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset;
 	dst_obj.offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
 	src_obj.bo = NULL;
 	dst_obj.bo = NULL;
+    }
     src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
     dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
     src_obj.width = pSrc->drawable.width;
     src_obj.height = pSrc->drawable.height;
     src_obj.bpp = pSrc->drawable.bitsPerPixel;
     src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
     dst_obj.width = pDst->drawable.width;
     dst_obj.height = pDst->drawable.height;
     dst_obj.bpp = pDst->drawable.bitsPerPixel;
     dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
-    if (pMask) {
+    if (pMaskPicture) {
 	if (!pMask) {
 	    pMask = RADEONSolidPixmap(pScreen, pMaskPicture->pSourcePict->solidFill.color);
 	    if (!pMask) {
 		if (!pSrcPicture->pDrawable)
 		    pScreen->DestroyPixmap(pSrc);
 		RADEON_FALLBACK("Failed to create solid scratch pixmap\n");
+	    }
+	}
 #if defined(XF86DRM_MODE)
 	if (info->cs) {
 	    mask_obj.offset = 0;
 	    mask_obj.bo = radeon_get_pixmap_bo(pMask);
 	    mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
 	    mask_obj.surface = radeon_get_pixmap_surface(pMask);
 	} else
 #endif
+	{
 	    mask_obj.offset = exaGetPixmapOffset(pMask) + info->fbLocation + pScrn->fbOffset;
 	    mask_obj.bo = NULL;
+	}
 	mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
 @@ -1499,61 +1505,75 @@ static Bool R600PrepareComposite(int op,
     if (accel_state->vsync)
 	RADEONVlineHelperClear(pScrn);
     accel_state->composite_op = op;
     accel_state->dst_pic = pDstPicture;
     accel_state->src_pic = pSrcPicture;
     accel_state->dst_pix = pDst;
     accel_state->msk_pix = pMask;
     accel_state->src_pix = pSrc;
     return TRUE;
+}
-static void R600DoneComposite(PixmapPtr pDst)
+static void R600FinishComposite(ScrnInfoPtr pScrn, PixmapPtr pDst,
 				struct radeon_accel_state *accel_state)
+{
     ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     int vtx_size;
     if (accel_state->vsync)
        r600_cp_wait_vline_sync(pScrn, accel_state->ib, pDst,
 			       accel_state->vline_crtc,
 			       accel_state->vline_y1,
 			       accel_state->vline_y2);
     vtx_size = accel_state->msk_pic ? 24 : 16;
     r600_finish_op(pScrn, vtx_size);
+}
 static void R600DoneComposite(PixmapPtr pDst)
+{
     ScreenPtr pScreen = pDst->drawable.pScreen;
     ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     R600FinishComposite(pScrn, pDst, accel_state);
     if (!accel_state->src_pic->pDrawable)
 	pScreen->DestroyPixmap(accel_state->src_pix);
     if (accel_state->msk_pic && !accel_state->msk_pic->pDrawable)
 	pScreen->DestroyPixmap(accel_state->msk_pix);
+}
 static void R600Composite(PixmapPtr pDst,
 			  int srcX, int srcY,
 			  int maskX, int maskY,
 			  int dstX, int dstY,
 			  int w, int h)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     float *vb;
     /* ErrorF("R600Composite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n",
        srcX, srcY, maskX, maskY,dstX, dstY, w, h); */
 #ifdef XF86DRM_MODE
     if (info->cs && CS_FULL(info->cs)) {
-	R600DoneComposite(info->accel_state->dst_pix);
+	R600FinishComposite(pScrn, pDst, info->accel_state);
 	radeon_cs_flush_indirect(pScrn);
 	R600PrepareComposite(info->accel_state->composite_op,
 			     info->accel_state->src_pic,
 			     info->accel_state->msk_pic,
 			     info->accel_state->dst_pic,
 			     info->accel_state->src_pix,
 			     info->accel_state->msk_pix,
 			     info->accel_state->dst_pix);
+    }
 #endif
     if (accel_state->vsync)
 	RADEONVlineHelperSet(pScrn, dstX, dstY, dstX + w, dstY + h);
 @@ -1698,43 +1718,43 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
 	R600DoCopy(pScrn);
 	y += oldhpass;
+    }
     R600IBDiscard(pScrn, scratch);
     return TRUE;
+}
 static Bool
 R600UploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
 		   char *src, int src_pitch)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     uint32_t dst_pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
     uint32_t dst_mc_addr = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset;
     int bpp = pDst->drawable.bitsPerPixel;
     return R600CopyToVRAM(pScrn,
 			  src, src_pitch,
 			  dst_pitch, dst_mc_addr, pDst->drawable.width, pDst->drawable.height, bpp,
 			  x, y, w, h);
+}
 static Bool
 R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
 		       char *dst, int dst_pitch)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pSrc->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     uint32_t src_pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
     uint32_t src_mc_addr = exaGetPixmapOffset(pSrc) + info->fbLocation + pScrn->fbOffset;
     uint32_t src_width = pSrc->drawable.width;
     uint32_t src_height = pSrc->drawable.height;
     int bpp = pSrc->drawable.bitsPerPixel;
     uint32_t scratch_mc_addr;
     int scratch_pitch_bytes = RADEON_ALIGN(dst_pitch, 256);
     int scratch_offset = 0, hpass;
     uint32_t scratch_pitch = scratch_pitch_bytes / (bpp / 8);
     int wpass = w * (bpp/8);
     drmBufPtr scratch;
 @@ -1814,27 +1834,27 @@ R600DownloadFromScreen(PixmapPtr pSrc, i
     R600IBDiscard(pScrn, scratch);
     return TRUE;
+}
 #if defined(XF86DRM_MODE)
 static Bool
 R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
 		     char *src, int src_pitch)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pDst->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     struct radeon_exa_pixmap_priv *driver_priv;
     struct radeon_bo *scratch = NULL;
     struct radeon_bo *copy_dst;
     unsigned char *dst;
     unsigned size;
     uint32_t dst_domain;
     int bpp = pDst->drawable.bitsPerPixel;
     uint32_t scratch_pitch;
     uint32_t copy_pitch;
     uint32_t dst_pitch_hw = exaGetPixmapPitch(pDst) / (bpp / 8);
     int ret;
 @@ -1937,27 +1957,27 @@ copy:
 	R600DoCopyVline(pDst);
+    }
 out:
     if (scratch)
 	radeon_bo_unref(scratch);
     return r;
+}
 static Bool
 R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
 			 int h, char *dst, int dst_pitch)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pSrc->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pSrc->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     struct radeon_exa_pixmap_priv *driver_priv;
     struct radeon_bo *scratch = NULL;
     struct radeon_bo *copy_src;
     unsigned size;
     uint32_t src_domain = 0;
     int bpp = pSrc->drawable.bitsPerPixel;
     uint32_t scratch_pitch;
     uint32_t copy_pitch;
     uint32_t src_pitch_hw = exaGetPixmapPitch(pSrc) / (bpp / 8);
     int ret;
     Bool flush = FALSE;
 @@ -2075,38 +2095,38 @@ copy:
         dst += dst_pitch;
+    }
     radeon_bo_unmap(copy_src);
 out:
     if (scratch)
 	radeon_bo_unref(scratch);
     return r;
+}
 #endif
 static int
 R600MarkSync(ScreenPtr pScreen)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     return ++accel_state->exaSyncMarker;
+}
 static void
 R600Sync(ScreenPtr pScreen, int marker)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     struct radeon_accel_state *accel_state = info->accel_state;
     if (accel_state->exaMarkerSynced != marker) {
 #ifdef XF86DRM_MODE
 #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
 	if (!info->cs)
 #endif
 #endif
 	    RADEONWaitForIdleCP(pScrn);
 	accel_state->exaMarkerSynced = marker;
+    }
 @@ -2206,52 +2226,52 @@ R600LoadShaders(ScrnInfoPtr pScrn)
 #if (EXA_VERSION_MAJOR == 2 && EXA_VERSION_MINOR >= 4)
     if (info->cs) {
 	radeon_bo_unmap(accel_state->shaders_bo);
+    }
 #endif
 #endif
     return TRUE;
+}
 static Bool
 R600PrepareAccess(PixmapPtr pPix, int index)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     /* flush HDP read/write caches */
     OUTREG(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
     return TRUE;
+}
 static void
 R600FinishAccess(PixmapPtr pPix, int index)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pPix->drawable.pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     unsigned char *RADEONMMIO = info->MMIO;
     /* flush HDP read/write caches */
     OUTREG(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+}
 Bool
 R600DrawInit(ScreenPtr pScreen)
+{
-    ScrnInfoPtr pScrn =  xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn =  xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info   = RADEONPTR(pScrn);
     if (info->accel_state->exa == NULL) {
 	xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map not set up\n");
 	return FALSE;
+    }
     info->accel_state->exa->exa_major = EXA_VERSION_MAJOR;
     info->accel_state->exa->exa_minor = EXA_VERSION_MINOR;
     info->accel_state->exa->PrepareSolid = R600PrepareSolid;
     info->accel_state->exa->Solid = R600Solid;
     info->accel_state->exa->DoneSolid = R600DoneSolid;

 @@ -83,27 +83,27 @@ static void RADEONDRIRefreshArea(ScrnInf
 #if (DRIINFO_MAJOR_VERSION > 5 ||		\
      (DRIINFO_MAJOR_VERSION == 5 && DRIINFO_MINOR_VERSION >= 1))
 static void RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num);
 #endif
 #endif
 /* Initialize the visual configs that are supported by the hardware.
  * These are combined with the visual configs that the indirect
  * rendering core supports, and the intersection is exported to the
  * client.
  */
 static Bool RADEONInitVisualConfigs(ScreenPtr pScreen)
+{
-    ScrnInfoPtr          pScrn             = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr          pScrn             = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr        info              = RADEONPTR(pScrn);
     int                  numConfigs        = 0;
     __GLXvisualConfig   *pConfigs          = 0;
     RADEONConfigPrivPtr  pRADEONConfigs    = 0;
     RADEONConfigPrivPtr *pRADEONConfigPtrs = 0;
     int                  i, accum, stencil, db, use_db;
     use_db = !info->dri->noBackBuffer ? 1 : 0;
     switch (info->CurrentLayout.pixel_code) {
     case 8:  /* 8bpp mode is not support */
     case 15: /* FIXME */
     case 24: /* FIXME */
 @@ -309,27 +309,27 @@ static void RADEONDestroyContext(ScreenP
 				 DRIContextType contextStore)
+{
+}
 /* Called when the X server is woken up to allow the last client's
  * context to be saved and the X server's context to be loaded.  This is
  * not necessary for the Radeon since the client detects when it's
  * context is not currently loaded and then load's it itself.  Since the
  * registers to start and stop the CP are privileged, only the X server
  * can start/stop the engine.
  */
 static void RADEONEnterServer(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     drm_radeon_sarea_t *pSAREAPriv;
     RADEON_MARK_SYNC(info, pScrn);
     pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
     if (pSAREAPriv->ctx_owner != DRIGetContext(pScrn->pScreen)) {
 	info->accel_state->XInited3D = FALSE;
 	info->cp->needCacheFlush = (info->ChipFamily >= CHIP_FAMILY_R300);
+    }
 #ifdef DAMAGE
 @@ -351,27 +351,27 @@ static void RADEONEnterServer(ScreenPtr
+    }
 #endif
+}
 /* Called when the X server goes to sleep to allow the X server's
  * context to be saved and the last client's context to be loaded.  This
  * is not necessary for the Radeon since the client detects when it's
  * context is not currently loaded and then load's it itself.  Since the
  * registers to start and stop the CP are privileged, only the X server
  * can start/stop the engine.
  */
 static void RADEONLeaveServer(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     RING_LOCALS;
 #ifdef DAMAGE
     if (info->dri->pDamage) {
 	RegionPtr pDamageReg = DamageRegion(info->dri->pDamage);
 	int nrects = pDamageReg ? REGION_NUM_RECTS(pDamageReg) : 0;
 	if (nrects) {
 	    RADEONDRIRefreshArea(pScrn, pDamageReg);
+	}
+    }
 #endif
 @@ -482,27 +482,27 @@ static void RADEONDRIInitBuffers(WindowP
 /* Copy the back and depth buffers when the X server moves a window.
+ *
  * This routine is a modified form of XAADoBitBlt with the calls to
  * ScreenToScreenBitBlt built in. My routine has the prgnSrc as source
  * instead of destination. My origin is upside down so the ydir cases
  * are reversed.
  */
 static void RADEONDRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
 				 RegionPtr prgnSrc, CARD32 indx)
+{
 #ifdef USE_XAA
     ScreenPtr      pScreen  = pParent->drawable.pScreen;
-    ScrnInfoPtr    pScrn    = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn    = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info     = RADEONPTR(pScrn);
     BoxPtr         pboxTmp, pboxNext, pboxBase;
     DDXPointPtr    pptTmp;
     int            xdir, ydir;
     int            screenwidth = pScrn->virtualX;
     int            screenheight = pScrn->virtualY;
     BoxPtr         pbox     = REGION_RECTS(prgnSrc);
     int            nbox     = REGION_NUM_RECTS(prgnSrc);
     BoxPtr         pboxNew1 = NULL;
 @@ -892,27 +892,27 @@ static Bool RADEONSetAgpMode(RADEONInfoP
 				/* Modify the mode if the default mode
 				 * is not appropriate for this
 				 * particular combination of graphics
 				 * card and AGP chipset.
 				 */
     return TRUE;
+}
 /* Initialize Radeon's AGP registers */
 static void RADEONSetAgpBase(RADEONInfoPtr info, ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     unsigned char *RADEONMMIO = info->MMIO;
     if (info->ChipFamily >= CHIP_FAMILY_R600)
 	return;
     /* drm already does this, so we can probably remove this.
      * agp_base_2 ?
      */
     if (info->ChipFamily == CHIP_FAMILY_RV515)
 	OUTMC(pScrn, RV515_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
     else if ((info->ChipFamily >= CHIP_FAMILY_R520) &&
 	     (info->ChipFamily <= CHIP_FAMILY_RV570))
 	OUTMC(pScrn, R520_MC_AGP_BASE, drmAgpBase(info->dri->drmFD));
 @@ -1163,27 +1163,27 @@ static Bool RADEONDRIMapInit(RADEONInfoP
     if (drmAddMap(info->dri->drmFD, info->MMIOAddr, info->dri->registerSize,
 		  DRM_REGISTERS, DRM_READ_ONLY, &info->dri->registerHandle) < 0) {
 	return FALSE;
+    }
     xf86DrvMsg(pScreen->myNum, X_INFO,
 	       "[drm] register handle = 0x%08lx\n", info->dri->registerHandle);
     return TRUE;
+}
 /* Initialize the kernel data structures */
 static int RADEONDRIKernelInit(RADEONInfoPtr info, ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     int            cpp   = info->CurrentLayout.pixel_bytes;
     drm_radeon_init_t  drmInfo;
     memset(&drmInfo, 0, sizeof(drm_radeon_init_t));
     if ( info->ChipFamily >= CHIP_FAMILY_R600 )
 	drmInfo.func             = RADEON_INIT_R600_CP;
     else if ( info->ChipFamily >= CHIP_FAMILY_R300 )
 	drmInfo.func             = RADEON_INIT_R300_CP;
     else if ( info->ChipFamily >= CHIP_FAMILY_R200 )
 	drmInfo.func		= RADEON_INIT_R200_CP;
     else
 	drmInfo.func		= RADEON_INIT_CP;
 @@ -1270,27 +1270,27 @@ static Bool RADEONDRIBufInit(RADEONInfoP
 	xf86DrvMsg(pScreen->myNum, X_ERROR,
 		   "[drm] Failed to map vertex/indirect buffers list\n");
 	return FALSE;
+    }
     xf86DrvMsg(pScreen->myNum, X_INFO,
 	       "[drm] Mapped %d vertex/indirect buffers\n",
 	       info->dri->buffers->count);
     return TRUE;
+}
 static void RADEONDRIIrqInit(RADEONInfoPtr info, ScreenPtr pScreen)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     if (!info->dri->irq) {
 	info->dri->irq = drmGetInterruptFromBusID(
 	    info->dri->drmFD,
 	    PCI_CFG_BUS(info->PciInfo),
 	    PCI_CFG_DEV(info->PciInfo),
 	    PCI_CFG_FUNC(info->PciInfo));
 	if ((drmCtlInstHandler(info->dri->drmFD, info->dri->irq)) != 0) {
 	    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 		       "[drm] failure adding irq handler, "
 		       "there is a device already using that irq\n"
 		       "[drm] falling back to irq-free operation\n");
 @@ -1514,27 +1514,27 @@ Bool RADEONDRISetVBlankInterrupt(ScrnInf
+	}
+    }
     return TRUE;
+}
 /* Initialize the screen-specific data structures for the DRI and the
  * Radeon.  This is the main entry point to the device-specific
  * initialization code.  It calls device-independent DRI functions to
  * create the DRI data structures and initialize the DRI state.
  */
 Bool RADEONDRIScreenInit(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn   = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn   = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info    = RADEONPTR(pScrn);
     DRIInfoPtr     pDRIInfo;
     RADEONDRIPtr   pRADEONDRI;
     info->dri->DRICloseScreen = NULL;
     switch (info->CurrentLayout.pixel_code) {
     case 8:
     case 15:
     case 24:
 	/* These modes are not supported (yet). */
 	xf86DrvMsg(pScreen->myNum, X_ERROR,
 		   "[dri] RADEONInitVisualConfigs failed "
 @@ -1705,44 +1705,44 @@ Bool RADEONDRIScreenInit(ScreenPtr pScre
+    }
 				/* FIXME: When are these mappings unmapped? */
     if (!RADEONInitVisualConfigs(pScreen)) {
 	RADEONDRICloseScreen(pScreen);
 	return FALSE;
+    }
     xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[dri] Visual configs initialized\n");
     return TRUE;
+}
-static Bool RADEONDRIDoCloseScreen(int scrnIndex, ScreenPtr pScreen)
+static Bool RADEONDRIDoCloseScreen(CLOSE_SCREEN_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     RADEONDRICloseScreen(pScreen);
     pScreen->CloseScreen = info->dri->DRICloseScreen;
-    return (*pScreen->CloseScreen)(scrnIndex, pScreen);
+    return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS);
+}
 /* Finish initializing the device-dependent DRI state, and call
  * DRIFinishScreenInit() to complete the device-independent DRI
  * initialization.
  */
 Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen)
+{
-    ScrnInfoPtr         pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr         pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr       info  = RADEONPTR(pScrn);
     drm_radeon_sarea_t  *pSAREAPriv;
     RADEONDRIPtr        pRADEONDRI;
     info->dri->pDRIInfo->driverSwapMethod = DRI_HIDE_X_CONTEXT;
     /* info->dri->pDRIInfo->driverSwapMethod = DRI_SERVER_SWAP; */
     /* NOTE: DRIFinishScreenInit must be called before *DRIKernelInit
      * because *DRIKernelInit requires that the hardware lock is held by
      * the X server, and the first time the hardware lock is grabbed is
      * in DRIFinishScreenInit.
      */
     if (!DRIFinishScreenInit(pScreen)) {
 @@ -1820,27 +1820,27 @@ Bool RADEONDRIFinishScreenInit(ScreenPtr
     return TRUE;
+}
 /**
  * This function will attempt to get the Radeon hardware back into shape
  * after a resume from disc.
+ *
  * Charl P. Botha <http://cpbotha.net>
  */
 void RADEONDRIResume(ScreenPtr pScreen)
+{
     int _ret;
-    ScrnInfoPtr   pScrn   = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr   pScrn   = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info    = RADEONPTR(pScrn);
     if (info->dri->pKernelDRMVersion->version_minor >= 9) {
 	xf86DrvMsg(pScreen->myNum, X_INFO,
 		   "[RESUME] Attempting to re-init Radeon hardware.\n");
     } else {
 	xf86DrvMsg(pScreen->myNum, X_WARNING,
 		   "[RESUME] Cannot re-init Radeon hardware, DRM too old\n"
 		   "(need 1.9.0  or newer)\n");
 	return;
+    }
     if (info->cardType==CARD_AGP) {
 @@ -1855,50 +1855,50 @@ void RADEONDRIResume(ScreenPtr pScreen)
 	xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		   "%s: CP resume %d\n", __FUNCTION__, _ret);
 	/* FIXME: return? */
+    }
     if (info->ChipFamily < CHIP_FAMILY_R600)
 	RADEONEngineRestore(pScrn);
     RADEONDRICPInit(pScrn);
+}
 void RADEONDRIStop(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     RING_LOCALS;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONDRIStop\n");
     /* Stop the CP */
     if (info->directRenderingInited) {
 	/* If we've generated any CP commands, we must flush them to the
 	 * kernel module now.
 	 */
 	RADEONCP_RELEASE(pScrn, info);
 	RADEONCP_STOP(pScrn, info);
+    }
     info->directRenderingInited = FALSE;
+}
 /* The screen is being closed, so clean up any state and free any
  * resources used by the DRI.
  */
 void RADEONDRICloseScreen(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     drm_radeon_init_t  drmInfo;
      xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		    "RADEONDRICloseScreen\n");
 #ifdef DAMAGE
      REGION_UNINIT(pScreen, &info->dri->driRegion);
 #endif
      if (info->dri->irq) {
 	RADEONDRISetVBlankInterrupt (pScrn, FALSE);
 	drmCtlUninstHandler(info->dri->drmFD);
 @@ -2082,27 +2082,27 @@ static void RADEONDRIRefreshArea(ScrnInf
     info->accel_state->dst_pitch_offset &= ~RADEON_DST_TILE_MACRO;
 #endif
 out:
     REGION_NULL(pScreen, &region);
     DamageEmpty(info->dri->pDamage);
+}
 #endif /* DAMAGE */
 static void RADEONEnablePageFlip(ScreenPtr pScreen)
+{
 #ifdef DAMAGE
-    ScrnInfoPtr         pScrn      = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr         pScrn      = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr       info       = RADEONPTR(pScrn);
     if (info->dri->allowPageFlip) {
 	drm_radeon_sarea_t *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
 	BoxRec box = { .x1 = 0, .y1 = 0, .x2 = pScrn->virtualX - 1,
 		       .y2 = pScrn->virtualY - 1 };
 	RegionPtr pReg = REGION_CREATE(pScreen, &box, 1);
 	pSAREAPriv->pfState = 1;
 	RADEONDRIRefreshArea(pScrn, pReg);
 	REGION_DESTROY(pScreen, pReg);
+    }
 #endif
 @@ -2122,27 +2122,27 @@ static void RADEONDisablePageFlip(Screen
 static void RADEONDRITransitionSingleToMulti3d(ScreenPtr pScreen)
+{
     RADEONDisablePageFlip(pScreen);
+}
 static void RADEONDRITransitionMultiToSingle3d(ScreenPtr pScreen)
+{
     /* Let the remaining 3d app start page flipping again */
     RADEONEnablePageFlip(pScreen);
+}
 static void RADEONDRITransitionTo3d(ScreenPtr pScreen)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
 #ifdef USE_XAA
     FBAreaPtr      fbarea;
     int            width, height;
     /* EXA allocates these areas up front, so it doesn't do the following
      * stuff.
      */
     if (!info->useEXA) {
 	/* reserve offscreen area for back and depth buffers and textures */
 	/* If we still have an area for the back buffer reserved, free it
 	 * first so we always start with all free offscreen memory, except
 @@ -2210,27 +2210,27 @@ static void RADEONDRITransitionTo3d(Scre
     RADEONChangeSurfaces(pScrn);
     RADEONEnablePageFlip(pScreen);
     info->want_vblank_interrupts = TRUE;
     RADEONDRISetVBlankInterrupt(pScrn, TRUE);
     if (info->cursor)
 	xf86ForceHWCursor (pScreen, TRUE);
+}
 static void RADEONDRITransitionTo2d(ScreenPtr pScreen)
+{
-    ScrnInfoPtr         pScrn      = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr         pScrn      = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr       info       = RADEONPTR(pScrn);
     drm_radeon_sarea_t  *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
     /* Try flipping back to the front page if necessary */
     if (pSAREAPriv->pfCurrentPage == 1)
 	drmCommandNone(info->dri->drmFD, DRM_RADEON_FLIP);
     /* Shut down shadowing if we've made it back to the front page */
     if (pSAREAPriv->pfCurrentPage == 0) {
 	RADEONDisablePageFlip(pScreen);
 #ifdef USE_XAA
 	if (!info->useEXA) {
 	    xf86FreeOffscreenArea(info->dri->backArea);
 @@ -2255,50 +2255,50 @@ static void RADEONDRITransitionTo2d(Scre
     info->want_vblank_interrupts = FALSE;
     RADEONDRISetVBlankInterrupt(pScrn, FALSE);
     if (info->cursor)
 	xf86ForceHWCursor (pScreen, FALSE);
+}
 #if defined(DAMAGE) && (DRIINFO_MAJOR_VERSION > 5 ||	\
 			(DRIINFO_MAJOR_VERSION == 5 &&	\
 			 DRIINFO_MINOR_VERSION >= 1))
 static void
 RADEONDRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     REGION_UNINIT(pScreen, &info->dri->driRegion);
     REGION_NULL(pScreen, &info->dri->driRegion);
     if (num > 0) {
 	int i;
 	for (i = 0; i < num; i++) {
 	    WindowPtr pWin = ppWin[i];
 	    if (pWin) {
 		REGION_UNION(pScreen, &info->dri->driRegion, &pWin->clipList,
 			     &info->dri->driRegion);
+	    }
+	}
+    }
+}
 #endif
 void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen)
+{
-    ScrnInfoPtr        pScrn   = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr        pScrn   = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr      info    = RADEONPTR(pScrn);
     if (info->cardType != CARD_PCIE ||
 	info->dri->pKernelDRMVersion->version_minor < 19)
       return;
     if (info->FbSecureSize==0)
       return;
     /* set the old default size of pci gart table */
     if (info->dri->pKernelDRMVersion->version_minor < 26)
       info->dri->pciGartSize = 32768;

 @@ -111,27 +111,27 @@
 #else
 #define DPMS_SERVER
 #include <X11/extensions/dpms.h>
 #endif
 #include "atipciids.h"
 #include "radeon_chipset_gen.h"
 #include "radeon_chipinfo_gen.h"
 				/* Forward definitions for driver functions */
-static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen);
+static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL);
 static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode);
 static void RADEONSave(ScrnInfoPtr pScrn);
 static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 static void
 RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 #ifdef XF86DRI
 static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save);
 #endif
 static const OptionInfoRec RADEONOptions[] = {
 @@ -221,39 +221,39 @@ static int getRADEONEntityIndex(void)
 struct RADEONInt10Save {
 	uint32_t MEM_CNTL;
 	uint32_t MEMSIZE;
 	uint32_t MPP_TB_CONFIG;
 };
 static Bool RADEONMapMMIO(ScrnInfoPtr pScrn);
 static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn);
 static void *
 radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode,
 		   CARD32 *size, void *closure)
+{
-    ScrnInfoPtr pScrn = xf86Screens[screen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(screen);
     RADEONInfoPtr  info   = RADEONPTR(pScrn);
     int stride;
     stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8;
     *size = stride;
     return ((uint8_t *)info->FB + pScrn->fbOffset + row * stride + offset);
+}
 static Bool
 RADEONCreateScreenResources (ScreenPtr pScreen)
+{
-   ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+   ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
    RADEONInfoPtr  info   = RADEONPTR(pScrn);
    PixmapPtr pixmap;
    pScreen->CreateScreenResources = info->CreateScreenResources;
    if (!(*pScreen->CreateScreenResources)(pScreen))
       return FALSE;
    pScreen->CreateScreenResources = RADEONCreateScreenResources;
    if (info->r600_shadow_fb) {
        pixmap = pScreen->GetScreenPixmap(pScreen);
        if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(),
 		      radeonShadowWindow, 0, NULL))
 @@ -3363,35 +3363,34 @@ static void RADEONLoadPalette(ScrnInfoPt
 	  if (crtc->randr_crtc)
 	      RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b);
 	  else
 #endif
 	      crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256);
+      }
+    }
 #ifdef XF86DRI
     if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
 #endif
+}
-static void RADEONBlockHandler(int i, pointer blockData,
+static void RADEONBlockHandler(BLOCKHANDLER_ARGS_DECL)
 			       pointer pTimeout, pointer pReadmask)
+{
-    ScreenPtr      pScreen = screenInfo.screens[i];
+    SCREEN_PTR(arg);
-    ScrnInfoPtr    pScrn   = xf86Screens[i];
+    ScrnInfoPtr    pScrn   = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info    = RADEONPTR(pScrn);
     pScreen->BlockHandler = info->BlockHandler;
-    (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask);
+    (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS);
     pScreen->BlockHandler = RADEONBlockHandler;
     if (info->VideoTimerCallback)
 	(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
 #if defined(RENDER) && defined(USE_XAA)
     if(info->accel_state->RenderCallback)
 	(*info->accel_state->RenderCallback)(pScrn);
 #endif
 #ifdef USE_EXA
     info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;
 #endif
 @@ -3438,30 +3437,29 @@ RADEONInitBIOSRegisters(ScrnInfoPtr pScr
 				 RADEON_ACC_MODE_CHANGE);
 	/* tell the bios a driver is loaded */
 	save->bios_7_scratch |= RADEON_DRV_LOADED;
 	OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch);
 	OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch);
 	//OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch);
+    }
+}
 /* Called at the start of each server generation. */
-Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen,
+Bool RADEONScreenInit(SCREEN_INIT_ARGS_DECL)
                                 int argc, char **argv)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     int            hasDRI = 0;
 #ifdef RENDER
     int            subPixelOrder = SubPixelUnknown;
     char*          s;
 #endif
     info->accelOn      = FALSE;
 #ifdef USE_XAA
     info->accel_state->accel        = NULL;
 #endif
 #ifdef XF86DRI
 @@ -3626,58 +3624,58 @@ Bool RADEONScreenInit(int scrnIndex, Scr
 #if defined(XF86DRI) && defined(USE_XAA)
     if (!info->useEXA && hasDRI) {
 	info->dri->textureSize = -1;
 	if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT,
 				 &(info->dri->textureSize))) {
 	    if (info->dri->textureSize < 0 || info->dri->textureSize > 100) {
 		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 			   "Illegal texture memory percentage: %dx, using default behaviour\n",
 			   info->dri->textureSize);
 		info->dri->textureSize = -1;
+	    }
+	}
-	if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen))
+	if (!RADEONSetupMemXAA_DRI(pScreen))
 	    return FALSE;
     	pScrn->fbOffset    = info->dri->frontOffset;
+    }
 #endif
 #ifdef USE_XAA
-    if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen))
+    if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(pScreen))
 	return FALSE;
 #endif
     info->accel_state->dst_pitch_offset =
 	(((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64)
 	  << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10));
     /* Setup DRI after visuals have been established, but before fbScreenInit is
      * called.  fbScreenInit will eventually call the driver's InitGLXVisuals
      * call back. */
 #ifdef XF86DRI
     if (info->directRenderingEnabled) {
 	/* FIXME: When we move to dynamic allocation of back and depth
 	 * buffers, we will want to revisit the following check for 3
 	 * times the virtual size of the screen below.
 	 */
 	int  width_bytes = (pScrn->displayWidth *
 			    info->CurrentLayout.pixel_bytes);
 	int  maxy        = info->FbMapSize / width_bytes;
 	if (maxy <= pScrn->virtualY * 3) {
-	    xf86DrvMsg(scrnIndex, X_ERROR,
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "Static buffer allocation failed.  Disabling DRI.\n");
-	    xf86DrvMsg(scrnIndex, X_ERROR,
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "At least %d kB of video memory needed at this "
 		       "resolution and depth.\n",
 		       (pScrn->displayWidth * pScrn->virtualY *
 			info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
 	    info->directRenderingEnabled = FALSE;
 	} else {
 	    info->directRenderingEnabled = RADEONDRIScreenInit(pScreen);
+	}
+    }
     /* Tell DRI about new memory map */
     if (info->directRenderingEnabled && info->dri->newMemoryMap) {
         if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) {
 @@ -3807,75 +3805,75 @@ Bool RADEONScreenInit(int scrnIndex, Scr
     if (info->ChipFamily < CHIP_FAMILY_R600) {
         xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
                        "Setting up final surfaces\n");
         RADEONChangeSurfaces(pScrn);
+    }
     /* Enable aceleration */
     if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) {
 	xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		       "Initializing Acceleration\n");
 	if (RADEONAccelInit(pScreen)) {
-	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n");
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n");
 	    info->accelOn = TRUE;
 	} else {
-	    xf86DrvMsg(scrnIndex, X_ERROR,
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "Acceleration initialization failed\n");
-	    xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
 	    info->accelOn = FALSE;
+	}
     } else {
-	xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n");
+	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n");
 	info->accelOn = FALSE;
+    }
     /* Init DPMS */
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "Initializing DPMS\n");
     xf86DPMSInit(pScreen, xf86DPMSSet, 0);
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "Initializing Cursor\n");
     /* Set Silken Mouse */
     xf86SetSilkenMouse(pScreen);
     /* Cursor setup */
     miDCInitialize(pScreen, xf86GetPointerScreenFuncs());
     /* Hardware cursor setup */
     if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) {
 	if (RADEONCursorInit(pScreen)) {
 #ifdef USE_XAA
 	    if (!info->useEXA) {
 		int  width, height;
 		if (xf86QueryLargestOffscreenArea(pScreen, &width, &height,
 , 0, 0)) {
-		    xf86DrvMsg(scrnIndex, X_INFO,
+		    xf86DrvMsg(pScrn->scrnIndex, X_INFO,
 			       "Largest offscreen area available: %d x %d\n",
 			       width, height);
+		}
+	    }
 #endif /* USE_XAA */
 	} else {
-	    xf86DrvMsg(scrnIndex, X_ERROR,
+	    xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
 		       "Hardware cursor initialization failed\n");
-	    xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
+	    xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n");
+	}
     } else {
-	xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n");
+	xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using software cursor\n");
+    }
     /* DGA setup */
 #ifdef XFreeXDGA
     xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset);
 #endif
     /* Init Xv */
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "Initializing Xv\n");
     RADEONInitVideo(pScreen);
     if (info->r600_shadow_fb == TRUE) {
 @@ -5927,47 +5925,47 @@ static void RADEONRestore(ScrnInfoPtr pS
         dce4_restore_vga_regs(pScrn, restore);
     else if (IS_AVIVO_VARIANT)
 	avivo_restore_vga_regs(pScrn, restore);
     else {
 	RADEONRestoreDACRegisters(pScrn, restore);
+    }
 #if 0
     RADEONWaitForVerticalSync(pScrn);
 #endif
+}
 static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode)
+{
-    ScrnInfoPtr  pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr  pScrn = xf86ScreenToScrn(pScreen);
     Bool         unblank;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONSaveScreen(%d)\n", mode);
     unblank = xf86IsUnblank(mode);
     if (unblank) SetTimeSinceLastInputEvent();
     if ((pScrn != NULL) && pScrn->vtSema) {
 	if (unblank)
 	    RADEONUnblank(pScrn);
 	else
 	    RADEONBlank(pScrn);
+    }
     return TRUE;
+}
-Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
+Bool RADEONSwitchMode(SWITCH_MODE_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn       = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr  info        = RADEONPTR(pScrn);
     Bool           tilingOld   = info->tilingEnabled;
     Bool           ret;
 #ifdef XF86DRI
     Bool           CPStarted   = info->cp->CPStarted;
     if (CPStarted) {
 	DRILock(pScrn->pScreen, 0);
 	RADEONCP_STOP(pScrn, info);
+    }
 #endif
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 @@ -5984,29 +5982,29 @@ Bool RADEONSwitchMode(int scrnIndex, Dis
 	    pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
 	    info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE;
+	}
 #endif
+    }
     if (info->accelOn)
         RADEON_SYNC(info, pScrn);
     ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0);
     if (info->tilingEnabled != tilingOld) {
 	/* need to redraw front buffer, I guess this can be considered a hack ? */
-	xf86EnableDisableFBAccess(scrnIndex, FALSE);
+	xf86EnableDisableFBAccess(arg, FALSE);
 	RADEONChangeSurfaces(pScrn);
-	xf86EnableDisableFBAccess(scrnIndex, TRUE);
+	xf86EnableDisableFBAccess(arg, TRUE);
 	/* xf86SetRootClip would do, but can't access that here */
+    }
     if (info->accelOn) {
         RADEON_SYNC(info, pScrn);
 	if (info->ChipFamily < CHIP_FAMILY_R600)
 	    RADEONEngineRestore(pScrn);
+    }
 #ifdef XF86DRI
     if (CPStarted) {
 	RADEONCP_START(pScrn, info);
 	DRIUnlock(pScrn->pScreen);
 @@ -6041,30 +6039,30 @@ xf86ModeBandwidth(DisplayModePtr mode, i
     if (!mode->HTotal || !mode->VTotal || !mode->Clock)
 	return 0;
     a_active = mode->HDisplay * mode->VDisplay;
     a_total = mode->HTotal * mode->VTotal;
     active_percent = a_active / a_total;
     pixels_per_second = active_percent * mode->Clock * 1000.0;
     return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024));
+}
 #endif
 /* Used to disallow modes that are not supported by the hardware */
-ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode,
+ModeStatus RADEONValidMode(SCRN_ARG_TYPE arg, DisplayModePtr mode,
                                      Bool verbose, int flag)
+{
-    ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     /*
      * RN50 has effective maximum mode bandwidth of about 300MiB/s.
      * XXX should really do this for all chips by properly computing
      * memory bandwidth and an overhead factor.
      */
     if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) {
 	if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300)
 	    return MODE_BANDWIDTH;
+    }
 @@ -6148,27 +6146,27 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pSc
+       }
        Base += offset;
+    }
     Base &= ~7;                 /* 3 lower bits are always 0 */
 #ifdef XF86DRI
     if (info->directRenderingInited) {
 	/* note cannot use pScrn->pScreen since this is unitialized when called from
 	   RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */
         /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for
 	 *** pageflipping!
 	 ***/
-	pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]);
+	pSAREAPriv = DRIGetSAREAPrivate(xf86ScrnToScreen(pScrn));
 	/* can't get at sarea in a semi-sane way? */
 	pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec));
 	if (crtc2) {
 	    pSAREAPriv->crtc2_base = Base;
+	}
 	else {
 	    pSAREA->frame.x = (Base  / info->CurrentLayout.pixel_bytes)
 		% info->CurrentLayout.displayWidth;
 	    pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes)
 		/ info->CurrentLayout.displayWidth;
 	    pSAREA->frame.width = pScrn->frameX1 - x + 1;
 	    pSAREA->frame.height = pScrn->frameY1 - y + 1;
 @@ -6179,29 +6177,29 @@ void RADEONDoAdjustFrame(ScrnInfoPtr pSc
+	}
+    }
 #endif
     if (IS_R300_VARIANT || IS_AVIVO_VARIANT) {
 	OUTREG(xytilereg, crtcxytile);
     } else {
 	OUTREG(regcntl, crtcoffsetcntl);
+    }
     OUTREG(reg, Base);
+}
-void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags)
+void RADEONAdjustFrame(ADJUST_FRAME_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn      = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr  info       = RADEONPTR(pScrn);
     RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
     xf86CrtcConfigPtr	config = XF86_CRTC_CONFIG_PTR(pScrn);
     xf86OutputPtr  output = config->output[config->compat_output];
     xf86CrtcPtr	crtc = output->crtc;
     /* not handled */
     if (IS_AVIVO_VARIANT)
 	return;
 #ifdef XF86DRI
     if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0);
 #endif
 @@ -6217,29 +6215,29 @@ void RADEONAdjustFrame(int scrnIndex, in
 	crtc->x = output->initial_x + x;
 	crtc->y = output->initial_y + y;
+    }
 #ifdef XF86DRI
 	if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen);
 #endif
+}
 /* Called when VT switching back to the X server.  Reinitialize the
  * video mode.
  */
-Bool RADEONEnterVT(int scrnIndex, int flags)
+Bool RADEONEnterVT(VT_FUNC_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
     int i;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONEnterVT\n");
     if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */
 	if (info->IsAtomBios) {
 	    rhdAtomASICInit(info->atomBIOS);
 	} else {
 	    xf86Int10InfoPtr pInt;
 @@ -6317,29 +6315,29 @@ Bool RADEONEnterVT(int scrnIndex, int fl
 	RADEONCP_START(pScrn, info);
 	DRIUnlock(pScrn->pScreen);
+    }
 #endif
     if (IS_R500_3D || IS_R300_3D)
 	radeon_load_bicubic_texture(pScrn);
     return TRUE;
+}
 /* Called when VT switching away from the X server.  Restore the
  * original text mode.
  */
-void RADEONLeaveVT(int scrnIndex, int flags)
+void RADEONLeaveVT(VT_FUNC_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
     int i;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONLeaveVT\n");
 #ifdef XF86DRI
     if (RADEONPTR(pScrn)->directRenderingInited) {
 	RADEONDRISetVBlankInterrupt (pScrn, FALSE);
 	DRILock(pScrn->pScreen, 0);
 	RADEONCP_STOP(pScrn, info);
 @@ -6404,29 +6402,29 @@ void RADEONLeaveVT(int scrnIndex, int fl
     RADEONRestore(pScrn);
     for (i = 0; i < config->num_crtc; i++)
 	radeon_crtc_modeset_ioctl(config->crtc[i], FALSE);
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "Ok, leaving now...\n");
+}
 /* Called at the end of each server generation.  Restore the original
  * text mode, unmap video memory, and unwrap and call the saved
  * CloseScreen function.
  */
-static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen)
+static Bool RADEONCloseScreen(CLOSE_SCREEN_ARGS_DECL)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[scrnIndex];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
     int i;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONCloseScreen\n");
     RADEONPMFini(pScrn);
     /* Mark acceleration as stopped or we might try to access the engine at
      * wrong times, especially if we had DRI, after DRI has been stopped
      */
     info->accelOn = FALSE;
 @@ -6489,32 +6487,32 @@ static Bool RADEONCloseScreen(int scrnIn
     if (info->cursor) xf86DestroyCursorInfoRec(info->cursor);
     info->cursor = NULL;
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "Unmapping memory\n");
     RADEONUnmapMem(pScrn);
     pScrn->vtSema = FALSE;
     xf86ClearPrimInitDone(info->pEnt->index);
     pScreen->BlockHandler = info->BlockHandler;
     pScreen->CloseScreen = info->CloseScreen;
-    return (*pScreen->CloseScreen)(scrnIndex, pScreen);
+    return (*pScreen->CloseScreen)(CLOSE_SCREEN_ARGS);
+}
-void RADEONFreeScreen(int scrnIndex, int flags)
+void RADEONFreeScreen(FREE_SCREEN_ARGS_DECL)
+{
-    ScrnInfoPtr  pScrn = xf86Screens[scrnIndex];
+    SCRN_INFO_PTR(arg);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
 		   "RADEONFreeScreen\n");
     /* when server quits at PreInit, we don't need do this anymore*/
     if (!info) return;
 #ifdef WITH_VGAHW
     if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec"))
 	vgaHWFreeHWRec(pScrn);
 #endif
     RADEONFreeRec(pScrn);

 @@ -1142,27 +1142,27 @@ FUNC_NAME(RADEONDisableClipping)(ScrnInf
     FINISH_ACCEL();
     BEGIN_ACCEL(2);
     OUT_ACCEL_REG(RADEON_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL);
     OUT_ACCEL_REG(RADEON_WAIT_UNTIL,
                   RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_DMA_GUI_IDLE);
     FINISH_ACCEL();
     FUNC_NAME(RADEONSetTransparency)(pScrn, info->accel_state->trans_color);
+}
 void
 FUNC_NAME(RADEONAccelInit)(ScreenPtr pScreen, XAAInfoRecPtr a)
+{
-    ScrnInfoPtr    pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr    pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr  info  = RADEONPTR(pScrn);
     a->Flags                            = (PIXMAP_CACHE
 					   | OFFSCREEN_PIXMAPS
 					   | LINEAR_FRAMEBUFFER);
 				/* Sync */
     a->Sync                             = FUNC_NAME(RADEONWaitForIdle);
 				/* Solid Filled Rectangle */
     a->PolyFillRectSolidFlags           = 0;
     a->SetupForSolidFill
 	= FUNC_NAME(RADEONSetupForSolidFill);

 @@ -397,27 +397,27 @@ radeon_crtc_load_cursor_argb (xf86CrtcPt
     CURSOR_SWAPPING_START();
     memcpy (d, image, CURSOR_HEIGHT * CURSOR_WIDTH * 4);
     CURSOR_SWAPPING_END ();
+}
 #endif
 /* Initialize hardware cursor support. */
 Bool RADEONCursorInit(ScreenPtr pScreen)
+{
-    ScrnInfoPtr        pScrn   = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr        pScrn   = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr      info    = RADEONPTR(pScrn);
     unsigned char     *RADEONMMIO = info->MMIO;
     xf86CrtcConfigPtr  xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
     int                c;
     for (c = 0; c < xf86_config->num_crtc; c++) {
 	xf86CrtcPtr crtc = xf86_config->crtc[c];
 	RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
 	if (!info->useEXA) {
 	    int size_bytes  = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
 	    int align = IS_AVIVO_VARIANT ? 4096 : 256;

 @@ -801,27 +801,27 @@ static void radeon_unload_bicubic_textur
     RADEONInfoPtr    info = RADEONPTR(pScrn);
     if (info->bicubic_memory != NULL) {
 	radeon_legacy_free_memory(pScrn, info->bicubic_memory);
 	info->bicubic_memory = NULL;
+    }
+}
 #endif
 XF86VideoAdaptorPtr
 RADEONSetupImageTexturedVideo(ScreenPtr pScreen)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr    info = RADEONPTR(pScrn);
     RADEONPortPrivPtr pPortPriv;
     XF86VideoAdaptorPtr adapt;
     int i;
     int num_texture_ports = 16;
     adapt = calloc(1, sizeof(XF86VideoAdaptorRec) + num_texture_ports *
 		   (sizeof(RADEONPortPrivRec) + sizeof(DevUnion)));
     if (adapt == NULL)
 	return NULL;
     xvBicubic         = MAKE_ATOM("XV_BICUBIC");
     xvVSync           = MAKE_ATOM("XV_VSYNC");

 @@ -61,27 +61,27 @@
 static int
 FUNC_NAME(RADEONMarkSync)(ScreenPtr pScreen)
+{
     RINFO_FROM_SCREEN(pScreen);
     TRACE;
     return ++info->accel_state->exaSyncMarker;
+}
 static void
 FUNC_NAME(RADEONSync)(ScreenPtr pScreen, int marker)
+{
-    ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
+    ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
     RADEONInfoPtr info = RADEONPTR(pScrn);
     if (info->cs)
 	    return;
     TRACE;
     if (info->accel_state->exaMarkerSynced != marker) {
 	FUNC_NAME(RADEONWaitForIdle)(pScrn);
 	info->accel_state->exaMarkerSynced = marker;
+    }
     RADEONPTR(pScrn)->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN;