Sun Oct 7 18:47:07 2012 UTC ()
Fix range ops to properly flush.


(matt)
diff -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs diff -r1.6 -r1.7 src/sys/arch/arm/arm/cpufunc_asm_armv7.S (expand / switch to unified diff)

--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S 2012/09/22 00:33:37 1.6
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S 2012/10/07 18:47:07 1.7
@@ -89,26 +89,30 @@ ENTRY(armv7_setttb) @@ -89,26 +89,30 @@ ENTRY(armv7_setttb)
89 dsb @ data synchronization barrier 89 dsb @ data synchronization barrier
90 isb 90 isb
91 bx lr 91 bx lr
92END(armv7_setttb) 92END(armv7_setttb)
93 93
94/* Cache operations. */ 94/* Cache operations. */
95 95
96/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */ 96/* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */
97ENTRY_NP(armv7_icache_sync_range) 97ENTRY_NP(armv7_icache_sync_range)
98 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR 98 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
99 and r2, r2, #7 @ get line size (log2(size)-4, 0=16) 99 and r2, r2, #7 @ get line size (log2(size)-4, 0=16)
100 mov ip, #16 @ make a bit mask 100 mov ip, #16 @ make a bit mask
101 lsl r2, ip, r2 @ and shift into position 101 lsl r2, ip, r2 @ and shift into position
 102 sub ip, r2, #1 @ make into a mask
 103 and r3, r0, ip @ get offset into cache line
 104 add r1, r1, r3 @ add to length
 105 bic r0, r0, ip @ clear offset from start.
1021: 1061:
103 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache line 107 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache line
104 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line 108 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
105 add r0, r0, r2 109 add r0, r0, r2
106 subs r1, r1, r2 110 subs r1, r1, r2
107 bhi 1b 111 bhi 1b
108 112
109 dsb @ data synchronization barrier 113 dsb @ data synchronization barrier
110 isb 114 isb
111 bx lr 115 bx lr
112END(armv7_icache_sync_range) 116END(armv7_icache_sync_range)
113 117
114/* LINTSTUB: void armv7_icache_sync_all(void); */ 118/* LINTSTUB: void armv7_icache_sync_all(void); */
@@ -121,73 +125,89 @@ ENTRY_NP(armv7_icache_sync_all) @@ -121,73 +125,89 @@ ENTRY_NP(armv7_icache_sync_all)
121 stmdb sp!, {r0, lr} 125 stmdb sp!, {r0, lr}
122 bl _C_LABEL(armv7_idcache_wbinv_all) @clean the D cache 126 bl _C_LABEL(armv7_idcache_wbinv_all) @clean the D cache
123 ldmia sp!, {r0, lr} 127 ldmia sp!, {r0, lr}
124 dsb @ data synchronization barrier 128 dsb @ data synchronization barrier
125 isb 129 isb
126 bx lr 130 bx lr
127END(armv7_icache_sync_all) 131END(armv7_icache_sync_all)
128 132
129ENTRY(armv7_dcache_wb_range) 133ENTRY(armv7_dcache_wb_range)
130 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR 134 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
131 and r2, r2, #7 @ get line size (log2(size)-4, 0=16) 135 and r2, r2, #7 @ get line size (log2(size)-4, 0=16)
132 mov ip, #16 @ make a bit mask 136 mov ip, #16 @ make a bit mask
133 lsl r2, ip, r2 @ and shift into position 137 lsl r2, ip, r2 @ and shift into position
 138 sub ip, r2, #1 @ make into a mask
 139 and r3, r0, ip @ get offset into cache line
 140 add r1, r1, r3 @ add to length
 141 bic r0, r0, ip @ clear offset from start.
1341: 1421:
135 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache to PoC 143 mcr p15, 0, r0, c7, c10, 1 @ wb the D-Cache to PoC
136 add r0, r0, r2 144 add r0, r0, r2
137 subs r1, r1, r2 145 subs r1, r1, r2
138 bhi 1b 146 bhi 1b
139 dsb @ data synchronization barrier 147 dsb @ data synchronization barrier
140 bx lr 148 bx lr
141END(armv7_dcache_wb_range) 149END(armv7_dcache_wb_range)
142 150
143/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */ 151/* LINTSTUB: void armv7_dcache_wbinv_range(vaddr_t, vsize_t); */
144ENTRY(armv7_dcache_wbinv_range) 152ENTRY(armv7_dcache_wbinv_range)
145 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR 153 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
146 and r2, r2, #7 @ get line size (log2(size)-4, 0=16) 154 and r2, r2, #7 @ get line size (log2(size)-4, 0=16)
147 mov ip, #16 @ make a bit mask 155 mov ip, #16 @ make a bit mask
148 lsl r2, ip, r2 @ and shift into position 156 lsl r2, ip, r2 @ and shift into position
 157 sub ip, r2, #1 @ make into a mask
 158 and r3, r0, ip @ get offset into cache line
 159 add r1, r1, r3 @ add to length
 160 bic r0, r0, ip @ clear offset from start.
1491: 1611:
150 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line 162 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
151 add r0, r0, r2 163 add r0, r0, r2
152 subs r1, r1, r2 164 subs r1, r1, r2
153 bhi 1b 165 bhi 1b
154 dsb @ data synchronization barrier 166 dsb @ data synchronization barrier
155 bx lr 167 bx lr
156END(armv7_dcache_wbinv_range) 168END(armv7_dcache_wbinv_range)
157 169
158/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */ 170/* * LINTSTUB: void armv7_dcache_inv_range(vaddr_t, vsize_t); */
159ENTRY(armv7_dcache_inv_range) 171ENTRY(armv7_dcache_inv_range)
160 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR 172 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
161 and r2, r2, #7 @ get line size (log2(size)-4, 0=16) 173 and r2, r2, #7 @ get line size (log2(size)-4, 0=16)
162 mov ip, #16 @ make a bit mask 174 mov ip, #16 @ make a bit mask
163 lsl r2, ip, r2 @ and shift into position 175 lsl r2, ip, r2 @ and shift into position
 176 sub ip, r2, #1 @ make into a mask
 177 and r3, r0, ip @ get offset into cache line
 178 add r1, r1, r3 @ add to length
 179 bic r0, r0, ip @ clear offset from start.
1641: 1801:
165 mcr p15, 0, r0, c7, c6, 1 @ invalidate the D-Cache line  181 mcr p15, 0, r0, c7, c6, 1 @ invalidate the D-Cache line
166 add r0, r0, r2  182 add r0, r0, r2
167 subs r1, r1, r2 183 subs r1, r1, r2
168 bhi 1b 184 bhi 1b
169 185
170 dsb @ data synchronization barrier 186 dsb @ data synchronization barrier
171 bx lr 187 bx lr
172END(armv7_dcache_inv_range) 188END(armv7_dcache_inv_range)
173 189
174 190
175/* * LINTSTUB: void armv7_idcache_wbinv_range(vaddr_t, vsize_t); */ 191/* * LINTSTUB: void armv7_idcache_wbinv_range(vaddr_t, vsize_t); */
176ENTRY(armv7_idcache_wbinv_range) 192ENTRY(armv7_idcache_wbinv_range)
177 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR 193 mrc p15, 1, r2, c0, c0, 0 @ read CCSIDR
178 and r2, r2, #7 @ get line size (log2(size)-4, 0=16) 194 and r2, r2, #7 @ get line size (log2(size)-4, 0=16)
179 mov ip, #16 @ make a bit mask 195 mov ip, #16 @ make a bit mask
180 lsl r2, ip, r2 @ and shift into position 196 lsl r2, ip, r2 @ and shift into position
 197 sub ip, r2, #1 @ make into a mask
 198 and r3, r0, ip @ get offset into cache line
 199 add r1, r1, r3 @ add to length
 200 bic r0, r0, ip @ clear offset from start.
1811: 2011:
182 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line 202 mcr p15, 0, r0, c7, c5, 1 @ invalidate the I-Cache line
183 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line 203 mcr p15, 0, r0, c7, c14, 1 @ wb and inv the D-Cache line
184 add r0, r0, r2 204 add r0, r0, r2
185 subs r1, r1, r2 205 subs r1, r1, r2
186 bhi 1b 206 bhi 1b
187 207
188 dsb @ data synchronization barrier 208 dsb @ data synchronization barrier
189 isb 209 isb
190 bx lr 210 bx lr
191END(armv7_idcache_wbinv_range) 211END(armv7_idcache_wbinv_range)
192 212
193/* * LINTSTUB: void armv7_idcache_wbinv_all(void); */ 213/* * LINTSTUB: void armv7_idcache_wbinv_all(void); */