 @@ -1,14 +1,14 @@
-/*	$NetBSD: cpufunc.c,v 1.116 2012/09/11 17:51:38 matt Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.117 2012/10/19 13:47:03 matt Exp $	*/
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
  * arm8 support code Copyright (c) 1997 ARM Limited
  * arm8 support code Copyright (c) 1997 Causality Limited
  * arm9 support code Copyright (C) 2001 ARM Ltd
  * arm11 support code Copyright (c) 2007 Microsoft
  * cortexa8 support code Copyright (c) 2008 3am Software Foundry
  * cortexa8 improvements Copyright (c) Goeran Weinholt
  * Copyright (c) 1997 Mark Brinicombe.
  * Copyright (c) 1997 Causality Limited
  * All rights reserved.
+ *
 @@ -39,27 +39,27 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
+ *
  * RiscBSD kernel project
+ *
  * cpufuncs.c
+ *
  * C functions for supporting CPU / MMU / TLB specific operations.
+ *
  * Created	: 30/01/97
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.116 2012/09/11 17:51:38 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.117 2012/10/19 13:47:03 matt Exp $");
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
 #include "opt_perfctrs.h"
 #include <sys/types.h>
 #include <sys/param.h>
 #include <sys/pmc.h>
 #include <sys/systm.h>
 #include <machine/cpu.h>
 #include <machine/bootconfig.h>
 #include <arch/arm/arm/disassem.h>
 @@ -1301,27 +1301,27 @@ struct cpu_functions cortex_cpufuncs = {
 	.cf_sdcache_wbinv_range	= (void *)cpufunc_nullop,
 	.cf_sdcache_inv_range	= (void *)cpufunc_nullop,
 	.cf_sdcache_wb_range	= (void *)cpufunc_nullop,
 	.cf_icache_sync_range	= armv7_icache_sync_range,
 	.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
 	.cf_idcache_wbinv_all	= armv7_idcache_wbinv_all,
 	/* Other functions */
 	.cf_flush_prefetchbuf	= cpufunc_nullop,
-	.cf_drain_writebuf	= arm11_drain_writebuf,
+	.cf_drain_writebuf	= armv7_drain_writebuf,
 	.cf_flush_brnchtgt_C	= cpufunc_nullop,
 	.cf_flush_brnchtgt_E	= (void *)cpufunc_nullop,
 	.cf_sleep		= armv7_cpu_sleep,
 	/* Soft functions */
 	.cf_dataabt_fixup	= cpufunc_null_fixup,
 	.cf_prefetchabt_fixup	= cpufunc_null_fixup,
 	.cf_context_switch	= armv7_context_switch,
 	.cf_setup		= armv7_setup

 @@ -64,43 +64,50 @@ END(armv7_context_switch)
 ENTRY(armv7_tlb_flushID_SE)
 #ifdef MULTIPROCESSOR
 	mcr	p15, 0, r0, c8, c3, 1	@ flush I+D tlb single entry
 #else
 	mcr	p15, 0, r0, c8, c7, 1	@ flush I+D tlb single entry
 #endif
 	dsb				@ data synchronization barrier
 	isb
 	bx	lr
 END(armv7_tlb_flushID_SE)
-ENTRY(armv7_setttb)
+ENTRY_NP(armv7_setttb)
 	mrc	p15, 0, r2, c0, c0, 5	@ get MPIDR
 	cmp	r2, #0
 	orrlt	r0, #0x5b		@ MP, cachable (Normal WB)
 	orrge	r0, #0x1b		@ Non-MP, cacheable, normal WB
 	mcr	p15, 0, r0, c2, c0, 0   @ load new TTB
 	cmp	r1, #0
 #ifdef MULTIPROCESSOR
 	mcrne	p15, 0, r0, c8, c3, 0	@ invalidate all I+D TLBs
 #else
 	mcrne	p15, 0, r0, c8, c7, 0   @ invalidate all I+D TLBs
 #endif
 	dsb				@ data synchronization barrier
 	isb
 	bx	lr
 END(armv7_setttb)
 /* Other functions. */
 ENTRY_NP(armv7_drain_writebuf)
 	dsb				@ data synchronization barrier
 	RET
 END(armv7_drain_writebuf)
 /* Cache operations. */
 /* LINTSTUB: void armv7_icache_sync_range(vaddr_t, vsize_t); */
 ENTRY_NP(armv7_icache_sync_range)
 	mrc	p15, 1, r2, c0, c0, 0	@ read CCSIDR
 	and	r2, r2, #7		@ get line size (log2(size)-4, 0=16)
 	mov	ip, #16			@ make a bit mask
 	lsl	r2, ip, r2		@ and shift into position
 	sub	ip, r2, #1		@ make into a mask
 	and	r3, r0, ip		@ get offset into cache line
 	add	r1, r1, r3		@ add to length
 	bic	r0, r0, ip		@ clear offset from start.
 :

 @@ -464,27 +464,28 @@ void	armv7_setttb(u_int, bool);
 void	armv7_icache_sync_range(vaddr_t, vsize_t);
 void	armv7_dcache_wb_range(vaddr_t, vsize_t);
 void	armv7_dcache_wbinv_range(vaddr_t, vsize_t);
 void	armv7_dcache_inv_range(vaddr_t, vsize_t);
 void	armv7_idcache_wbinv_range(vaddr_t, vsize_t);
 void 	armv7_dcache_wbinv_all (void);
 void	armv7_idcache_wbinv_all(void);
 void	armv7_icache_sync_all(void);
 void	armv7_cpu_sleep(int);
 void	armv7_context_switch(u_int);
 void	armv7_tlb_flushID_SE(u_int);
-void	armv7_setup		(char *string);
+void	armv7_drain_writebuf(void);
 void	armv7_setup(char *string);
 #endif
 #if defined(CPU_ARM1136) || defined(CPU_ARM1176)
 void	arm11x6_setttb			(u_int, bool);
 void	arm11x6_idcache_wbinv_all	(void);
 void	arm11x6_dcache_wbinv_all	(void);
 void	arm11x6_icache_sync_all		(void);
 void	arm11x6_flush_prefetchbuf	(void);
 void	arm11x6_icache_sync_range	(vaddr_t, vsize_t);
 void	arm11x6_idcache_wbinv_range	(vaddr_t, vsize_t);
 void	arm11x6_setup			(char *string);
 void	arm11x6_sleep			(int);	/* no ref. for errata */