 @@ -1,1000 +1,1000 @@
-/*	$NetBSD: locore.s,v 1.346 2013/01/23 12:19:02 martin Exp $	*/
+/*	$NetBSD: locore.s,v 1.347 2013/01/23 21:03:25 martin Exp $	*/
 /*
  * Copyright (c) 2006-2010 Matthew R. Green
  * Copyright (c) 1996-2002 Eduardo Horvath
  * Copyright (c) 1996 Paul Kranenburg
  * Copyright (c) 1996
  * 	The President and Fellows of Harvard College.
  *	All rights reserved.
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.
  *	All rights reserved.
+ *
  * This software was developed by the Computer Systems Engineering group
  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
  * contributed to Berkeley.
+ *
  * All advertising materials mentioning features or use of this software
  * must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Lawrence Berkeley Laboratory.
  *	This product includes software developed by Harvard University.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the
  *    distribution.
  * 3. All advertising materials mentioning features or use of this
  *    software must display the following acknowledgement:
  *	This product includes software developed by the University of
  *	California, Berkeley and its contributors.
  *	This product includes software developed by Harvard University.
  *	This product includes software developed by Paul Kranenburg.
  * 4. Neither the name of the University nor the names of its
  *    contributors may be used to endorse or promote products derived
  *    from this software without specific prior written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR
  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  * DAMAGE.
+ *
  *	@(#)locore.s	8.4 (Berkeley) 12/10/93
  */
 #undef	PARANOID		/* Extremely expensive consistency checks */
 #undef	NO_VCACHE		/* Map w/D$ disabled */
 #undef	TRAPSTATS		/* Count traps */
 #undef	TRAPS_USE_IG		/* Use Interrupt Globals for all traps */
 #define	HWREF			/* Track ref/mod bits in trap handlers */
 #undef	DCACHE_BUG		/* Flush D$ around ASI_PHYS accesses */
 #undef	NO_TSB			/* Don't use TSB */
 #define	BB_ERRATA_1		/* writes to TICK_CMPR may fail */
 #undef	TLB_FLUSH_LOWVA		/* also flush 32-bit entries from the MMU */
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
 #include "opt_multiprocessor.h"
 #include "opt_compat_netbsd.h"
 #include "opt_compat_netbsd32.h"
 #include "opt_lockdebug.h"
 #include "assym.h"
 #include <machine/param.h>
 #include <machine/types.h>
 #include <sparc64/sparc64/intreg.h>
 #include <sparc64/sparc64/timerreg.h>
 #include <machine/ctlreg.h>
 #include <machine/psl.h>
 #include <machine/signal.h>
 #include <machine/trap.h>
 #include <machine/frame.h>
 #include <machine/pte.h>
 #include <machine/pmap.h>
 #include <machine/intr.h>
 #include <machine/asm.h>
 #include <machine/locore.h>
 #include <sys/syscall.h>
 #define BLOCK_SIZE SPARC64_BLOCK_SIZE
 #define BLOCK_ALIGN SPARC64_BLOCK_ALIGN
 #include "ksyms.h"
 #if 1
 /*
  * Try to issue an elf note to ask the Solaris
  * bootloader to align the kernel properly.
  */
 	.section	.note
 	.word	0x0d
 	.word	4		! Dunno why
 	.word	1
 :	.asciz	"SUNW Solaris"
 :
 	.align	4
 	.word	0x0400000
 #endif
 	.register	%g2,#scratch
 	.register	%g3,#scratch
 	.data
 	.globl	_C_LABEL(data_start)
 _C_LABEL(data_start):					! Start of data segment
 #ifdef KGDB
 /*
  * Another item that must be aligned, easiest to put it here.
  */
 KGDB_STACK_SIZE = 2048
 	.globl	_C_LABEL(kgdb_stack)
 _C_LABEL(kgdb_stack):
 	.space	KGDB_STACK_SIZE		! hope this is enough
 #endif
 #ifdef NOTDEF_DEBUG
 /*
  * This stack is used when we detect kernel stack corruption.
  */
 	.space	USPACE
 	.align	16
 panicstack:
 #endif
 /*
  * romp is the prom entry pointer
  * romtba is the prom trap table base address
  */
 	.globl	romp
 romp:	POINTER	0
 	.globl	romtba
 romtba:	POINTER	0
 	_ALIGN
 	.text
 /*
  * The v9 trap frame is stored in the special trap registers.  The
  * register window is only modified on window overflow, underflow,
  * and clean window traps, where it points to the register window
  * needing service.  Traps have space for 8 instructions, except for
  * the window overflow, underflow, and clean window traps which are
  * 32 instructions long, large enough to in-line.
+ *
  * The spitfire CPU (Ultra I) has 4 different sets of global registers.
  * (blah blah...)
+ *
  * I used to generate these numbers by address arithmetic, but gas's
  * expression evaluator has about as much sense as your average slug
  * (oddly enough, the code looks about as slimy too).  Thus, all the
  * trap numbers are given as arguments to the trap macros.  This means
  * there is one line per trap.  Sigh.
+ *
  * Hardware interrupt vectors can be `linked'---the linkage is to regular
  * C code---or rewired to fast in-window handlers.  The latter are good
  * for unbuffered hardware like the Zilog serial chip and the AMD audio
  * chip, where many interrupts can be handled trivially with pseudo-DMA
  * or similar.  Only one `fast' interrupt can be used per level, however,
  * and direct and `fast' interrupts are incompatible.  Routines in intr.c
  * handle setting these, with optional paranoia.
  */
 /*
  *	TA8 -- trap align for 8 instruction traps
  *	TA32 -- trap align for 32 instruction traps
  */
 #define TA8	.align 32
 #define TA32	.align 128
 /*
  * v9 trap macros:
+ *
  *	We have a problem with v9 traps; we have no registers to put the
  *	trap type into.  But we do have a %tt register which already has
  *	that information.  Trap types in these macros are all dummys.
  */
 	/* regular vectored traps */
 #define	VTRAP(type, label) \
 	ba,a,pt	%icc,label; nop; NOTREACHED; TA8
 	/* hardware interrupts (can be linked or made `fast') */
 #define	HARDINT4U(lev) \
 	VTRAP(lev, _C_LABEL(sparc_interrupt))
 	/* software interrupts (may not be made direct, sorry---but you
 	   should not be using them trivially anyway) */
 #define	SOFTINT4U(lev, bit) \
 	HARDINT4U(lev)
 	/* traps that just call trap() */
 #define	TRAP(type)	VTRAP(type, slowtrap)
 	/* architecturally undefined traps (cause panic) */
 #ifndef DEBUG
 #define	UTRAP(type)	sir; VTRAP(type, slowtrap)
 #else
 #define	UTRAP(type)	VTRAP(type, slowtrap)
 #endif
 	/* software undefined traps (may be replaced) */
 #define	STRAP(type)	VTRAP(type, slowtrap)
 /* breakpoint acts differently under kgdb */
 #ifdef KGDB
 #define	BPT		VTRAP(T_BREAKPOINT, bpt)
 #define	BPT_KGDB_EXEC	VTRAP(T_KGDB_EXEC, bpt)
 #else
 #define	BPT		TRAP(T_BREAKPOINT)
 #define	BPT_KGDB_EXEC	TRAP(T_KGDB_EXEC)
 #endif
 #define	SYSCALL		VTRAP(0x100, syscall_setup)
 #ifdef notyet
 #define	ZS_INTERRUPT	ba,a,pt %icc, zshard; nop; TA8
 #else
 #define	ZS_INTERRUPT4U	HARDINT4U(12)
 #endif
 /*
  * Macro to clear %tt so we don't get confused with old traps.
  */
 #ifdef DEBUG
 #define CLRTT	wrpr	%g0,0x1ff,%tt
 #else
 #define CLRTT
 #endif
 /*
  * Here are some oft repeated traps as macros.
  */
 	/* spill a 64-bit register window */
 #define SPILL64(label,as) \
 label:	\
 	wr	%g0, as, %asi; \
 	stxa	%l0, [%sp+BIAS+0x00]%asi; \
 	stxa	%l1, [%sp+BIAS+0x08]%asi; \
 	stxa	%l2, [%sp+BIAS+0x10]%asi; \
 	stxa	%l3, [%sp+BIAS+0x18]%asi; \
 	stxa	%l4, [%sp+BIAS+0x20]%asi; \
 	stxa	%l5, [%sp+BIAS+0x28]%asi; \
 	stxa	%l6, [%sp+BIAS+0x30]%asi; \
+	\
 	stxa	%l7, [%sp+BIAS+0x38]%asi; \
 	stxa	%i0, [%sp+BIAS+0x40]%asi; \
 	stxa	%i1, [%sp+BIAS+0x48]%asi; \
 	stxa	%i2, [%sp+BIAS+0x50]%asi; \
 	stxa	%i3, [%sp+BIAS+0x58]%asi; \
 	stxa	%i4, [%sp+BIAS+0x60]%asi; \
 	stxa	%i5, [%sp+BIAS+0x68]%asi; \
 	stxa	%i6, [%sp+BIAS+0x70]%asi; \
+	\
 	stxa	%i7, [%sp+BIAS+0x78]%asi; \
 	saved; \
 	CLRTT; \
 	retry; \
 	NOTREACHED; \
 	TA32
 	/* spill a 32-bit register window */
 #define SPILL32(label,as) \
 label:	\
 	wr	%g0, as, %asi; \
 	srl	%sp, 0, %sp; /* fixup 32-bit pointers */ \
 	stwa	%l0, [%sp+0x00]%asi; \
 	stwa	%l1, [%sp+0x04]%asi; \
 	stwa	%l2, [%sp+0x08]%asi; \
 	stwa	%l3, [%sp+0x0c]%asi; \
 	stwa	%l4, [%sp+0x10]%asi; \
 	stwa	%l5, [%sp+0x14]%asi; \
+	\
 	stwa	%l6, [%sp+0x18]%asi; \
 	stwa	%l7, [%sp+0x1c]%asi; \
 	stwa	%i0, [%sp+0x20]%asi; \
 	stwa	%i1, [%sp+0x24]%asi; \
 	stwa	%i2, [%sp+0x28]%asi; \
 	stwa	%i3, [%sp+0x2c]%asi; \
 	stwa	%i4, [%sp+0x30]%asi; \
 	stwa	%i5, [%sp+0x34]%asi; \
+	\
 	stwa	%i6, [%sp+0x38]%asi; \
 	stwa	%i7, [%sp+0x3c]%asi; \
 	saved; \
 	CLRTT; \
 	retry; \
 	NOTREACHED; \
 	TA32
 	/* Spill either 32-bit or 64-bit register window. */
 #define SPILLBOTH(label64,label32,as) \
 	andcc	%sp, 1, %g0; \
 	bnz,pt	%xcc, label64+4;	/* Is it a v9 or v8 stack? */ \
 	 wr	%g0, as, %asi; \
 	ba,pt	%xcc, label32+8; \
 	 srl	%sp, 0, %sp; /* fixup 32-bit pointers */ \
 	NOTREACHED; \
 	TA32
 	/* fill a 64-bit register window */
 #define FILL64(label,as) \
 label: \
 	wr	%g0, as, %asi; \
 	ldxa	[%sp+BIAS+0x00]%asi, %l0; \
 	ldxa	[%sp+BIAS+0x08]%asi, %l1; \
 	ldxa	[%sp+BIAS+0x10]%asi, %l2; \
 	ldxa	[%sp+BIAS+0x18]%asi, %l3; \
 	ldxa	[%sp+BIAS+0x20]%asi, %l4; \
 	ldxa	[%sp+BIAS+0x28]%asi, %l5; \
 	ldxa	[%sp+BIAS+0x30]%asi, %l6; \
+	\
 	ldxa	[%sp+BIAS+0x38]%asi, %l7; \
 	ldxa	[%sp+BIAS+0x40]%asi, %i0; \
 	ldxa	[%sp+BIAS+0x48]%asi, %i1; \
 	ldxa	[%sp+BIAS+0x50]%asi, %i2; \
 	ldxa	[%sp+BIAS+0x58]%asi, %i3; \
 	ldxa	[%sp+BIAS+0x60]%asi, %i4; \
 	ldxa	[%sp+BIAS+0x68]%asi, %i5; \
 	ldxa	[%sp+BIAS+0x70]%asi, %i6; \
+	\
 	ldxa	[%sp+BIAS+0x78]%asi, %i7; \
 	restored; \
 	CLRTT; \
 	retry; \
 	NOTREACHED; \
 	TA32
 	/* fill a 32-bit register window */
 #define FILL32(label,as) \
 label:	\
 	wr	%g0, as, %asi; \
 	srl	%sp, 0, %sp; /* fixup 32-bit pointers */ \
 	lda	[%sp+0x00]%asi, %l0; \
 	lda	[%sp+0x04]%asi, %l1; \
 	lda	[%sp+0x08]%asi, %l2; \
 	lda	[%sp+0x0c]%asi, %l3; \
 	lda	[%sp+0x10]%asi, %l4; \
 	lda	[%sp+0x14]%asi, %l5; \
+	\
 	lda	[%sp+0x18]%asi, %l6; \
 	lda	[%sp+0x1c]%asi, %l7; \
 	lda	[%sp+0x20]%asi, %i0; \
 	lda	[%sp+0x24]%asi, %i1; \
 	lda	[%sp+0x28]%asi, %i2; \
 	lda	[%sp+0x2c]%asi, %i3; \
 	lda	[%sp+0x30]%asi, %i4; \
 	lda	[%sp+0x34]%asi, %i5; \
+	\
 	lda	[%sp+0x38]%asi, %i6; \
 	lda	[%sp+0x3c]%asi, %i7; \
 	restored; \
 	CLRTT; \
 	retry; \
 	NOTREACHED; \
 	TA32
 	/* fill either 32-bit or 64-bit register window. */
 #define FILLBOTH(label64,label32,as) \
 	andcc	%sp, 1, %i0; \
 	bnz	(label64)+4; /* See if it's a v9 stack or v8 */ \
 	 wr	%g0, as, %asi; \
 	ba	(label32)+8; \
 	 srl	%sp, 0, %sp; /* fixup 32-bit pointers */ \
 	NOTREACHED; \
 	TA32
 	.globl	start, _C_LABEL(kernel_text)
 	_C_LABEL(kernel_text) = kernel_start		! for kvm_mkdb(8)
 kernel_start:
 	/* Traps from TL=0 -- traps from user mode */
 #ifdef __STDC__
 #define TABLE(name)	user_ ## name
 #else
 #define	TABLE(name)	user_/**/name
 #endif
 	.globl	_C_LABEL(trapbase)
 _C_LABEL(trapbase):
 	b dostart; nop; TA8	! 000 = reserved -- Use it to boot
 	/* We should not get the next 5 traps */
 	UTRAP(0x001)		! 001 = POR Reset -- ROM should get this
 	UTRAP(0x002)		! 002 = WDR -- ROM should get this
 	UTRAP(0x003)		! 003 = XIR -- ROM should get this
 	UTRAP(0x004)		! 004 = SIR -- ROM should get this
 	UTRAP(0x005)		! 005 = RED state exception
 	UTRAP(0x006); UTRAP(0x007)
 	VTRAP(T_INST_EXCEPT, textfault)	! 008 = instr. access except
 	VTRAP(T_TEXTFAULT, textfault)	! 009 = instr access MMU miss
 	VTRAP(T_INST_ERROR, textfault)	! 00a = instr. access err
 	UTRAP(0x00b); UTRAP(0x00c); UTRAP(0x00d); UTRAP(0x00e); UTRAP(0x00f)
 	TRAP(T_ILLINST)			! 010 = illegal instruction
 	TRAP(T_PRIVINST)		! 011 = privileged instruction
 	UTRAP(0x012)			! 012 = unimplemented LDD
 	UTRAP(0x013)			! 013 = unimplemented STD
 	UTRAP(0x014); UTRAP(0x015); UTRAP(0x016); UTRAP(0x017); UTRAP(0x018)
 	UTRAP(0x019); UTRAP(0x01a); UTRAP(0x01b); UTRAP(0x01c); UTRAP(0x01d)
 	UTRAP(0x01e); UTRAP(0x01f)
 	TRAP(T_FPDISABLED)		! 020 = fp instr, but EF bit off in psr
 	TRAP(T_FP_IEEE_754)		! 021 = ieee 754 exception
 	TRAP(T_FP_OTHER)		! 022 = other fp exception
 	TRAP(T_TAGOF)			! 023 = tag overflow
 	rdpr %cleanwin, %o7		! 024-027 = clean window trap
 	inc %o7				!	This handler is in-lined and cannot fault
 #ifdef DEBUG
 	set	0xbadcafe, %l0		! DEBUG -- compiler should not rely on zero-ed registers.
 #else
 	clr	%l0
 #endif
 	wrpr %g0, %o7, %cleanwin	!       Nucleus (trap&IRQ) code does not need clean windows
 	mov %l0,%l1; mov %l0,%l2	!	Clear out %l0-%l8 and %o0-%o8 and inc %cleanwin and done
 	mov %l0,%l3; mov %l0,%l4
 #if 0
 #ifdef DIAGNOSTIC
 	!!
 	!! Check the sp redzone
 	!!
 	!! Since we can't spill the current window, we'll just keep
 	!! track of the frame pointer.  Problems occur when the routine
 	!! allocates and uses stack storage.
 	!!
 !	rdpr	%wstate, %l5	! User stack?
 !	cmp	%l5, WSTATE_KERN
 !	bne,pt	%icc, 7f
 	 sethi	%hi(CPCB), %l5
 	LDPTR	[%l5 + %lo(CPCB)], %l5	! If pcb < fp < pcb+sizeof(pcb)
 	inc	PCB_SIZE, %l5		! then we have a stack overflow
 	btst	%fp, 1			! 64-bit stack?
 	sub	%fp, %l5, %l7
 	bnz,a,pt	%icc, 1f
 	 inc	BIAS, %l7		! Remove BIAS
 :
 	cmp	%l7, PCB_SIZE
 	blu	%xcc, cleanwin_overflow
 #endif
 #endif
 	mov %l0, %l5
 	mov %l0, %l6; mov %l0, %l7; mov %l0, %o0; mov %l0, %o1
 	mov %l0, %o2; mov %l0, %o3; mov %l0, %o4; mov %l0, %o5;
 	mov %l0, %o6; mov %l0, %o7
 	CLRTT
 	retry; nop; NOTREACHED; TA32
 	TRAP(T_DIV0)			! 028 = divide by zero
 	UTRAP(0x029)			! 029 = internal processor error
 	UTRAP(0x02a); UTRAP(0x02b); UTRAP(0x02c); UTRAP(0x02d); UTRAP(0x02e); UTRAP(0x02f)
 	VTRAP(T_DATAFAULT, winfault)	! 030 = data fetch fault
 	UTRAP(0x031)			! 031 = data MMU miss -- no MMU
 	VTRAP(T_DATA_ERROR, winfault)	! 032 = data access error
 	VTRAP(T_DATA_PROT, winfault)	! 033 = data protection fault
 	TRAP(T_ALIGN)			! 034 = address alignment error -- we could fix it inline...
 	TRAP(T_LDDF_ALIGN)		! 035 = LDDF address alignment error -- we could fix it inline...
 	TRAP(T_STDF_ALIGN)		! 036 = STDF address alignment error -- we could fix it inline...
 	TRAP(T_PRIVACT)			! 037 = privileged action
 	UTRAP(0x038); UTRAP(0x039); UTRAP(0x03a); UTRAP(0x03b); UTRAP(0x03c);
 	UTRAP(0x03d); UTRAP(0x03e); UTRAP(0x03f);
 	VTRAP(T_ASYNC_ERROR, winfault)	! 040 = data fetch fault
 	SOFTINT4U(1, IE_L1)		! 041 = level 1 interrupt
 	HARDINT4U(2)			! 042 = level 2 interrupt
 	HARDINT4U(3)			! 043 = level 3 interrupt
 	SOFTINT4U(4, IE_L4)		! 044 = level 4 interrupt
 	HARDINT4U(5)			! 045 = level 5 interrupt
 	SOFTINT4U(6, IE_L6)		! 046 = level 6 interrupt
 	HARDINT4U(7)			! 047 = level 7 interrupt
 	HARDINT4U(8)			! 048 = level 8 interrupt
 	HARDINT4U(9)			! 049 = level 9 interrupt
 	HARDINT4U(10)			! 04a = level 10 interrupt
 	HARDINT4U(11)			! 04b = level 11 interrupt
 	ZS_INTERRUPT4U			! 04c = level 12 (zs) interrupt
 	HARDINT4U(13)			! 04d = level 13 interrupt
 	HARDINT4U(14)			! 04e = level 14 interrupt
 	HARDINT4U(15)			! 04f = nonmaskable interrupt
 	UTRAP(0x050); UTRAP(0x051); UTRAP(0x052); UTRAP(0x053); UTRAP(0x054); UTRAP(0x055)
 	UTRAP(0x056); UTRAP(0x057); UTRAP(0x058); UTRAP(0x059); UTRAP(0x05a); UTRAP(0x05b)
 	UTRAP(0x05c); UTRAP(0x05d); UTRAP(0x05e); UTRAP(0x05f)
 	VTRAP(0x060, interrupt_vector); ! 060 = interrupt vector
 	TRAP(T_PA_WATCHPT)		! 061 = physical address data watchpoint
 	TRAP(T_VA_WATCHPT)		! 062 = virtual address data watchpoint
 	TRAP(T_ECCERR)			! 063 = corrected ECC error
 ufast_IMMU_miss:			! 064 = fast instr access MMU miss
 	ldxa	[%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, instr_miss
 #endif
 	ldxa	[%g0] ASI_IMMU, %g1	! Load IMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag:data into %g4:%g5
 	brgez,pn %g5, instr_miss	! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bne,pn %xcc, instr_miss		! Got right tag?
 	 nop
 	CLRTT
 	stxa	%g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
 	retry				! Try new mapping
 :
 	sir
 	TA32
 ufast_DMMU_miss:			! 068 = fast data access MMU miss
 	ldxa	[%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, data_miss
 #endif
 	ldxa	[%g0] ASI_DMMU, %g1	! Load DMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag and data into %g4 and %g5
 	brgez,pn %g5, data_miss		! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bnz,pn	%xcc, data_miss		! Got right tag?
 	 nop
 	CLRTT
 #ifdef TRAPSTATS
 	sethi	%hi(_C_LABEL(udhit)), %g1
 	lduw	[%g1+%lo(_C_LABEL(udhit))], %g2
 	inc	%g2
 	stw	%g2, [%g1+%lo(_C_LABEL(udhit))]
 #endif
 	stxa	%g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
 	retry				! Try new mapping
 :
 	sir
 	TA32
 ufast_DMMU_protection:			! 06c = fast data access MMU protection
 #ifdef TRAPSTATS
 	sethi	%hi(_C_LABEL(udprot)), %g1
 	lduw	[%g1+%lo(_C_LABEL(udprot))], %g2
 	inc	%g2
 	stw	%g2, [%g1+%lo(_C_LABEL(udprot))]
 #endif
 #ifdef HWREF
 	ba,a,pt	%xcc, dmmu_write_fault
 #else
 	ba,a,pt	%xcc, winfault
 #endif
 	nop
 	TA32
 	UTRAP(0x070)			! Implementation dependent traps
 	UTRAP(0x071); UTRAP(0x072); UTRAP(0x073); UTRAP(0x074); UTRAP(0x075); UTRAP(0x076)
 	UTRAP(0x077); UTRAP(0x078); UTRAP(0x079); UTRAP(0x07a); UTRAP(0x07b); UTRAP(0x07c)
 	UTRAP(0x07d); UTRAP(0x07e); UTRAP(0x07f)
 TABLE(uspill):
 	SPILL64(uspill8,ASI_AIUS)	! 0x080 spill_0_normal -- used to save user windows in user mode
 	SPILL32(uspill4,ASI_AIUS)	! 0x084 spill_1_normal
 	SPILLBOTH(uspill8,uspill4,ASI_AIUS)	 ! 0x088 spill_2_normal
 	UTRAP(0x08c); TA32		! 0x08c spill_3_normal
 TABLE(kspill):
 	SPILL64(kspill8,ASI_N)		! 0x090 spill_4_normal -- used to save supervisor windows
 	SPILL32(kspill4,ASI_N)		! 0x094 spill_5_normal
 	SPILLBOTH(kspill8,kspill4,ASI_N) ! 0x098 spill_6_normal
 	UTRAP(0x09c); TA32		! 0x09c spill_7_normal
 TABLE(uspillk):
 	SPILL64(uspillk8,ASI_AIUS)	! 0x0a0 spill_0_other -- used to save user windows in supervisor mode
 	SPILL32(uspillk4,ASI_AIUS)	! 0x0a4 spill_1_other
 	SPILLBOTH(uspillk8,uspillk4,ASI_AIUS) ! 0x0a8 spill_2_other
 	UTRAP(0x0ac); TA32		! 0x0ac spill_3_other
 	UTRAP(0x0b0); TA32		! 0x0b0 spill_4_other
 	UTRAP(0x0b4); TA32		! 0x0b4 spill_5_other
 	UTRAP(0x0b8); TA32		! 0x0b8 spill_6_other
 	UTRAP(0x0bc); TA32		! 0x0bc spill_7_other
 TABLE(ufill):
 	FILL64(ufill8,ASI_AIUS)		! 0x0c0 fill_0_normal -- used to fill windows when running user mode
 	FILL32(ufill4,ASI_AIUS)		! 0x0c4 fill_1_normal
 	FILLBOTH(ufill8,ufill4,ASI_AIUS) ! 0x0c8 fill_2_normal
 	UTRAP(0x0cc); TA32		! 0x0cc fill_3_normal
 TABLE(kfill):
 	FILL64(kfill8,ASI_N)		! 0x0d0 fill_4_normal -- used to fill windows when running supervisor mode
 	FILL32(kfill4,ASI_N)		! 0x0d4 fill_5_normal
 	FILLBOTH(kfill8,kfill4,ASI_N)	! 0x0d8 fill_6_normal
 	UTRAP(0x0dc); TA32		! 0x0dc fill_7_normal
 TABLE(ufillk):
 	FILL64(ufillk8,ASI_AIUS)	! 0x0e0 fill_0_other
 	FILL32(ufillk4,ASI_AIUS)	! 0x0e4 fill_1_other
 	FILLBOTH(ufillk8,ufillk4,ASI_AIUS) ! 0x0e8 fill_2_other
 	UTRAP(0x0ec); TA32		! 0x0ec fill_3_other
 	UTRAP(0x0f0); TA32		! 0x0f0 fill_4_other
 	UTRAP(0x0f4); TA32		! 0x0f4 fill_5_other
 	UTRAP(0x0f8); TA32		! 0x0f8 fill_6_other
 	UTRAP(0x0fc); TA32		! 0x0fc fill_7_other
 TABLE(syscall):
 	SYSCALL				! 0x100 = sun syscall
 	BPT				! 0x101 = pseudo breakpoint instruction
 	STRAP(0x102); STRAP(0x103); STRAP(0x104); STRAP(0x105); STRAP(0x106); STRAP(0x107)
 	SYSCALL				! 0x108 = svr4 syscall
 	SYSCALL				! 0x109 = bsd syscall
 	BPT_KGDB_EXEC			! 0x10a = enter kernel gdb on kernel startup
 	STRAP(0x10b); STRAP(0x10c); STRAP(0x10d); STRAP(0x10e); STRAP(0x10f);
 	STRAP(0x110); STRAP(0x111); STRAP(0x112); STRAP(0x113); STRAP(0x114); STRAP(0x115); STRAP(0x116); STRAP(0x117)
 	STRAP(0x118); STRAP(0x119); STRAP(0x11a); STRAP(0x11b); STRAP(0x11c); STRAP(0x11d); STRAP(0x11e); STRAP(0x11f)
 	STRAP(0x120); STRAP(0x121); STRAP(0x122); STRAP(0x123); STRAP(0x124); STRAP(0x125); STRAP(0x126); STRAP(0x127)
 	STRAP(0x128); STRAP(0x129); STRAP(0x12a); STRAP(0x12b); STRAP(0x12c); STRAP(0x12d); STRAP(0x12e); STRAP(0x12f)
 	STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
 	STRAP(0x138); STRAP(0x139); STRAP(0x13a); STRAP(0x13b); STRAP(0x13c); STRAP(0x13d); STRAP(0x13e); STRAP(0x13f)
 	SYSCALL				! 0x140 SVID syscall (Solaris 2.7)
 	SYSCALL				! 0x141 SPARC International syscall
 	SYSCALL				! 0x142	OS Vendor syscall
 	SYSCALL				! 0x143 HW OEM syscall
 	STRAP(0x144); STRAP(0x145); STRAP(0x146); STRAP(0x147)
 	STRAP(0x148); STRAP(0x149); STRAP(0x14a); STRAP(0x14b); STRAP(0x14c); STRAP(0x14d); STRAP(0x14e); STRAP(0x14f)
 	STRAP(0x150); STRAP(0x151); STRAP(0x152); STRAP(0x153); STRAP(0x154); STRAP(0x155); STRAP(0x156); STRAP(0x157)
 	STRAP(0x158); STRAP(0x159); STRAP(0x15a); STRAP(0x15b); STRAP(0x15c); STRAP(0x15d); STRAP(0x15e); STRAP(0x15f)
 	STRAP(0x160); STRAP(0x161); STRAP(0x162); STRAP(0x163); STRAP(0x164); STRAP(0x165); STRAP(0x166); STRAP(0x167)
 	STRAP(0x168); STRAP(0x169); STRAP(0x16a); STRAP(0x16b); STRAP(0x16c); STRAP(0x16d); STRAP(0x16e); STRAP(0x16f)
 	STRAP(0x170); STRAP(0x171); STRAP(0x172); STRAP(0x173); STRAP(0x174); STRAP(0x175); STRAP(0x176); STRAP(0x177)
 	STRAP(0x178); STRAP(0x179); STRAP(0x17a); STRAP(0x17b); STRAP(0x17c); STRAP(0x17d); STRAP(0x17e); STRAP(0x17f)
 	! Traps beyond 0x17f are reserved
 	UTRAP(0x180); UTRAP(0x181); UTRAP(0x182); UTRAP(0x183); UTRAP(0x184); UTRAP(0x185); UTRAP(0x186); UTRAP(0x187)
 	UTRAP(0x188); UTRAP(0x189); UTRAP(0x18a); UTRAP(0x18b); UTRAP(0x18c); UTRAP(0x18d); UTRAP(0x18e); UTRAP(0x18f)
 	UTRAP(0x190); UTRAP(0x191); UTRAP(0x192); UTRAP(0x193); UTRAP(0x194); UTRAP(0x195); UTRAP(0x196); UTRAP(0x197)
 	UTRAP(0x198); UTRAP(0x199); UTRAP(0x19a); UTRAP(0x19b); UTRAP(0x19c); UTRAP(0x19d); UTRAP(0x19e); UTRAP(0x19f)
 	UTRAP(0x1a0); UTRAP(0x1a1); UTRAP(0x1a2); UTRAP(0x1a3); UTRAP(0x1a4); UTRAP(0x1a5); UTRAP(0x1a6); UTRAP(0x1a7)
 	UTRAP(0x1a8); UTRAP(0x1a9); UTRAP(0x1aa); UTRAP(0x1ab); UTRAP(0x1ac); UTRAP(0x1ad); UTRAP(0x1ae); UTRAP(0x1af)
 	UTRAP(0x1b0); UTRAP(0x1b1); UTRAP(0x1b2); UTRAP(0x1b3); UTRAP(0x1b4); UTRAP(0x1b5); UTRAP(0x1b6); UTRAP(0x1b7)
 	UTRAP(0x1b8); UTRAP(0x1b9); UTRAP(0x1ba); UTRAP(0x1bb); UTRAP(0x1bc); UTRAP(0x1bd); UTRAP(0x1be); UTRAP(0x1bf)
 	UTRAP(0x1c0); UTRAP(0x1c1); UTRAP(0x1c2); UTRAP(0x1c3); UTRAP(0x1c4); UTRAP(0x1c5); UTRAP(0x1c6); UTRAP(0x1c7)
 	UTRAP(0x1c8); UTRAP(0x1c9); UTRAP(0x1ca); UTRAP(0x1cb); UTRAP(0x1cc); UTRAP(0x1cd); UTRAP(0x1ce); UTRAP(0x1cf)
 	UTRAP(0x1d0); UTRAP(0x1d1); UTRAP(0x1d2); UTRAP(0x1d3); UTRAP(0x1d4); UTRAP(0x1d5); UTRAP(0x1d6); UTRAP(0x1d7)
 	UTRAP(0x1d8); UTRAP(0x1d9); UTRAP(0x1da); UTRAP(0x1db); UTRAP(0x1dc); UTRAP(0x1dd); UTRAP(0x1de); UTRAP(0x1df)
 	UTRAP(0x1e0); UTRAP(0x1e1); UTRAP(0x1e2); UTRAP(0x1e3); UTRAP(0x1e4); UTRAP(0x1e5); UTRAP(0x1e6); UTRAP(0x1e7)
 	UTRAP(0x1e8); UTRAP(0x1e9); UTRAP(0x1ea); UTRAP(0x1eb); UTRAP(0x1ec); UTRAP(0x1ed); UTRAP(0x1ee); UTRAP(0x1ef)
 	UTRAP(0x1f0); UTRAP(0x1f1); UTRAP(0x1f2); UTRAP(0x1f3); UTRAP(0x1f4); UTRAP(0x1f5); UTRAP(0x1f6); UTRAP(0x1f7)
 	UTRAP(0x1f8); UTRAP(0x1f9); UTRAP(0x1fa); UTRAP(0x1fb); UTRAP(0x1fc); UTRAP(0x1fd); UTRAP(0x1fe); UTRAP(0x1ff)
 	/* Traps from TL>0 -- traps from supervisor mode */
 #undef TABLE
 #ifdef __STDC__
 #define	TABLE(name)	nucleus_ ## name
 #else
 #define	TABLE(name)	nucleus_/**/name
 #endif
 trapbase_priv:
 	UTRAP(0x000)			! 000 = reserved -- Use it to boot
 	/* We should not get the next 5 traps */
 	UTRAP(0x001)			! 001 = POR Reset -- ROM should get this
 	UTRAP(0x002)			! 002 = WDR Watchdog -- ROM should get this
 	UTRAP(0x003)			! 003 = XIR -- ROM should get this
 	UTRAP(0x004)			! 004 = SIR -- ROM should get this
 	UTRAP(0x005)			! 005 = RED state exception
 	UTRAP(0x006); UTRAP(0x007)
 ktextfault:
 	VTRAP(T_INST_EXCEPT, textfault)	! 008 = instr. access except
 	VTRAP(T_TEXTFAULT, textfault)	! 009 = instr access MMU miss -- no MMU
 	VTRAP(T_INST_ERROR, textfault)	! 00a = instr. access err
 	UTRAP(0x00b); UTRAP(0x00c); UTRAP(0x00d); UTRAP(0x00e); UTRAP(0x00f)
 	TRAP(T_ILLINST)			! 010 = illegal instruction
 	TRAP(T_PRIVINST)		! 011 = privileged instruction
 	UTRAP(0x012)			! 012 = unimplemented LDD
 	UTRAP(0x013)			! 013 = unimplemented STD
 	UTRAP(0x014); UTRAP(0x015); UTRAP(0x016); UTRAP(0x017); UTRAP(0x018)
 	UTRAP(0x019); UTRAP(0x01a); UTRAP(0x01b); UTRAP(0x01c); UTRAP(0x01d)
 	UTRAP(0x01e); UTRAP(0x01f)
 	TRAP(T_FPDISABLED)		! 020 = fp instr, but EF bit off in psr
 	TRAP(T_FP_IEEE_754)		! 021 = ieee 754 exception
 	TRAP(T_FP_OTHER)		! 022 = other fp exception
 	TRAP(T_TAGOF)			! 023 = tag overflow
 	clr	%l0
 #ifdef DEBUG
 	set	0xbadbeef, %l0		! DEBUG
 #endif
 	mov %l0, %l1; mov %l0, %l2	! 024-027 = clean window trap
 	rdpr %cleanwin, %o7		!	This handler is in-lined and cannot fault
 	inc %o7; mov %l0, %l3		!       Nucleus (trap&IRQ) code does not need clean windows
 	wrpr %g0, %o7, %cleanwin	!	Clear out %l0-%l8 and %o0-%o8 and inc %cleanwin and done
 #ifdef NOT_DEBUG
 	!!
 	!! Check the sp redzone
 	!!
 	rdpr	%wstate, t1
 	cmp	t1, WSTATE_KERN
 	bne,pt	icc, 7f
 	 sethi	%hi(_C_LABEL(redzone)), t1
 	ldx	[t1 + %lo(_C_LABEL(redzone))], t2
 	cmp	%sp, t2			! if sp >= t2, not in red zone
 	blu	panic_red		! and can continue normally
 :
 #endif
 	mov %l0, %l4; mov %l0, %l5; mov %l0, %l6; mov %l0, %l7
 	mov %l0, %o0; mov %l0, %o1; mov %l0, %o2; mov %l0, %o3
 	mov %l0, %o4; mov %l0, %o5; mov %l0, %o6; mov %l0, %o7
 	CLRTT
 	retry; nop; TA32
 	TRAP(T_DIV0)			! 028 = divide by zero
 	UTRAP(0x029)			! 029 = internal processor error
 	UTRAP(0x02a); UTRAP(0x02b); UTRAP(0x02c); UTRAP(0x02d); UTRAP(0x02e); UTRAP(0x02f)
 kdatafault:
 	VTRAP(T_DATAFAULT, winfault)	! 030 = data fetch fault
 	UTRAP(0x031)			! 031 = data MMU miss -- no MMU
 	VTRAP(T_DATA_ERROR, winfault)	! 032 = data fetch fault
 	VTRAP(T_DATA_PROT, winfault)	! 033 = data fetch fault
 	VTRAP(T_ALIGN, checkalign)	! 034 = address alignment error -- we could fix it inline...
 	TRAP(T_LDDF_ALIGN)		! 035 = LDDF address alignment error -- we could fix it inline...
 	TRAP(T_STDF_ALIGN)		! 036 = STDF address alignment error -- we could fix it inline...
 	TRAP(T_PRIVACT)			! 037 = privileged action
 	UTRAP(0x038); UTRAP(0x039); UTRAP(0x03a); UTRAP(0x03b); UTRAP(0x03c);
 	UTRAP(0x03d); UTRAP(0x03e); UTRAP(0x03f);
 	VTRAP(T_ASYNC_ERROR, winfault)	! 040 = data fetch fault
 	SOFTINT4U(1, IE_L1)		! 041 = level 1 interrupt
 	HARDINT4U(2)			! 042 = level 2 interrupt
 	HARDINT4U(3)			! 043 = level 3 interrupt
 	SOFTINT4U(4, IE_L4)		! 044 = level 4 interrupt
 	HARDINT4U(5)			! 045 = level 5 interrupt
 	SOFTINT4U(6, IE_L6)		! 046 = level 6 interrupt
 	HARDINT4U(7)			! 047 = level 7 interrupt
 	HARDINT4U(8)			! 048 = level 8 interrupt
 	HARDINT4U(9)			! 049 = level 9 interrupt
 	HARDINT4U(10)			! 04a = level 10 interrupt
 	HARDINT4U(11)			! 04b = level 11 interrupt
 	ZS_INTERRUPT4U			! 04c = level 12 (zs) interrupt
 	HARDINT4U(13)			! 04d = level 13 interrupt
 	HARDINT4U(14)			! 04e = level 14 interrupt
 	HARDINT4U(15)			! 04f = nonmaskable interrupt
 	UTRAP(0x050); UTRAP(0x051); UTRAP(0x052); UTRAP(0x053); UTRAP(0x054); UTRAP(0x055)
 	UTRAP(0x056); UTRAP(0x057); UTRAP(0x058); UTRAP(0x059); UTRAP(0x05a); UTRAP(0x05b)
 	UTRAP(0x05c); UTRAP(0x05d); UTRAP(0x05e); UTRAP(0x05f)
 	VTRAP(0x060, interrupt_vector); ! 060 = interrupt vector
 	TRAP(T_PA_WATCHPT)		! 061 = physical address data watchpoint
 	TRAP(T_VA_WATCHPT)		! 062 = virtual address data watchpoint
 	TRAP(T_ECCERR)			! 063 = corrected ECC error
 kfast_IMMU_miss:			! 064 = fast instr access MMU miss
 	ldxa	[%g0] ASI_IMMU_8KPTR, %g2 ! Load IMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, instr_miss
 #endif
 	ldxa	[%g0] ASI_IMMU, %g1	! Load IMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag:data into %g4:%g5
 	brgez,pn %g5, instr_miss	! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bne,pn %xcc, instr_miss		! Got right tag?
 	 nop
 	CLRTT
 	stxa	%g5, [%g0] ASI_IMMU_DATA_IN ! Enter new mapping
 	retry				! Try new mapping
 :
 	sir
 	TA32
 kfast_DMMU_miss:			! 068 = fast data access MMU miss
 	ldxa	[%g0] ASI_DMMU_8KPTR, %g2! Load DMMU 8K TSB pointer
 #ifdef NO_TSB
 	ba,a	%icc, data_miss
 #endif
 	ldxa	[%g0] ASI_DMMU, %g1	! Load DMMU tag target register
 	ldda	[%g2] ASI_NUCLEUS_QUAD_LDD, %g4	! Load TSB tag and data into %g4 and %g5
 	brgez,pn %g5, data_miss		! Entry invalid?  Punt
 	 cmp	%g1, %g4		! Compare TLB tags
 	bnz,pn	%xcc, data_miss		! Got right tag?
 	 nop
 	CLRTT
 #ifdef TRAPSTATS
 	sethi	%hi(_C_LABEL(kdhit)), %g1
 	lduw	[%g1+%lo(_C_LABEL(kdhit))], %g2
 	inc	%g2
 	stw	%g2, [%g1+%lo(_C_LABEL(kdhit))]
 #endif
 	stxa	%g5, [%g0] ASI_DMMU_DATA_IN ! Enter new mapping
 	retry				! Try new mapping
 :
 	sir
 	TA32
 kfast_DMMU_protection:			! 06c = fast data access MMU protection
 #ifdef TRAPSTATS
 	sethi	%hi(_C_LABEL(kdprot)), %g1
 	lduw	[%g1+%lo(_C_LABEL(kdprot))], %g2
 	inc	%g2
 	stw	%g2, [%g1+%lo(_C_LABEL(kdprot))]
 #endif
 #ifdef HWREF
 	ba,a,pt	%xcc, dmmu_write_fault
 #else
 	ba,a,pt	%xcc, winfault
 #endif
 	nop
 	TA32
 	UTRAP(0x070)			! Implementation dependent traps
 	UTRAP(0x071); UTRAP(0x072); UTRAP(0x073); UTRAP(0x074); UTRAP(0x075); UTRAP(0x076)
 	UTRAP(0x077); UTRAP(0x078); UTRAP(0x079); UTRAP(0x07a); UTRAP(0x07b); UTRAP(0x07c)
 	UTRAP(0x07d); UTRAP(0x07e); UTRAP(0x07f)
 TABLE(uspill):
 	SPILL64(1,ASI_AIUS)		! 0x080 spill_0_normal -- used to save user windows
 	SPILL32(2,ASI_AIUS)		! 0x084 spill_1_normal
 	SPILLBOTH(1b,2b,ASI_AIUS)	! 0x088 spill_2_normal
 	UTRAP(0x08c); TA32		! 0x08c spill_3_normal
 TABLE(kspill):
 	SPILL64(1,ASI_N)		! 0x090 spill_4_normal -- used to save supervisor windows
 	SPILL32(2,ASI_N)		! 0x094 spill_5_normal
 	SPILLBOTH(1b,2b,ASI_N)		! 0x098 spill_6_normal
 	UTRAP(0x09c); TA32		! 0x09c spill_7_normal
 TABLE(uspillk):
 	SPILL64(1,ASI_AIUS)		! 0x0a0 spill_0_other -- used to save user windows in nucleus mode
 	SPILL32(2,ASI_AIUS)		! 0x0a4 spill_1_other
 	SPILLBOTH(1b,2b,ASI_AIUS)	! 0x0a8 spill_2_other
 	UTRAP(0x0ac); TA32		! 0x0ac spill_3_other
 	UTRAP(0x0b0); TA32		! 0x0b0 spill_4_other
 	UTRAP(0x0b4); TA32		! 0x0b4 spill_5_other
 	UTRAP(0x0b8); TA32		! 0x0b8 spill_6_other
 	UTRAP(0x0bc); TA32		! 0x0bc spill_7_other
 TABLE(ufill):
 	FILL64(nufill8,ASI_AIUS)	! 0x0c0 fill_0_normal -- used to fill windows when running nucleus mode from user
 	FILL32(nufill4,ASI_AIUS)	! 0x0c4 fill_1_normal
 	FILLBOTH(nufill8,nufill4,ASI_AIUS) ! 0x0c8 fill_2_normal
 	UTRAP(0x0cc); TA32		! 0x0cc fill_3_normal
 TABLE(sfill):
 	FILL64(sfill8,ASI_N)		! 0x0d0 fill_4_normal -- used to fill windows when running nucleus mode from supervisor
 	FILL32(sfill4,ASI_N)		! 0x0d4 fill_5_normal
 	FILLBOTH(sfill8,sfill4,ASI_N)	! 0x0d8 fill_6_normal
 	UTRAP(0x0dc); TA32		! 0x0dc fill_7_normal
 TABLE(kfill):
 	FILL64(nkfill8,ASI_AIUS)	! 0x0e0 fill_0_other -- used to fill user windows when running nucleus mode -- will we ever use this?
 	FILL32(nkfill4,ASI_AIUS)	! 0x0e4 fill_1_other
 	FILLBOTH(nkfill8,nkfill4,ASI_AIUS)! 0x0e8 fill_2_other
 	UTRAP(0x0ec); TA32		! 0x0ec fill_3_other
 	UTRAP(0x0f0); TA32		! 0x0f0 fill_4_other
 	UTRAP(0x0f4); TA32		! 0x0f4 fill_5_other
 	UTRAP(0x0f8); TA32		! 0x0f8 fill_6_other
 	UTRAP(0x0fc); TA32		! 0x0fc fill_7_other
 TABLE(syscall):
 	SYSCALL				! 0x100 = sun syscall
 	BPT				! 0x101 = pseudo breakpoint instruction
 	STRAP(0x102); STRAP(0x103); STRAP(0x104); STRAP(0x105); STRAP(0x106); STRAP(0x107)
 	SYSCALL				! 0x108 = svr4 syscall
 	SYSCALL				! 0x109 = bsd syscall
 	BPT_KGDB_EXEC			! 0x10a = enter kernel gdb on kernel startup
 	STRAP(0x10b); STRAP(0x10c); STRAP(0x10d); STRAP(0x10e); STRAP(0x10f);
 	STRAP(0x110); STRAP(0x111); STRAP(0x112); STRAP(0x113); STRAP(0x114); STRAP(0x115); STRAP(0x116); STRAP(0x117)
 	STRAP(0x118); STRAP(0x119); STRAP(0x11a); STRAP(0x11b); STRAP(0x11c); STRAP(0x11d); STRAP(0x11e); STRAP(0x11f)
 	STRAP(0x120); STRAP(0x121); STRAP(0x122); STRAP(0x123); STRAP(0x124); STRAP(0x125); STRAP(0x126); STRAP(0x127)
 	STRAP(0x128); STRAP(0x129); STRAP(0x12a); STRAP(0x12b); STRAP(0x12c); STRAP(0x12d); STRAP(0x12e); STRAP(0x12f)
 	STRAP(0x130); STRAP(0x131); STRAP(0x132); STRAP(0x133); STRAP(0x134); STRAP(0x135); STRAP(0x136); STRAP(0x137)
 	STRAP(0x138); STRAP(0x139); STRAP(0x13a); STRAP(0x13b); STRAP(0x13c); STRAP(0x13d); STRAP(0x13e); STRAP(0x13f)
 	STRAP(0x140); STRAP(0x141); STRAP(0x142); STRAP(0x143); STRAP(0x144); STRAP(0x145); STRAP(0x146); STRAP(0x147)
 	STRAP(0x148); STRAP(0x149); STRAP(0x14a); STRAP(0x14b); STRAP(0x14c); STRAP(0x14d); STRAP(0x14e); STRAP(0x14f)
 	STRAP(0x150); STRAP(0x151); STRAP(0x152); STRAP(0x153); STRAP(0x154); STRAP(0x155); STRAP(0x156); STRAP(0x157)
 	STRAP(0x158); STRAP(0x159); STRAP(0x15a); STRAP(0x15b); STRAP(0x15c); STRAP(0x15d); STRAP(0x15e); STRAP(0x15f)
 	STRAP(0x160); STRAP(0x161); STRAP(0x162); STRAP(0x163); STRAP(0x164); STRAP(0x165); STRAP(0x166); STRAP(0x167)
 	STRAP(0x168); STRAP(0x169); STRAP(0x16a); STRAP(0x16b); STRAP(0x16c); STRAP(0x16d); STRAP(0x16e); STRAP(0x16f)
 	STRAP(0x170); STRAP(0x171); STRAP(0x172); STRAP(0x173); STRAP(0x174); STRAP(0x175); STRAP(0x176); STRAP(0x177)
 	STRAP(0x178); STRAP(0x179); STRAP(0x17a); STRAP(0x17b); STRAP(0x17c); STRAP(0x17d); STRAP(0x17e); STRAP(0x17f)
 	! Traps beyond 0x17f are reserved
 	UTRAP(0x180); UTRAP(0x181); UTRAP(0x182); UTRAP(0x183); UTRAP(0x184); UTRAP(0x185); UTRAP(0x186); UTRAP(0x187)
 	UTRAP(0x188); UTRAP(0x189); UTRAP(0x18a); UTRAP(0x18b); UTRAP(0x18c); UTRAP(0x18d); UTRAP(0x18e); UTRAP(0x18f)
 	UTRAP(0x190); UTRAP(0x191); UTRAP(0x192); UTRAP(0x193); UTRAP(0x194); UTRAP(0x195); UTRAP(0x196); UTRAP(0x197)
 	UTRAP(0x198); UTRAP(0x199); UTRAP(0x19a); UTRAP(0x19b); UTRAP(0x19c); UTRAP(0x19d); UTRAP(0x19e); UTRAP(0x19f)
 	UTRAP(0x1a0); UTRAP(0x1a1); UTRAP(0x1a2); UTRAP(0x1a3); UTRAP(0x1a4); UTRAP(0x1a5); UTRAP(0x1a6); UTRAP(0x1a7)
 	UTRAP(0x1a8); UTRAP(0x1a9); UTRAP(0x1aa); UTRAP(0x1ab); UTRAP(0x1ac); UTRAP(0x1ad); UTRAP(0x1ae); UTRAP(0x1af)
 	UTRAP(0x1b0); UTRAP(0x1b1); UTRAP(0x1b2); UTRAP(0x1b3); UTRAP(0x1b4); UTRAP(0x1b5); UTRAP(0x1b6); UTRAP(0x1b7)
 	UTRAP(0x1b8); UTRAP(0x1b9); UTRAP(0x1ba); UTRAP(0x1bb); UTRAP(0x1bc); UTRAP(0x1bd); UTRAP(0x1be); UTRAP(0x1bf)
 	UTRAP(0x1c0); UTRAP(0x1c1); UTRAP(0x1c2); UTRAP(0x1c3); UTRAP(0x1c4); UTRAP(0x1c5); UTRAP(0x1c6); UTRAP(0x1c7)
 	UTRAP(0x1c8); UTRAP(0x1c9); UTRAP(0x1ca); UTRAP(0x1cb); UTRAP(0x1cc); UTRAP(0x1cd); UTRAP(0x1ce); UTRAP(0x1cf)
 	UTRAP(0x1d0); UTRAP(0x1d1); UTRAP(0x1d2); UTRAP(0x1d3); UTRAP(0x1d4); UTRAP(0x1d5); UTRAP(0x1d6); UTRAP(0x1d7)
 	UTRAP(0x1d8); UTRAP(0x1d9); UTRAP(0x1da); UTRAP(0x1db); UTRAP(0x1dc); UTRAP(0x1dd); UTRAP(0x1de); UTRAP(0x1df)
 	UTRAP(0x1e0); UTRAP(0x1e1); UTRAP(0x1e2); UTRAP(0x1e3); UTRAP(0x1e4); UTRAP(0x1e5); UTRAP(0x1e6); UTRAP(0x1e7)
 	UTRAP(0x1e8); UTRAP(0x1e9); UTRAP(0x1ea); UTRAP(0x1eb); UTRAP(0x1ec); UTRAP(0x1ed); UTRAP(0x1ee); UTRAP(0x1ef)
 	UTRAP(0x1f0); UTRAP(0x1f1); UTRAP(0x1f2); UTRAP(0x1f3); UTRAP(0x1f4); UTRAP(0x1f5); UTRAP(0x1f6); UTRAP(0x1f7)
 	UTRAP(0x1f8); UTRAP(0x1f9); UTRAP(0x1fa); UTRAP(0x1fb); UTRAP(0x1fc); UTRAP(0x1fd); UTRAP(0x1fe); UTRAP(0x1ff)
 #if 0
 /*
  * If the cleanwin trap handler detects an overfow we come here.
  * We need to fix up the window registers, switch to the interrupt
  * stack, and then trap to the debugger.
  */
 cleanwin_overflow:
 	!! We've already incremented %cleanwin
 	!! So restore %cwp
 	rdpr	%cwp, %l0
 	dec	%l0
 	wrpr	%l0, %g0, %cwp
 	set	EINTSTACK-STKB-CC64FSZ, %l0
 	save	%l0, 0, %sp
 	ta	1		! Enter debugger
 	sethi	%hi(1f), %o0
 	call	_C_LABEL(panic)
 	 or	%o0, %lo(1f), %o0
 	restore
 	retry
 	.data
 :
 	.asciz	"Kernel stack overflow!"
 	_ALIGN
 	.text
 #endif
 #ifdef NOTDEF_DEBUG
 /*
  * A hardware red zone is impossible.  We simulate one in software by
  * keeping a `red zone' pointer; if %sp becomes less than this, we panic.
  * This is expensive and is only enabled when debugging.
  */
 #define	REDSIZE	(PCB_SIZE)	/* Mark used portion of pcb structure out of bounds */
 #define	REDSTACK 2048		/* size of `panic: stack overflow' region */
 	.data
 	_ALIGN
 redzone:
 	.xword	_C_LABEL(XXX) + REDSIZE
 redstack:
 	.space	REDSTACK
 eredstack:
 Lpanic_red:
 	.asciz	"kernel stack overflow"
 	_ALIGN
 	.text
 	/* set stack pointer redzone to base+minstack; alters base */
 #define	SET_SP_REDZONE(base, tmp) \
 	add	base, REDSIZE, base; \
 	sethi	%hi(_C_LABEL(redzone)), tmp; \
 	stx	base, [tmp + %lo(_C_LABEL(redzone))]
 	/* variant with a constant */
 #define	SET_SP_REDZONE_CONST(const, tmp1, tmp2) \
 	set	(const) + REDSIZE, tmp1; \
 	sethi	%hi(_C_LABEL(redzone)), tmp2; \
 	stx	tmp1, [tmp2 + %lo(_C_LABEL(redzone))]
 	/* check stack pointer against redzone (uses two temps) */
 #define	CHECK_SP_REDZONE(t1, t2) \
 	sethi	KERNBASE, t1;	\
 	cmp	%sp, t1;	\
 	blu,pt	%xcc, 7f;	\
 	 sethi	%hi(_C_LABEL(redzone)), t1; \
 	ldx	[t1 + %lo(_C_LABEL(redzone))], t2; \
 	cmp	%sp, t2;	/* if sp >= t2, not in red zone */ \
 	blu	panic_red; nop;	/* and can continue normally */ \
 :
 panic_red:
 	/* move to panic stack */
 	stx	%g0, [t1 + %lo(_C_LABEL(redzone))];
 	set	eredstack - BIAS, %sp;
 	/* prevent panic() from lowering ipl */
 	sethi	%hi(_C_LABEL(panicstr)), t2;
 	set	Lpanic_red, t2;
 	st	t2, [t1 + %lo(_C_LABEL(panicstr))];
 	wrpr	g0, 15, %pil		/* t1 = splhigh() */
 	save	%sp, -CCF64SZ, %sp;	/* preserve current window */
 	sethi	%hi(Lpanic_red), %o0;
 	call	_C_LABEL(panic);
 	 or %o0, %lo(Lpanic_red), %o0;
 #else
 #define	SET_SP_REDZONE(base, tmp)
 #define	SET_SP_REDZONE_CONST(const, t1, t2)
 #define	CHECK_SP_REDZONE(t1, t2)
 #endif
 #define TRACESIZ	0x01000
 	.globl	_C_LABEL(trap_trace)
 	.globl	_C_LABEL(trap_trace_ptr)
 	.globl	_C_LABEL(trap_trace_end)
 	.globl	_C_LABEL(trap_trace_dis)
 	.data
 _C_LABEL(trap_trace_dis):
 	.word	1, 1		! Starts disabled.  DDB turns it on.
 _C_LABEL(trap_trace_ptr):
 	.word	0, 0, 0, 0
 _C_LABEL(trap_trace):
 	.space	TRACESIZ
 _C_LABEL(trap_trace_end):
 	.space	0x20		! safety margin
 /*
  * v9 machines do not have a trap window.
+ *
  * When we take a trap the trap state is pushed on to the stack of trap
  * registers, interrupts are disabled, then we switch to an alternate set
  * of global registers.
+ *
  * The trap handling code needs to allocate a trap frame on the kernel, or
  * for interrupts, the interrupt stack, save the out registers to the trap
  * frame, then switch to the normal globals and save them to the trap frame
  * too.
+ *
  * XXX it would be good to save the interrupt stack frame to the kernel
  * stack so we wouldn't have to copy it later if we needed to handle a AST.
+ *
  * Since kernel stacks are all on one page and the interrupt stack is entirely
  * within the locked TLB, we can use physical addressing to save out our
  * trap frame so we don't trap during the TRAP_SETUP() operation.  There
  * is unfortunately no supportable method for issuing a non-trapping save.
+ *
  * However, if we use physical addresses to save our trapframe, we will need
  * to clear out the data cache before continuing much further.
+ *
  * In short, what we need to do is:
+ *
 @@ -5287,1015 +5287,1076 @@ ENTRY(softint_fastintr)
 	restore					! rewind register window
 	ld	[%l0 + CI_IDEPTH], %l1
 	STPTR	%l6, [%l0 + CI_EINTSTACK]	! restore ci_eintstack
 	inc	%l1
 	st	%l1, [%l0 + CI_IDEPTH]		! re-adjust ci_idepth
 	wrpr	%g0, %l7, %pil			! restore ipl
 	ret
 	 restore	%g0, 1, %o0
 /*
  * Trampoline function that gets returned to by cpu_switchto() when
  * an interrupt handler blocks.
+ *
  * Arguments:
  *	o0	old lwp from cpu_switchto()
+ *
  * from softint_fastintr():
  *	l0	CPUINFO_VA
  *	l6	saved ci_eintstack
  *	l7	saved ipl
  */
 softint_fastintr_ret:
 	/* re-adjust after mi_switch() */
 	ld	[%l0 + CI_MTX_COUNT], %o1
 	inc	%o1				! ci_mtx_count++
 	st	%o1, [%l0 + CI_MTX_COUNT]
 	st	%g0, [%o0 + L_CTXSWTCH]		! prev->l_ctxswtch = 0
 	ld	[%l0 + CI_IDEPTH], %l1
 	STPTR	%l6, [%l0 + CI_EINTSTACK]	! restore ci_eintstack
 	inc	%l1
 	st	%l1, [%l0 + CI_IDEPTH]		! re-adjust ci_idepth
 	wrpr	%g0, %l7, %pil			! restore ipl
 	ret
 	 restore	%g0, 1, %o0
 #endif /* __HAVE_FAST_SOFTINTS */
 /*
  * Snapshot the current process so that stack frames are up to date.
  * Only used just before a crash dump.
  */
 ENTRY(snapshot)
 	rdpr	%pstate, %o1		! save psr
 	stx	%o7, [%o0 + PCB_PC]	! save pc
 	stx	%o6, [%o0 + PCB_SP]	! save sp
 	rdpr	%pil, %o2
 	sth	%o1, [%o0 + PCB_PSTATE]
 	rdpr	%cwp, %o3
 	stb	%o2, [%o0 + PCB_PIL]
 	stb	%o3, [%o0 + PCB_CWP]
 	flushw
 	save	%sp, -CC64FSZ, %sp
 	flushw
 	ret
 	 restore
 /*
  * cpu_lwp_fork() arranges for lwp_trampoline() to run when the
  * nascent lwp is selected by switch().
+ *
  * The switch frame will contain pointer to struct lwp of this lwp in
  * %l2, a pointer to the function to call in %l0, and an argument to
  * pass to it in %l1 (we abuse the callee-saved registers).
+ *
  * We enter lwp_trampoline as if we are "returning" from
  * cpu_switchto(), so %o0 contains previous lwp (the one we are
  * switching from) that we pass to lwp_startup().
+ *
  * If the function *(%l0) returns, we arrange for an immediate return
  * to user mode.  This happens in two known cases: after execve(2) of
  * init, and when returning a child to user mode after a fork(2).
+ *
  * If were setting up a kernel thread, the function *(%l0) will not
  * return.
  */
 ENTRY(lwp_trampoline)
 	/*
 	 * Note: cpu_lwp_fork() has set up a stack frame for us to run
 	 * in, so we can call other functions from here without using
 	 * `save ... restore'.
 	 */
 	! newlwp in %l2, oldlwp in %o0
 	call    lwp_startup
 	 mov    %l2, %o1
 	call	%l0			! re-use current frame
 	 mov	%l1, %o0
 	/*
 	 * Going to userland - set proper tstate in trap frame
 	 */
 	set	(ASI_PRIMARY_NO_FAULT<<TSTATE_ASI_SHIFT)|((PSTATE_USER)<<TSTATE_PSTATE_SHIFT), %g1
 	stx	%g1, [%sp + CC64FSZ + STKB + TF_TSTATE]
 	/*
 	 * Here we finish up as in syscall, but simplified.
 	 */
 	ba,a,pt	%icc, return_from_trap
 	 nop
 /*
  * pmap_zero_page_phys(pa)
+ *
  * Zero one page physically addressed
+ *
  * Block load/store ASIs do not exist for physical addresses,
  * so we won't use them.
+ *
  * We will execute a flush at the end to sync the I$.
+ *
  * This version expects to have the dcache_flush_page_all(pa)
  * to have been called before calling into here.
  */
 ENTRY(pmap_zero_page_phys)
 #ifndef _LP64
 	COMBINE(%o0, %o1, %o0)
 #endif
 #ifdef DEBUG
 	set	pmapdebug, %o4
 	ld	[%o4], %o4
 	btst	0x80, %o4	! PDB_COPY
 	bz,pt	%icc, 3f
 	 nop
 	save	%sp, -CC64FSZ, %sp
 	set	2f, %o0
 	call	printf
 	 mov	%i0, %o1
 !	ta	1; nop
 	restore
 	.data
 :	.asciz	"pmap_zero_page(%p)\n"
 	_ALIGN
 	.text
 :
 #endif
 	set	NBPG, %o2		! Loop count
 	wr	%g0, ASI_PHYS_CACHED, %asi
 :
 	/* Unroll the loop 8 times */
 	stxa	%g0, [%o0 + 0x00] %asi
 	deccc	0x40, %o2
 	stxa	%g0, [%o0 + 0x08] %asi
 	stxa	%g0, [%o0 + 0x10] %asi
 	stxa	%g0, [%o0 + 0x18] %asi
 	stxa	%g0, [%o0 + 0x20] %asi
 	stxa	%g0, [%o0 + 0x28] %asi
 	stxa	%g0, [%o0 + 0x30] %asi
 	stxa	%g0, [%o0 + 0x38] %asi
 	bg,pt	%icc, 1b
 	 inc	0x40, %o0
 	sethi	%hi(KERNBASE), %o3
 	flush	%o3
 	retl
 	 wr	%g0, ASI_PRIMARY_NOFAULT, %asi	! Make C code happy
 /*
  * pmap_copy_page_phys(paddr_t src, paddr_t dst)
+ *
  * Copy one page physically addressed
  * We need to use a global reg for ldxa/stxa
  * so the top 32-bits cannot be lost if we take
  * a trap and need to save our stack frame to a
  * 32-bit stack.  We will unroll the loop by 4 to
  * improve performance.
+ *
  * This version expects to have the dcache_flush_page_all(pa)
  * to have been called before calling into here.
+ *
  */
 ENTRY(pmap_copy_page_phys)
 #ifndef _LP64
 	COMBINE(%o0, %o1, %o0)
 	COMBINE(%o2, %o3, %o1)
 #endif
 #ifdef DEBUG
 	set	pmapdebug, %o4
 	ld	[%o4], %o4
 	btst	0x80, %o4	! PDB_COPY
 	bz,pt	%icc, 3f
 	 nop
 	save	%sp, -CC64FSZ, %sp
 	mov	%i0, %o1
 	set	2f, %o0
 	call	printf
 	 mov	%i1, %o2
 !	ta	1; nop
 	restore
 	.data
 :	.asciz	"pmap_copy_page(%p,%p)\n"
 	_ALIGN
 	.text
 :
 #endif
 #if 1
 	set	NBPG, %o2
 	wr	%g0, ASI_PHYS_CACHED, %asi
 :
 	ldxa	[%o0 + 0x00] %asi, %g1
 	ldxa	[%o0 + 0x08] %asi, %o3
 	ldxa	[%o0 + 0x10] %asi, %o4
 	ldxa	[%o0 + 0x18] %asi, %o5
 	inc	0x20, %o0
 	deccc	0x20, %o2
 	stxa	%g1, [%o1 + 0x00] %asi
 	stxa	%o3, [%o1 + 0x08] %asi
 	stxa	%o4, [%o1 + 0x10] %asi
 	stxa	%o5, [%o1 + 0x18] %asi
 	bg,pt	%icc, 1b		! We don't care about pages >4GB
 	 inc	0x20, %o1
 	retl
 	 wr	%g0, ASI_PRIMARY_NOFAULT, %asi
 #else
 	set	NBPG, %o3
 	add	%o3, %o0, %o3
 	mov	%g1, %o4		! Save g1
 :
 	ldxa	[%o0] ASI_PHYS_CACHED, %g1
 	inc	8, %o0
 	cmp	%o0, %o3
 	stxa	%g1, [%o1] ASI_PHYS_CACHED
 	bl,pt	%icc, 1b		! We don't care about pages >4GB
 	 inc	8, %o1
 	retl
 	 mov	%o4, %g1		! Restore g1
 #endif
 /*
  * extern int64_t pseg_get_real(struct pmap *pm, vaddr_t addr);
+ *
  * Return TTE at addr in pmap.  Uses physical addressing only.
  * pmap->pm_physaddr must by the physical address of pm_segs
+ *
  */
 ENTRY(pseg_get_real)
 !	flushw			! Make sure we don't have stack probs & lose hibits of %o
 #ifndef _LP64
 	clruw	%o1					! Zero extend
 #endif
 	ldx	[%o0 + PM_PHYS], %o2			! pmap->pm_segs
 	srax	%o1, HOLESHIFT, %o3			! Check for valid address
 	brz,pt	%o3, 0f					! Should be zero or -1
 	 inc	%o3					! Make -1 -> 0
 	brnz,pn	%o3, 1f					! Error! In hole!
 :
 	srlx	%o1, STSHIFT, %o3
 	and	%o3, STMASK, %o3			! Index into pm_segs
 	sll	%o3, 3, %o3
 	add	%o2, %o3, %o2
 	DLFLUSH(%o2,%o3)
 	ldxa	[%o2] ASI_PHYS_CACHED, %o2		! Load page directory pointer
 	DLFLUSH2(%o3)
 	srlx	%o1, PDSHIFT, %o3
 	and	%o3, PDMASK, %o3
 	sll	%o3, 3, %o3
 	brz,pn	%o2, 1f					! NULL entry? check somewhere else
 	 add	%o2, %o3, %o2
 	DLFLUSH(%o2,%o3)
 	ldxa	[%o2] ASI_PHYS_CACHED, %o2		! Load page table pointer
 	DLFLUSH2(%o3)
 	srlx	%o1, PTSHIFT, %o3			! Convert to ptab offset
 	and	%o3, PTMASK, %o3
 	sll	%o3, 3, %o3
 	brz,pn	%o2, 1f					! NULL entry? check somewhere else
 	 add	%o2, %o3, %o2
 	DLFLUSH(%o2,%o3)
 	ldxa	[%o2] ASI_PHYS_CACHED, %o0
 	DLFLUSH2(%o3)
 	brgez,pn %o0, 1f				! Entry invalid?  Punt
 	 btst	1, %sp
 	bz,pn	%icc, 0f				! 64-bit mode?
 	 nop
 	retl						! Yes, return full value
 	 nop
 :
 #if 1
 	srl	%o0, 0, %o1
 	retl						! No, generate a %o0:%o1 double
 	 srlx	%o0, 32, %o0
 #else
 	DLFLUSH(%o2,%o3)
 	ldda	[%o2] ASI_PHYS_CACHED, %o0
 	DLFLUSH2(%o3)
 	retl						! No, generate a %o0:%o1 double
 	 nop
 #endif
 :
 #ifndef _LP64
 	clr	%o1
 #endif
 	retl
 	 clr	%o0
 /*
  * In 32-bit mode:
+ *
  * extern int pseg_set_real(struct pmap* %o0, vaddr_t addr %o1,
  *			    int64_t tte %o2:%o3, paddr_t spare %o4:%o5);
+ *
  * In 64-bit mode:
+ *
  * extern int pseg_set_real(struct pmap* %o0, vaddr_t addr %o1,
  *			    int64_t tte %o2, paddr_t spare %o3);
+ *
  * Set a pseg entry to a particular TTE value.  Return values are:
+ *
  *	-2	addr in hole
  *	0	success	(spare was not used if given)
  *	1	failure	(spare was not given, but one is needed)
  *	2	success	(spare was given, used for L2)
  *	3	failure	(spare was given, used for L2, another is needed for L3)
  *	4	success	(spare was given, used for L3)
+ *
  *	rv == 0	success, spare not used if one was given
  *	rv & 4	spare was used for L3
  *	rv & 2	spare was used for L2
  *	rv & 1	failure, spare is needed
+ *
  * (NB: nobody in pmap checks for the virtual hole, so the system will hang.)
  * The way to call this is:  first just call it without a spare page.
  * If that fails, allocate a page and try again, passing the paddr of the
  * new page as the spare.
  * If spare is non-zero it is assumed to be the address of a zeroed physical
  * page that can be used to generate a directory table or page table if needed.
+ *
  * We keep track of valid (A_TLB_V bit set) and wired (A_TLB_TSB_LOCK bit set)
  * mappings that are set here. We check both bits on the new data entered
  * and increment counts, as well as decrementing counts if the bits are set
  * in the value replaced by this call.
  * The counters are 32 bit or 64 bit wide, depending on the kernel type we are
  * running!
  */
 ENTRY(pseg_set_real)
 #ifndef _LP64
 	clruw	%o1					! Zero extend
 	COMBINE(%o2, %o3, %o2)
 	COMBINE(%o4, %o5, %o3)
 #endif
 	!!
 	!! However we managed to get here we now have:
 	!!
 	!! %o0 = *pmap
 	!! %o1 = addr
 	!! %o2 = tte
 	!! %o3 = paddr of spare page
 	!!
 	srax	%o1, HOLESHIFT, %o4			! Check for valid address
 	brz,pt	%o4, 0f					! Should be zero or -1
 	 inc	%o4					! Make -1 -> 0
 	brz,pt	%o4, 0f
 	 nop
 #ifdef DEBUG
 	ta	1					! Break into debugger
 #endif
 	retl
 	 mov -2, %o0					! Error -- in hole!
 :
 	ldx	[%o0 + PM_PHYS], %o4			! pmap->pm_segs
 	clr	%g1
 	srlx	%o1, STSHIFT, %o5
 	and	%o5, STMASK, %o5
 	sll	%o5, 3, %o5
 	add	%o4, %o5, %o4
 :
 	DLFLUSH(%o4,%g5)
 	ldxa	[%o4] ASI_PHYS_CACHED, %o5		! Load page directory pointer
 	DLFLUSH2(%g5)
 	brnz,a,pt %o5, 0f				! Null pointer?
 	 mov	%o5, %o4
 	brz,pn	%o3, 9f					! Have a spare?
 	 mov	%o3, %o5
 	casxa	[%o4] ASI_PHYS_CACHED, %g0, %o5
 	brnz,pn	%o5, 0b					! Something changed?
 	DLFLUSH(%o4, %o5)
 	mov	%o3, %o4
 	mov	2, %g1					! record spare used for L2
 	clr	%o3					! and not available for L3
 :
 	srlx	%o1, PDSHIFT, %o5
 	and	%o5, PDMASK, %o5
 	sll	%o5, 3, %o5
 	add	%o4, %o5, %o4
 :
 	DLFLUSH(%o4,%g5)
 	ldxa	[%o4] ASI_PHYS_CACHED, %o5		! Load table directory pointer
 	DLFLUSH2(%g5)
 	brnz,a,pt %o5, 0f				! Null pointer?
 	 mov	%o5, %o4
 	brz,pn	%o3, 9f					! Have a spare?
 	 mov	%o3, %o5
 	casxa	[%o4] ASI_PHYS_CACHED, %g0, %o5
 	brnz,pn	%o5, 0b					! Something changed?
 	DLFLUSH(%o4, %o4)
 	mov	%o3, %o4
 	mov	4, %g1					! record spare used for L3
 :
 	srlx	%o1, PTSHIFT, %o5			! Convert to ptab offset
 	and	%o5, PTMASK, %o5
 	sll	%o5, 3, %o5
 	add	%o5, %o4, %o4
 	DLFLUSH(%o4,%g5)
 	ldxa	[%o4] ASI_PHYS_CACHED, %o5		! save old value in %o5
 	stxa	%o2, [%o4] ASI_PHYS_CACHED		! Easier than shift+or
 	DLFLUSH2(%g5)
 	!! at this point we have:
 	!!  %g1 = return value
 	!!  %o0 = struct pmap * (where the counts are)
 	!!  %o2 = new TTE
 	!!  %o5 = old TTE
 	!! see if stats needs an update
 	set	A_TLB_TSB_LOCK, %g5
 	xor	%o2, %o5, %o3			! %o3 - what changed
 	brgez,pn %o3, 5f			! has resident changed? (we predict it has)
 	 btst	%g5, %o3			! has wired changed?
 	LDPTR	[%o0 + PM_RESIDENT], %o1	! gonna update resident count
 	brlz	%o2, 0f
 	 mov	1, %o4
 	neg	%o4				! new is not resident -> decrement
 :	add	%o1, %o4, %o1
 	STPTR	%o1, [%o0 + PM_RESIDENT]
 	btst	%g5, %o3			! has wired changed?
 :	bz,pt	%xcc, 8f			! we predict it's not
 	 btst	%g5, %o2			! don't waste delay slot, check if new one is wired
 	LDPTR	[%o0 + PM_WIRED], %o1		! gonna update wired count
 	bnz,pt	%xcc, 0f			! if wired changes, we predict it increments
 	 mov	1, %o4
 	neg	%o4				! new is not wired -> decrement
 :	add	%o1, %o4, %o1
 	STPTR	%o1, [%o0 + PM_WIRED]
 :	retl
 	 mov	%g1, %o0			! return %g1
 :	retl
 	 or	%g1, 1, %o0			! spare needed, return flags + 1
 /*
  * clearfpstate()
+ *
  * Drops the current fpu state, without saving it.
  */
 ENTRY(clearfpstate)
 	rdpr	%pstate, %o1		! enable FPU
 	wr	%g0, FPRS_FEF, %fprs
 	or	%o1, PSTATE_PEF, %o1
 	retl
 	 wrpr	%o1, 0, %pstate
 /*
  * savefpstate(f) struct fpstate *f;
+ *
  * Store the current FPU state.
+ *
  * Since the kernel may need to use the FPU and we have problems atomically
  * testing and enabling the FPU, we leave here with the FPRS_FEF bit set.
  * Normally this should be turned on in loadfpstate().
  */
  /* XXXXXXXXXX  Assume caller created a proper stack frame */
 ENTRY(savefpstate)
 !	flushw			! Make sure we don't have stack probs & lose hibits of %o
 	rdpr	%pstate, %o1		! enable FP before we begin
 	rd	%fprs, %o5
 	wr	%g0, FPRS_FEF, %fprs
 	or	%o1, PSTATE_PEF, %o1
 	wrpr	%o1, 0, %pstate
 	stx	%fsr, [%o0 + FS_FSR]	! f->fs_fsr = getfsr();
 	rd	%gsr, %o4		! Save %gsr
 	st	%o4, [%o0 + FS_GSR]
 	add	%o0, FS_REGS, %o2
 #ifdef DIAGNOSTIC
 	btst	BLOCK_ALIGN, %o2	! Needs to be re-executed
 	bnz,pn	%icc, 6f		! Check alignment
 #endif
 	 st	%g0, [%o0 + FS_QSIZE]	! f->fs_qsize = 0;
 	btst	FPRS_DL|FPRS_DU, %o5	! Both FPU halves clean?
 	bz,pt	%icc, 5f		! Then skip it
 	 btst	FPRS_DL, %o5		! Lower FPU clean?
 	membar	#Sync
 	bz,a,pt	%icc, 1f		! Then skip it, but upper FPU not clean
 	 add	%o2, 2*BLOCK_SIZE, %o2	! Skip a block
 	stda	%f0, [%o2] ASI_BLK_P	! f->fs_f0 = etc;
 	inc	BLOCK_SIZE, %o2
 	stda	%f16, [%o2] ASI_BLK_P
 	btst	FPRS_DU, %o5		! Upper FPU clean?
 	bz,pt	%icc, 2f		! Then skip it
 	 inc	BLOCK_SIZE, %o2
 :
 	stda	%f32, [%o2] ASI_BLK_P
 	inc	BLOCK_SIZE, %o2
 	stda	%f48, [%o2] ASI_BLK_P
 :
 	membar	#Sync			! Finish operation so we can
 :
 	retl
 	 wr	%g0, FPRS_FEF, %fprs	! Mark FPU clean
 #ifdef DIAGNOSTIC
 	!!
 	!! Damn thing is *NOT* aligned on a 64-byte boundary
 	!!
 :
 	wr	%g0, FPRS_FEF, %fprs
 	! XXX -- we should panic instead of silently entering debugger
 	ta	1
 	retl
 	 nop
 #endif
 /*
  * Load FPU state.
  */
  /* XXXXXXXXXX  Should test to see if we only need to do a partial restore */
 ENTRY(loadfpstate)
 	flushw			! Make sure we don't have stack probs & lose hibits of %o
 	rdpr	%pstate, %o1		! enable FP before we begin
 	ld	[%o0 + FS_GSR], %o4	! Restore %gsr
 	set	PSTATE_PEF, %o2
 	wr	%g0, FPRS_FEF, %fprs
 	or	%o1, %o2, %o1
 	wrpr	%o1, 0, %pstate
 	ldx	[%o0 + FS_FSR], %fsr	! setfsr(f->fs_fsr);
 	add	%o0, FS_REGS, %o3	! This is zero...
 #ifdef DIAGNOSTIC
 	btst	BLOCK_ALIGN, %o3
 	bne,pn	%icc, 1f	! Only use block loads on aligned blocks
 #endif
 	 wr	%o4, %g0, %gsr
 	membar	#Sync
 	ldda	[%o3] ASI_BLK_P, %f0
 	inc	BLOCK_SIZE, %o3
 	ldda	[%o3] ASI_BLK_P, %f16
 	inc	BLOCK_SIZE, %o3
 	ldda	[%o3] ASI_BLK_P, %f32
 	inc	BLOCK_SIZE, %o3
 	ldda	[%o3] ASI_BLK_P, %f48
 	membar	#Sync			! Make sure loads are complete
 	retl
 	 wr	%g0, FPRS_FEF, %fprs	! Clear dirty bits
 #ifdef DIAGNOSTIC
 	!!
 	!! Damn thing is *NOT* aligned on a 64-byte boundary
 	!!
 :
 	wr	%g0, FPRS_FEF, %fprs	! Clear dirty bits
 	! XXX -- we should panic instead of silently entering debugger
 	ta	1
 	retl
 	 nop
 #endif
 /*
  * ienab_bis(bis) int bis;
  * ienab_bic(bic) int bic;
+ *
  * Set and clear bits in the interrupt register.
  */
 /*
  * sun4u has separate asr's for clearing/setting the interrupt mask.
  */
 ENTRY(ienab_bis)
 	retl
 	 wr	%o0, 0, SET_SOFTINT	! SET_SOFTINT
 ENTRY(ienab_bic)
 	retl
 	 wr	%o0, 0, CLEAR_SOFTINT	! CLEAR_SOFTINT
 /*
  * send_softint(cpu, level, intrhand)
+ *
  * Send a softint with an intrhand pointer so we can cause a vectored
  * interrupt instead of a polled interrupt.  This does pretty much the same
  * as interrupt_vector.  If cpu is -1 then send it to this CPU, if it's -2
  * send it to any CPU, otherwise send it to a particular CPU.
+ *
  * XXXX Dispatching to different CPUs is not implemented yet.
  */
 ENTRY(send_softint)
 	rdpr	%pstate, %g1
 	andn	%g1, PSTATE_IE, %g2	! clear PSTATE.IE
 	wrpr	%g2, 0, %pstate
 	sethi	%hi(CPUINFO_VA+CI_INTRPENDING), %o3
 	LDPTR	[%o2 + IH_PEND], %o5
 	or	%o3, %lo(CPUINFO_VA+CI_INTRPENDING), %o3
 	brnz	%o5, 1f
 	 sll	%o1, PTRSHFT, %o5	! Find start of table for this IPL
 	add	%o3, %o5, %o3
 :
 	LDPTR	[%o3], %o5		! Load list head
 	STPTR	%o5, [%o2+IH_PEND]	! Link our intrhand node in
 	mov	%o2, %o4
 	CASPTR	[%o3] ASI_N, %o5, %o4
 	cmp	%o4, %o5		! Did it work?
 	bne,pn	CCCR, 2b		! No, try again
 	 .empty
 	mov	1, %o4			! Change from level to bitmask
 	sllx	%o4, %o1, %o4
 	wr	%o4, 0, SET_SOFTINT	! SET_SOFTINT
 :
 	retl
 	 wrpr	%g1, 0, %pstate		! restore PSTATE.IE
 #define MICROPERSEC	(1000000)
 /*
  * delay function
+ *
  * void delay(N)  -- delay N microseconds
+ *
  * Register usage: %o0 = "N" number of usecs to go (counts down to zero)
  *		   %o1 = "timerblurb" (stays constant)
  *		   %o2 = counter for 1 usec (counts down from %o1 to zero)
+ *
+ *
  *	ci_cpu_clockrate should be tuned during CPU probe to the CPU
  *	clockrate in Hz
+ *
  */
 ENTRY(delay)			! %o0 = n
 #if 1
 	rdpr	%tick, %o1					! Take timer snapshot
 	sethi	%hi(CPUINFO_VA + CI_CLOCKRATE), %o2
 	sethi	%hi(MICROPERSEC), %o3
 	ldx	[%o2 + %lo(CPUINFO_VA + CI_CLOCKRATE + 8)], %o4	! Get scale factor
 	brnz,pt	%o4, 0f
 	 or	%o3, %lo(MICROPERSEC), %o3
 	!! Calculate ticks/usec
 	ldx	[%o2 + %lo(CPUINFO_VA + CI_CLOCKRATE)], %o4	! No, we need to calculate it
 	udivx	%o4, %o3, %o4
 	stx	%o4, [%o2 + %lo(CPUINFO_VA + CI_CLOCKRATE + 8)]	! Save it so we don't need to divide again
 :
 	mulx	%o0, %o4, %o0					! Convert usec -> ticks
 	rdpr	%tick, %o2					! Top of next itr
 :
 	sub	%o2, %o1, %o3					! How many ticks have gone by?
 	sub	%o0, %o3, %o4					! Decrement count by that much
 	movrgz	%o3, %o4, %o0					! But only if we're decrementing
 	mov	%o2, %o1					! Remember last tick
 	brgz,pt	%o0, 1b						! Done?
 	 rdpr	%tick, %o2					! Get new tick
 	retl
 	 nop
 #else
 /* This code only works if %tick does not wrap */
 	rdpr	%tick, %g1					! Take timer snapshot
 	sethi	%hi(CPUINFO_VA + CI_CLOCKRATE), %g2
 	sethi	%hi(MICROPERSEC), %o2
 	ldx	[%g2 + %lo(CPUINFO_VA + CI_CLOCKRATE)], %g2	! Get scale factor
 	or	%o2, %lo(MICROPERSEC), %o2
 !	sethi	%hi(_C_LABEL(timerblurb), %o5			! This is if we plan to tune the clock
 !	ld	[%o5 + %lo(_C_LABEL(timerblurb))], %o5		!  with respect to the counter/timer
 	mulx	%o0, %g2, %g2					! Scale it: (usec * Hz) / 1 x 10^6 = ticks
 	udivx	%g2, %o2, %g2
 	add	%g1, %g2, %g2
 !	add	%o5, %g2, %g2			5, %g2, %g2					! But this gets complicated
 	rdpr	%tick, %g1					! Top of next itr
 	mov	%g1, %g1	! Erratum 50
 :
 	cmp	%g1, %g2
 	bl,a,pn %xcc, 1b					! Done?
 	 rdpr	%tick, %g1
 	retl
 	 nop
 #endif
 	/*
 	 * If something's wrong with the standard setup do this stupid loop
 	 * calibrated for a 143MHz processor.
 	 */
 Lstupid_delay:
 	set	142857143/MICROPERSEC, %o1
 Lstupid_loop:
 	brnz,pt	%o1, Lstupid_loop
 	 dec	%o1
 	brnz,pt	%o0, Lstupid_delay
 	 dec	%o0
 	retl
 	 nop
 /*
  * next_tick(long increment)
+ *
  * Sets the %tick_cmpr register to fire off in `increment' machine
  * cycles in the future.  Also handles %tick wraparound.  In 32-bit
  * mode we're limited to a 32-bit increment.
  */
 ENTRY(next_tick)
 	rd	TICK_CMPR, %o2
 	rdpr	%tick, %o1
 	mov	1, %o3		! Mask off high bits of these registers
 	sllx	%o3, 63, %o3
 	andn	%o1, %o3, %o1
 	andn	%o2, %o3, %o2
 	cmp	%o1, %o2	! Did we wrap?  (tick < tick_cmpr)
 	bgt,pt	%icc, 1f
 	 add	%o1, 1000, %o1	! Need some slack so we don't lose intrs.
 	/*
 	 * Handle the unlikely case of %tick wrapping.
+	 *
 	 * This should only happen every 10 years or more.
+	 *
 	 * We need to increment the time base by the size of %tick in
 	 * microseconds.  This will require some divides and multiplies
 	 * which can take time.  So we re-read %tick.
+	 *
 	 */
 	/* XXXXX NOT IMPLEMENTED */
 :
 	add	%o2, %o0, %o2
 	andn	%o2, %o3, %o4
 	brlz,pn	%o4, Ltick_ovflw
 	 cmp	%o2, %o1	! Has this tick passed?
 	blt,pn	%xcc, 1b	! Yes
 	 nop
 #ifdef BB_ERRATA_1
 	ba,a	2f
 	 nop
 #else
 	retl
 	 wr	%o2, TICK_CMPR
 #endif
 Ltick_ovflw:
 /*
  * When we get here tick_cmpr has wrapped, but we don't know if %tick
  * has wrapped.  If bit 62 is set then we have not wrapped and we can
  * use the current value of %o4 as %tick.  Otherwise we need to return
  * to our loop with %o4 as %tick_cmpr (%o2).
  */
 	srlx	%o3, 1, %o5
 	btst	%o5, %o1
 	bz,pn	%xcc, 1b
 	 mov	%o4, %o2
 #ifdef BB_ERRATA_1
 	ba,a	2f
 	 nop
 	.align	64
 :	wr	%o2, TICK_CMPR
 	rd	TICK_CMPR, %g0
 	retl
 	 nop
 #else
 	retl
 	 wr	%o2, TICK_CMPR
 #endif
 /*
  * next_stick(long increment)
+ *
  * Sets the %stick_cmpr register to fire off in `increment' machine
  * cycles in the future.  Also handles %stick wraparound.  In 32-bit
  * mode we're limited to a 32-bit increment.
  */
 ENTRY(next_stick)
 	rd	STICK_CMPR, %o2
 	rd	STICK, %o1
 	mov	1, %o3		! Mask off high bits of these registers
 	sllx	%o3, 63, %o3
 	andn	%o1, %o3, %o1
 	andn	%o2, %o3, %o2
 	cmp	%o1, %o2	! Did we wrap?  (tick < tick_cmpr)
 	bgt,pt	%icc, 1f
 	 add	%o1, 1000, %o1	! Need some slack so we don't lose intrs.
 	/*
 	 * Handle the unlikely case of %stick wrapping.
+	 *
 	 * This should only happen every 10 years or more.
+	 *
 	 * We need to increment the time base by the size of %stick in
 	 * microseconds.  This will require some divides and multiplies
 	 * which can take time.  So we re-read %stick.
+	 *
 	 */
 	/* XXXXX NOT IMPLEMENTED */
 :
 	add	%o2, %o0, %o2
 	andn	%o2, %o3, %o4
 	brlz,pn	%o4, Lstick_ovflw
 	 cmp	%o2, %o1	! Has this stick passed?
 	blt,pn	%xcc, 1b	! Yes
 	 nop
 	retl
 	 wr	%o2, STICK_CMPR
 Lstick_ovflw:
 /*
  * When we get here tick_cmpr has wrapped, but we don't know if %stick
  * has wrapped.  If bit 62 is set then we have not wrapped and we can
  * use the current value of %o4 as %stick.  Otherwise we need to return
  * to our loop with %o4 as %stick_cmpr (%o2).
  */
 	srlx	%o3, 1, %o5
 	btst	%o5, %o1
 	bz,pn	%xcc, 1b
 	 mov	%o4, %o2
 	retl
 	 wr	%o2, STICK_CMPR
 ENTRY(setjmp)
 	save	%sp, -CC64FSZ, %sp	! Need a frame to return to.
 	flushw
 	stx	%fp, [%i0+0]	! 64-bit stack pointer
 	stx	%i7, [%i0+8]	! 64-bit return pc
 	ret
 	 restore	%g0, 0, %o0
 	.data
 Lpanic_ljmp:
 	.asciz	"longjmp botch"
 	_ALIGN
 	.text
 ENTRY(longjmp)
 	save	%sp, -CC64FSZ, %sp	! prepare to restore to (old) frame
 	flushw
 	mov	1, %i2
 	ldx	[%i0+0], %fp	! get return stack
 	movrz	%i1, %i1, %i2	! compute v ? v : 1
 	ldx	[%i0+8], %i7	! get rpc
 	ret
 	 restore	%i2, 0, %o0
 #if defined(DDB) || defined(KGDB)
 	/*
 	 * Debug stuff.  Dump the trap registers into buffer & set tl=0.
+	 *
 	 *  %o0 = *ts
 	 */
 ENTRY(savetstate)
 	mov	%o0, %o1
 	rdpr	%tl, %o0
 	brz	%o0, 2f
 	 mov	%o0, %o2
 :
 	rdpr	%tstate, %o3
 	stx	%o3, [%o1]
 	deccc	%o2
 	inc	8, %o1
 	rdpr	%tpc, %o4
 	stx	%o4, [%o1]
 	inc	8, %o1
 	rdpr	%tnpc, %o5
 	stx	%o5, [%o1]
 	inc	8, %o1
 	rdpr	%tt, %o4
 	stx	%o4, [%o1]
 	inc	8, %o1
 	bnz	1b
 	 wrpr	%o2, 0, %tl
 :
 	retl
 	 nop
 	/*
 	 * Debug stuff.  Resore trap registers from buffer.
+	 *
 	 *  %o0 = %tl
 	 *  %o1 = *ts
+	 *
 	 * Maybe this should be re-written to increment tl instead of decrementing.
 	 */
 ENTRY(restoretstate)
 	flushw			! Make sure we don't have stack probs & lose hibits of %o
 	brz,pn	%o0, 2f
 	 mov	%o0, %o2
 	wrpr	%o0, 0, %tl
 :
 	ldx	[%o1], %o3
 	deccc	%o2
 	inc	8, %o1
 	wrpr	%o3, 0, %tstate
 	ldx	[%o1], %o4
 	inc	8, %o1
 	wrpr	%o4, 0, %tpc
 	ldx	[%o1], %o5
 	inc	8, %o1
 	wrpr	%o5, 0, %tnpc
 	ldx	[%o1], %o4
 	inc	8, %o1
 	wrpr	%o4, 0, %tt
 	bnz	1b
 	 wrpr	%o2, 0, %tl
 :
 	retl
 	 wrpr	%o0, 0, %tl
 	/*
 	 * Switch to context in abs(%o0)
 	 */
 ENTRY(switchtoctx_us)
 	set	DEMAP_CTX_SECONDARY, %o3
 	stxa	%o3, [%o3] ASI_DMMU_DEMAP
 	mov	CTX_SECONDARY, %o4
 	stxa	%o3, [%o3] ASI_IMMU_DEMAP
 	membar	#Sync
 	stxa	%o0, [%o4] ASI_DMMU		! Maybe we should invalid
 	sethi	%hi(KERNBASE), %o2
 	membar	#Sync
 	flush	%o2
 	retl
 	 nop
 ENTRY(switchtoctx_usiii)
 	mov	CTX_SECONDARY, %o4
 	ldxa	[%o4] ASI_DMMU, %o2		! Load secondary context
 	mov	CTX_PRIMARY, %o5
 	ldxa	[%o5] ASI_DMMU, %o1		! Save primary context
 	membar	#LoadStore
 	stxa	%o2, [%o5] ASI_DMMU		! Insert secondary for demap
 	membar	#Sync
 	set	DEMAP_CTX_PRIMARY, %o3
 	stxa	%o3, [%o3] ASI_DMMU_DEMAP
 	membar	#Sync
 	stxa	%o0, [%o4] ASI_DMMU		! Maybe we should invalid
 	membar	#Sync
 	stxa	%o1, [%o5] ASI_DMMU		! Restore primary context
 	sethi	%hi(KERNBASE), %o2
 	membar	#Sync
 	flush	%o2
 	retl
 	 nop
 #ifndef _LP64
 	/*
 	 * Convert to 32-bit stack then call OF_sym2val()
 	 */
 ENTRY(OF_sym2val32)
 	save	%sp, -CC64FSZ, %sp
 	btst	7, %i0
 	bnz,pn	%icc, 1f
 	 add	%sp, BIAS, %o1
 	btst	1, %sp
 	movnz	%icc, %o1, %sp
 	call	_C_LABEL(OF_sym2val)
 	 mov	%i0, %o0
 :
 	ret
 	 restore	%o0, 0, %o0
 	/*
 	 * Convert to 32-bit stack then call OF_val2sym()
 	 */
 ENTRY(OF_val2sym32)
 	save	%sp, -CC64FSZ, %sp
 	btst	7, %i0
 	bnz,pn	%icc, 1f
 	 add	%sp, BIAS, %o1
 	btst	1, %sp
 	movnz	%icc, %o1, %sp
 	call	_C_LABEL(OF_val2sym)
 	 mov	%i0, %o0
 :
 	ret
 	 restore	%o0, 0, %o0
 #endif /* _LP64 */
 #endif /* DDB */
 #if defined(MULTIPROCESSOR)
 /*
  * IPI target function to setup a C compatible environment and call a MI function.
+ *
  * On entry:
  *	We are on one of the alternate set of globals
  *	%g2 = function to call
  *	%g3 = single argument to called function
  */
 ENTRY(sparc64_ipi_ccall)
 #ifdef TRAPS_USE_IG
 	wrpr	%g0, PSTATE_KERN|PSTATE_IG, %pstate	! DEBUG
 #endif
 	TRAP_SETUP(-CC64FSZ-TF_SIZE)
 #ifdef DEBUG
 	rdpr	%tt, %o1	! debug
 	sth	%o1, [%sp + CC64FSZ + STKB + TF_TT]! debug
 #endif
 	mov	%g3, %o0			! save argument of function to call
 	mov	%g2, %o5			! save function pointer
 	wrpr	%g0, PSTATE_KERN, %pstate	! Get back to normal globals
 	stx	%g1, [%sp + CC64FSZ + STKB + TF_G + ( 1*8)]
 	mov	%g1, %o1			! code
 	rdpr	%tpc, %o2			! (pc)
 	stx	%g2, [%sp + CC64FSZ + STKB + TF_G + ( 2*8)]
 	rdpr	%tstate, %g1
 	stx	%g3, [%sp + CC64FSZ + STKB + TF_G + ( 3*8)]
 	rdpr	%tnpc, %o3
 	stx	%g4, [%sp + CC64FSZ + STKB + TF_G + ( 4*8)]
 	rd	%y, %o4
 	stx	%g5, [%sp + CC64FSZ + STKB + TF_G + ( 5*8)]
 	stx	%g6, [%sp + CC64FSZ + STKB + TF_G + ( 6*8)]
 	wrpr	%g0, 0, %tl			! return to tl=0
 	stx	%g7, [%sp + CC64FSZ + STKB + TF_G + ( 7*8)]
 	stx	%g1, [%sp + CC64FSZ + STKB + TF_TSTATE]
 	stx	%o2, [%sp + CC64FSZ + STKB + TF_PC]
 	stx	%o3, [%sp + CC64FSZ + STKB + TF_NPC]
 	st	%o4, [%sp + CC64FSZ + STKB + TF_Y]
 	rdpr	%pil, %g5
 	stb	%g5, [%sp + CC64FSZ + STKB + TF_PIL]
 	stb	%g5, [%sp + CC64FSZ + STKB + TF_OLDPIL]
 	!! In the EMBEDANY memory model %g4 points to the start of the data segment.
 	!! In our case we need to clear it before calling any C-code
 	clr	%g4
 	wr	%g0, ASI_NUCLEUS, %asi			! default kernel ASI
 	call %o5					! call function
 	 nop
 	ba,a	return_from_trap			! and return from IPI
 	 nop
 #endif
 	.data
 	_ALIGN
 #if NKSYMS || defined(DDB) || defined(LKM)
 	.globl	_C_LABEL(esym)
 _C_LABEL(esym):
 	POINTER	0
 	.globl	_C_LABEL(ssym)
 _C_LABEL(ssym):
 	POINTER	0
 #endif
 	.comm	_C_LABEL(promvec), PTRSZ
 #ifdef DEBUG
 	.comm	_C_LABEL(trapdebug), 4
 	.comm	_C_LABEL(pmapdebug), 4
 #endif