 @@ -1,1079 +1,1084 @@
 /* Definitions of target machine for GNU compiler, for ARM.
    Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
 , 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
    Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
    and Martin Simmons (@harleqn.co.uk).
    More major hacks by Richard Earnshaw (rearnsha@arm.com)
    Minor hacks by Nick Clifton (nickc@cygnus.com)
    This file is part of GCC.
    GCC is free software; you can redistribute it and/or modify it
    under the terms of the GNU General Public License as published
    by the Free Software Foundation; either version 2, or (at your
    option) any later version.
    GCC is distributed in the hope that it will be useful, but WITHOUT
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
    License for more details.
    You should have received a copy of the GNU General Public License
    along with GCC; see the file COPYING.  If not, write to
    the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 #ifndef GCC_ARM_H
 #define GCC_ARM_H
 /* The architecture define.  */
 extern char arm_arch_name[];
 /* Target CPU builtins.  */
 #define TARGET_CPU_CPP_BUILTINS()			\
   do							\
     {							\
 	/* Define __arm__ even when in thumb mode, for	\
 	   consistency with armcc.  */			\
 	builtin_define ("__arm__");			\
 	builtin_define ("__APCS_32__");			\
 	if (TARGET_THUMB)				\
 	  builtin_define ("__thumb__");			\
+							\
 	if (TARGET_BIG_END)				\
 	  {						\
 	    builtin_define ("__ARMEB__");		\
 	    if (TARGET_THUMB)				\
 	      builtin_define ("__THUMBEB__");		\
 	    if (TARGET_LITTLE_WORDS)			\
 	      builtin_define ("__ARMWEL__");		\
 	  }						\
         else						\
 	  {						\
 	    builtin_define ("__ARMEL__");		\
 	    if (TARGET_THUMB)				\
 	      builtin_define ("__THUMBEL__");		\
 	  }						\
+							\
 	if (TARGET_SOFT_FLOAT)				\
 	  builtin_define ("__SOFTFP__");		\
+							\
 	if (TARGET_VFP)					\
 	  builtin_define ("__VFP_FP__");		\
+							\
 	/* Add a define for interworking.		\
 	   Needed when building libgcc.a.  */		\
 	if (arm_cpp_interwork)				\
 	  builtin_define ("__THUMB_INTERWORK__");	\
+							\
 	builtin_assert ("cpu=arm");			\
 	builtin_assert ("machine=arm");			\
+							\
 	builtin_define (arm_arch_name);			\
 	if (arm_arch_cirrus)				\
 	  builtin_define ("__MAVERICK__");		\
 	if (arm_arch_xscale)				\
 	  builtin_define ("__XSCALE__");		\
 	if (arm_arch_iwmmxt)				\
 	  builtin_define ("__IWMMXT__");		\
 	if (TARGET_AAPCS_BASED)				\
-	  builtin_define ("__ARM_EABI__");		\
+	  {						\
 	    builtin_define ("__ARM_EABI__");		\
 	    builtin_define ("__ARM_PCS");		\
 	    if (TARGET_HARD_FLOAT && TARGET_VFP)	\
 	      builtin_define ("__ARM_PCS_VFP");		\
 	  }						\
     } while (0)
 /* The various ARM cores.  */
 enum processor_type
+{
 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
   IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
   /* Used to indicate that no processor has been specified.  */
   arm_none
 };
 enum target_cpus
+{
 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
   TARGET_CPU_##IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
   TARGET_CPU_generic
 };
 /* The processor for which instructions should be scheduled.  */
 extern enum processor_type arm_tune;
 typedef enum arm_cond_code
+{
   ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
   ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
+}
 arm_cc;
 extern arm_cc arm_current_cc;
 #define ARM_INVERSE_CONDITION_CODE(X)  ((arm_cc) (((int)X) ^ 1))
 extern int arm_target_label;
 extern int arm_ccfsm_state;
 extern GTY(()) rtx arm_target_insn;
 /* Define the information needed to generate branch insns.  This is
    stored from the compare operation.  */
 extern GTY(()) rtx arm_compare_op0;
 extern GTY(()) rtx arm_compare_op1;
 /* The label of the current constant pool.  */
 extern rtx pool_vector_label;
 /* Set to 1 when a return insn is output, this means that the epilogue
    is not needed.  */
 extern int return_used_this_function;
 /* Used to produce AOF syntax assembler.  */
 extern GTY(()) rtx aof_pic_label;
 /* Just in case configure has failed to define anything.  */
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
 #endif
 #undef  CPP_SPEC
 #define CPP_SPEC "%(subtarget_cpp_spec)					\
 %{msoft-float:%{mhard-float:						\
 	%e-msoft-float and -mhard_float may not be used together}}	\
 %{mbig-endian:%{mlittle-endian:						\
 	%e-mbig-endian and -mlittle-endian may not be used together}}"
 #ifndef CC1_SPEC
 #define CC1_SPEC ""
 #endif
 /* This macro defines names of additional specifications to put in the specs
    that can be used in various specifications like CC1_SPEC.  Its definition
    is an initializer with a subgrouping for each command option.
    Each subgrouping contains a string constant, that defines the
    specification name, and a string constant that used by the GCC driver
    program.
    Do not define this macro if it does not need to do anything.  */
 #define EXTRA_SPECS						\
   { "subtarget_cpp_spec",	SUBTARGET_CPP_SPEC },           \
   SUBTARGET_EXTRA_SPECS
 #ifndef SUBTARGET_EXTRA_SPECS
 #define SUBTARGET_EXTRA_SPECS
 #endif
 #ifndef SUBTARGET_CPP_SPEC
 #define SUBTARGET_CPP_SPEC      ""
 #endif
 /* Run-time Target Specification.  */
 #ifndef TARGET_VERSION
 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
 #endif
 #define TARGET_SOFT_FLOAT		(arm_float_abi == ARM_FLOAT_ABI_SOFT)
 /* Use hardware floating point instructions. */
 #define TARGET_HARD_FLOAT		(arm_float_abi != ARM_FLOAT_ABI_SOFT)
 /* Use hardware floating point calling convention.  */
 #define TARGET_HARD_FLOAT_ABI		(arm_float_abi == ARM_FLOAT_ABI_HARD)
 #define TARGET_FPA			(arm_fp_model == ARM_FP_MODEL_FPA)
 #define TARGET_MAVERICK			(arm_fp_model == ARM_FP_MODEL_MAVERICK)
 #define TARGET_VFP			(arm_fp_model == ARM_FP_MODEL_VFP)
 #define TARGET_IWMMXT			(arm_arch_iwmmxt)
 #define TARGET_REALLY_IWMMXT		(TARGET_IWMMXT && TARGET_ARM)
 #define TARGET_IWMMXT_ABI (TARGET_ARM && arm_abi == ARM_ABI_IWMMXT)
 #define TARGET_ARM                      (! TARGET_THUMB)
 #define TARGET_EITHER			1 /* (TARGET_ARM | TARGET_THUMB) */
 #define TARGET_BACKTRACE	        (leaf_function_p () \
 				         ? TARGET_TPCS_LEAF_FRAME \
 				         : TARGET_TPCS_FRAME)
 #define TARGET_LDRD			(arm_arch5e && ARM_DOUBLEWORD_ALIGN)
 #define TARGET_AAPCS_BASED \
     (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
 #define TARGET_HARD_TP			(target_thread_pointer == TP_CP15)
 #define TARGET_SOFT_TP			(target_thread_pointer == TP_SOFT)
 /* True iff the full BPABI is being used.  If TARGET_BPABI is true,
    then TARGET_AAPCS_BASED must be true -- but the converse does not
    hold.  TARGET_BPABI implies the use of the BPABI runtime library,
    etc., in addition to just the AAPCS calling conventions.  */
 #ifndef TARGET_BPABI
 #define TARGET_BPABI false
 #endif
 /* Support for a compile-time default CPU, et cetera.  The rules are:
    --with-arch is ignored if -march or -mcpu are specified.
    --with-cpu is ignored if -march or -mcpu are specified, and is overridden
     by --with-arch.
    --with-tune is ignored if -mtune or -mcpu are specified (but not affected
      by -march).
    --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are
    specified.
    --with-fpu is ignored if -mfpu is specified.
    --with-abi is ignored is -mabi is specified.  */
 #define OPTION_DEFAULT_SPECS \
   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \
   {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \
   {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \
   {"float", \
     "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \
   {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
   {"abi", "%{!mabi=*:-mabi=%(VALUE)}"},
 /* Which floating point model to use.  */
 enum arm_fp_model
+{
   ARM_FP_MODEL_UNKNOWN,
   /* FPA model (Hardware or software).  */
   ARM_FP_MODEL_FPA,
   /* Cirrus Maverick floating point model.  */
   ARM_FP_MODEL_MAVERICK,
   /* VFP floating point model.  */
   ARM_FP_MODEL_VFP
 };
 extern enum arm_fp_model arm_fp_model;
 /* Which floating point hardware is available.  Also update
    fp_model_for_fpu in arm.c when adding entries to this list.  */
 enum fputype
+{
   /* No FP hardware.  */
   FPUTYPE_NONE,
   /* Full FPA support.  */
   FPUTYPE_FPA,
   /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM).  */
   FPUTYPE_FPA_EMU2,
   /* Emulated FPA hardware, Issue 3 emulator.  */
   FPUTYPE_FPA_EMU3,
   /* Cirrus Maverick floating point co-processor.  */
   FPUTYPE_MAVERICK,
   /* VFP.  */
   FPUTYPE_VFP
 };
 /* Recast the floating point class to be the floating point attribute.  */
 #define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
 /* What type of floating point to tune for */
 extern enum fputype arm_fpu_tune;
 /* What type of floating point instructions are available */
 extern enum fputype arm_fpu_arch;
 enum float_abi_type
+{
   ARM_FLOAT_ABI_SOFT,
   ARM_FLOAT_ABI_SOFTFP,
   ARM_FLOAT_ABI_HARD
 };
 extern enum float_abi_type arm_float_abi;
 #ifndef TARGET_DEFAULT_FLOAT_ABI
 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
 #endif
 /* Which ABI to use.  */
 enum arm_abi_type
+{
   ARM_ABI_APCS,
   ARM_ABI_ATPCS,
   ARM_ABI_AAPCS,
   ARM_ABI_IWMMXT,
   ARM_ABI_AAPCS_LINUX
 };
 extern enum arm_abi_type arm_abi;
 #ifndef ARM_DEFAULT_ABI
 #define ARM_DEFAULT_ABI ARM_ABI_APCS
 #endif
 /* Which thread pointer access sequence to use.  */
 enum arm_tp_type {
   TP_AUTO,
   TP_SOFT,
   TP_CP15
 };
 extern enum arm_tp_type target_thread_pointer;
 /* Nonzero if this chip supports the ARM Architecture 3M extensions.  */
 extern int arm_arch3m;
 /* Nonzero if this chip supports the ARM Architecture 4 extensions.  */
 extern int arm_arch4;
 /* Nonzero if this chip supports the ARM Architecture 4T extensions.  */
 extern int arm_arch4t;
 /* Nonzero if this chip supports the ARM Architecture 5 extensions.  */
 extern int arm_arch5;
 /* Nonzero if this chip supports the ARM Architecture 5E extensions.  */
 extern int arm_arch5e;
 /* Nonzero if this chip supports the ARM Architecture 6 extensions.  */
 extern int arm_arch6;
 /* Nonzero if this chip can benefit from load scheduling.  */
 extern int arm_ld_sched;
 /* Nonzero if generating thumb code.  */
 extern int thumb_code;
 /* Nonzero if this chip is a StrongARM.  */
 extern int arm_tune_strongarm;
 /* Nonzero if this chip is a Cirrus variant.  */
 extern int arm_arch_cirrus;
 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology.  */
 extern int arm_arch_iwmmxt;
 /* Nonzero if this chip is an XScale.  */
 extern int arm_arch_xscale;
 /* Nonzero if tuning for XScale.  */
 extern int arm_tune_xscale;
 /* Nonzero if tuning for stores via the write buffer.  */
 extern int arm_tune_wbuf;
 /* Nonzero if we should define __THUMB_INTERWORK__ in the
    preprocessor.
    XXX This is a bit of a hack, it's intended to help work around
    problems in GLD which doesn't understand that armv5t code is
    interworking clean.  */
 extern int arm_cpp_interwork;
 #ifndef TARGET_DEFAULT
 #define TARGET_DEFAULT  (MASK_APCS_FRAME)
 #endif
 /* The frame pointer register used in gcc has nothing to do with debugging;
    that is controlled by the APCS-FRAME option.  */
 #define CAN_DEBUG_WITHOUT_FP
 #define OVERRIDE_OPTIONS  arm_override_options ()
 /* Nonzero if PIC code requires explicit qualifiers to generate
    PLT and GOT relocs rather than the assembler doing so implicitly.
    Subtargets can override these if required.  */
 #ifndef NEED_GOT_RELOC
 #define NEED_GOT_RELOC	0
 #endif
 #ifndef NEED_PLT_RELOC
 #define NEED_PLT_RELOC	0
 #endif
 /* Nonzero if we need to refer to the GOT with a PC-relative
    offset.  In other words, generate
    .word	_GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
    rather than
    .word	_GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
    The default is true, which matches NetBSD.  Subtargets can
    override this if required.  */
 #ifndef GOT_PCREL
 #define GOT_PCREL   1
 #endif
 /* Target machine storage Layout.  */
 /* Define this macro if it is advisable to hold scalars in registers
    in a wider mode than that declared by the program.  In such cases,
    the value is constrained to be within the bounds of the declared
    type, but kept valid in the wider mode.  The signedness of the
    extension may differ from that of the type.  */
 /* It is far faster to zero extend chars than to sign extend them */
 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
   if (GET_MODE_CLASS (MODE) == MODE_INT		\
       && GET_MODE_SIZE (MODE) < 4)      	\
     {						\
       if (MODE == QImode)			\
 	UNSIGNEDP = 1;				\
       else if (MODE == HImode)			\
 	UNSIGNEDP = 1;				\
       (MODE) = SImode;				\
+    }
 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE)	\
   if ((GET_MODE_CLASS (MODE) == MODE_INT		\
        || GET_MODE_CLASS (MODE) == MODE_COMPLEX_INT)    \
       && GET_MODE_SIZE (MODE) < 4)                      \
     (MODE) = SImode;				        \
 /* Define this if most significant bit is lowest numbered
    in instructions that operate on numbered bit-fields.  */
 #define BITS_BIG_ENDIAN  0
 /* Define this if most significant byte of a word is the lowest numbered.
    Most ARM processors are run in little endian mode, so that is the default.
    If you want to have it run-time selectable, change the definition in a
    cover file to be TARGET_BIG_ENDIAN.  */
 #define BYTES_BIG_ENDIAN  (TARGET_BIG_END != 0)
 /* Define this if most significant word of a multiword number is the lowest
    numbered.
    This is always false, even when in big-endian mode.  */
 #define WORDS_BIG_ENDIAN  (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
    on processor pre-defineds when compiling libgcc2.c.  */
 #if defined(__ARMEB__) && !defined(__ARMWEL__)
 #define LIBGCC2_WORDS_BIG_ENDIAN 1
 #else
 #define LIBGCC2_WORDS_BIG_ENDIAN 0
 #endif
 /* Define this if most significant word of doubles is the lowest numbered.
    The rules are different based on whether or not we use FPA-format,
    VFP-format or some other floating point co-processor's format doubles.  */
 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ())
 #define UNITS_PER_WORD	4
 /* True if natural alignment is used for doubleword types.  */
 #define ARM_DOUBLEWORD_ALIGN	TARGET_AAPCS_BASED
 #define DOUBLEWORD_ALIGNMENT 64
 #define PARM_BOUNDARY  	32
 #define STACK_BOUNDARY  (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
 #define PREFERRED_STACK_BOUNDARY \
     (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY)
 #define FUNCTION_BOUNDARY  32
 /* The lowest bit is used to indicate Thumb-mode functions, so the
    vbit must go into the delta field of pointers to member
    functions.  */
 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
 #define EMPTY_FIELD_BOUNDARY  32
 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32)
 /* XXX Blah -- this macro is used directly by libobjc.  Since it
    supports no vector modes, cut out the complexity and fall back
    on BIGGEST_FIELD_ALIGNMENT.  */
 #ifdef IN_TARGET_LIBS
 #define BIGGEST_FIELD_ALIGNMENT 64
 #endif
 /* Make strings word-aligned so strcpy from constants will be faster.  */
 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2)
 #define CONSTANT_ALIGNMENT(EXP, ALIGN)				\
    ((TREE_CODE (EXP) == STRING_CST				\
      && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR)	\
     ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
    value set in previous versions of this toolchain was 8, which produces more
    compact structures.  The command line option -mstructure_size_boundary=<n>
    can be used to change this value.  For compatibility with the ARM SDK
    however the value should be left at 32.  ARM SDT Reference Manual (ARM DUI
 D) page 2-20 says "Structures are aligned on word boundaries".
    The AAPCS specifies a value of 8.  */
 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
 extern int arm_structure_size_boundary;
 /* This is the value used to initialize arm_structure_size_boundary.  If a
    particular arm target wants to change the default value it should change
    the definition of this macro, not STRUCTURE_SIZE_BOUNDARY.  See netbsd.h
    for an example of this.  */
 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
 #endif
 /* Nonzero if move instructions will actually fail to work
    when given unaligned data.  */
 #define STRICT_ALIGNMENT 1
 /* wchar_t is unsigned under the AAPCS.  */
 #ifndef WCHAR_TYPE
 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int")
 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 #endif
 #ifndef SIZE_TYPE
 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int")
 #endif
 #ifndef PTRDIFF_TYPE
 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int")
 #endif
 /* AAPCS requires that structure alignment is affected by bitfields.  */
 #ifndef PCC_BITFIELD_TYPE_MATTERS
 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED
 #endif
 /* Standard register usage.  */
 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
    (S - saved over call).
 	r0	   *	argument word/integer result
 	r1-r3		argument word
 	r4-r8	     S	register variable
 	r9	     S	(rfp) register variable (real frame pointer)
 	r10  	   F S	(sl) stack limit (used by -mapcs-stack-check)
 	r11 	   F S	(fp) argument pointer
 	r12		(ip) temp workspace
 	r13  	   F S	(sp) lower end of current stack frame
 	r14		(lr) link address/workspace
 	r15	   F	(pc) program counter
 	f0		floating point result
 	f1-f3		floating point scratch
 	f4-f7	     S	floating point variable
 	cc		This is NOT a real register, but is used internally
 	                to represent things that use or set the condition
 			codes.
 	sfp             This isn't either.  It is used during rtl generation
 	                since the offset between the frame pointer and the
 			auto's isn't known until after register allocation.
 	afp		Nor this, we only need this because of non-local
 	                goto.  Without it fp appears to be used and the
 			elimination code won't get rid of sfp.  It tracks
 			fp exactly at all times.
    *: See CONDITIONAL_REGISTER_USAGE  */
 /*
   	mvf0		Cirrus floating point result
 	mvf1-mvf3	Cirrus floating point scratch
 	mvf4-mvf15   S	Cirrus floating point variable.  */
 /*	s0-s15		VFP scratch (aka d0-d7).
 	s16-s31	      S	VFP variable (aka d8-d15).
 	vfpcc		Not a real register.  Represents the VFP condition
 			code flags.  */
 /* The stack backtrace structure is as follows:
   fp points to here:  |  save code pointer  |      [fp]
                       |  return link value  |      [fp, #-4]
                       |  return sp value    |      [fp, #-8]
                       |  return fp value    |      [fp, #-12]
                      [|  saved r10 value    |]
                      [|  saved r9 value     |]
                      [|  saved r8 value     |]
                      [|  saved r7 value     |]
                      [|  saved r6 value     |]
                      [|  saved r5 value     |]
                      [|  saved r4 value     |]
                      [|  saved r3 value     |]
                      [|  saved r2 value     |]
                      [|  saved r1 value     |]
                      [|  saved r0 value     |]
                      [|  saved f7 value     |]     three words
                      [|  saved f6 value     |]     three words
                      [|  saved f5 value     |]     three words
                      [|  saved f4 value     |]     three words
   r0-r3 are not normally saved in a C function.  */
 /* 1 for registers that have pervasive standard uses
    and are not available for the register allocator.  */
 #define FIXED_REGISTERS \
 {                       \
 ,0,0,0,0,0,0,0,	\
 ,0,0,0,0,1,0,1,	\
 ,0,0,0,0,0,0,0,	\
 ,1,1,		\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,		\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 ,1,1,1,1,1,1,1,	\
 			\
+}
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
    registers that can be used without being saved.
    The latter must include the registers where values are returned
    and the register where structure-value addresses are passed.
    Aside from that, you can include as many other registers as you like.
    The CC is not preserved over function calls on the ARM 6, so it is
    easier to assume this for all.  SFP is preserved, since FP is.  */
 #define CALL_USED_REGISTERS  \
 {                            \
 ,1,1,1,0,0,0,0,	     \
 ,0,0,0,1,1,1,1,	     \
 ,1,1,1,0,0,0,0,	     \
 ,1,1,		     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,		     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 ,1,1,1,1,1,1,1,	     \
 			     \
+}
 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
 #endif
 #define CONDITIONAL_REGISTER_USAGE				\
 {								\
   int regno;							\
+								\
   if (TARGET_SOFT_FLOAT || TARGET_THUMB || !TARGET_FPA)		\
     {								\
       for (regno = FIRST_FPA_REGNUM;				\
 	   regno <= LAST_FPA_REGNUM; ++regno)			\
 	fixed_regs[regno] = call_used_regs[regno] = 1;		\
     }								\
+								\
   if (TARGET_THUMB && optimize_size)				\
     {								\
       /* When optimizing for size, it's better not to use	\
 	 the HI regs, because of the overhead of stacking 	\
 	 them.  */						\
       for (regno = FIRST_HI_REGNUM;				\
 	   regno <= LAST_HI_REGNUM; ++regno)			\
 	fixed_regs[regno] = call_used_regs[regno] = 1;		\
     }								\
+								\
   /* The link register can be clobbered by any branch insn,	\
      but we have no way to track that at present, so mark	\
      it as unavailable.  */					\
   if (TARGET_THUMB)						\
     fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1;	\
+								\
   if (TARGET_ARM && TARGET_HARD_FLOAT)				\
     {								\
       if (TARGET_MAVERICK)					\
 	{							\
 	  for (regno = FIRST_FPA_REGNUM;			\
 	       regno <= LAST_FPA_REGNUM; ++ regno)		\
 	    fixed_regs[regno] = call_used_regs[regno] = 1;	\
 	  for (regno = FIRST_CIRRUS_FP_REGNUM;			\
 	       regno <= LAST_CIRRUS_FP_REGNUM; ++ regno)	\
 	    {							\
 	      fixed_regs[regno] = 0;				\
 	      call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \
 	    }							\
 	}							\
       if (TARGET_VFP)						\
 	{							\
 	  for (regno = FIRST_VFP_REGNUM;			\
 	       regno <= LAST_VFP_REGNUM; ++ regno)		\
 	    {							\
 	      fixed_regs[regno] = 0;				\
 	      call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16; \
 	    }							\
 	}							\
     }								\
+								\
   if (TARGET_REALLY_IWMMXT)					\
     {								\
       regno = FIRST_IWMMXT_GR_REGNUM;				\
       /* The 2002/10/09 revision of the XScale ABI has wCG0     \
          and wCG1 as call-preserved registers.  The 2002/11/21  \
          revision changed this so that all wCG registers are    \
          scratch registers.  */					\
       for (regno = FIRST_IWMMXT_GR_REGNUM;			\
 	   regno <= LAST_IWMMXT_GR_REGNUM; ++ regno)		\
 	fixed_regs[regno] = 0;					\
       /* The XScale ABI has wR0 - wR9 as scratch registers,     \
 	 the rest as call-preserved registers.  */		\
       for (regno = FIRST_IWMMXT_REGNUM;				\
 	   regno <= LAST_IWMMXT_REGNUM; ++ regno)		\
 	{							\
 	  fixed_regs[regno] = 0;				\
 	  call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \
 	}							\
     }								\
+								\
   if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)	\
     {								\
       fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;			\
       call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;		\
     }								\
   else if (TARGET_APCS_STACK)					\
     {								\
       fixed_regs[10]     = 1;					\
       call_used_regs[10] = 1;					\
     }								\
   /* -mcaller-super-interworking reserves r11 for calls to	\
      _interwork_r11_call_via_rN().  Making the register global	\
      is an easy way of ensuring that it remains valid for all	\
      calls.  */							\
   if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING		\
       || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME)		\
     {								\
       fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;		\
       call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;	\
       if (TARGET_CALLER_INTERWORKING)				\
 	global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1;		\
     }								\
   SUBTARGET_CONDITIONAL_REGISTER_USAGE				\
+}
 /* These are a couple of extensions to the formats accepted
    by asm_fprintf:
      %@ prints out ASM_COMMENT_START
      %r prints out REGISTER_PREFIX reg_names[arg]  */
 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P)		\
   case '@':						\
     fputs (ASM_COMMENT_START, FILE);			\
     break;						\
+							\
   case 'r':						\
     fputs (REGISTER_PREFIX, FILE);			\
     fputs (reg_names [va_arg (ARGS, int)], FILE);	\
     break;
 /* Round X up to the nearest word.  */
 #define ROUND_UP_WORD(X) (((X) + 3) & ~3)
 /* Convert fron bytes to ints.  */
 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 /* The number of (integer) registers required to hold a quantity of type MODE.
    Also used for VFP registers.  */
 #define ARM_NUM_REGS(MODE)				\
   ARM_NUM_INTS (GET_MODE_SIZE (MODE))
 /* The number of (integer) registers required to hold a quantity of TYPE MODE.  */
 #define ARM_NUM_REGS2(MODE, TYPE)                   \
   ARM_NUM_INTS ((MODE) == BLKmode ? 		\
   int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
 /* The number of (integer) argument register available.  */
 #define NUM_ARG_REGS		4
 /* Return the register number of the N'th (integer) argument.  */
 #define ARG_REGISTER(N) 	(N - 1)
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
 /* The number of the last argument register.  */
 #define LAST_ARG_REGNUM 	ARG_REGISTER (NUM_ARG_REGS)
 /* The numbers of the Thumb register ranges.  */
 #define FIRST_LO_REGNUM  	0
 #define LAST_LO_REGNUM  	7
 #define FIRST_HI_REGNUM		8
 #define LAST_HI_REGNUM		11
 #ifndef TARGET_UNWIND_INFO
 /* We use sjlj exceptions for backwards compatibility.  */
 #define MUST_USE_SJLJ_EXCEPTIONS 1
 #endif
 /* We can generate DWARF2 Unwind info, even though we don't use it.  */
 #define DWARF2_UNWIND_INFO 1
 /* Use r0 and r1 to pass exception handling information.  */
 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM)
 /* The register that holds the return address in exception handlers.  */
 #define ARM_EH_STACKADJ_REGNUM	2
 #define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM)
 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
    as an invisible last argument (possible since varargs don't exist in
    Pascal), so the following is not true.  */
 #define STATIC_CHAIN_REGNUM	(TARGET_ARM ? 12 : 9)
 /* Define this to be where the real frame pointer is if it is not possible to
    work out the offset between the frame pointer and the automatic variables
    until after register allocation has taken place.  FRAME_POINTER_REGNUM
    should point to a special register that we will make sure is eliminated.
    For the Thumb we have another problem.  The TPCS defines the frame pointer
    as r11, and GCC believes that it is always possible to use the frame pointer
    as base register for addressing purposes.  (See comments in
    find_reloads_address()).  But - the Thumb does not allow high registers,
    including r11, to be used as base address registers.  Hence our problem.
    The solution used here, and in the old thumb port is to use r7 instead of
    r11 as the hard frame pointer and to have special code to generate
    backtrace structures on the stack (if required to do so via a command line
    option) using r11.  This is the only 'user visible' use of r11 as a frame
    pointer.  */
 #define ARM_HARD_FRAME_POINTER_REGNUM	11
 #define THUMB_HARD_FRAME_POINTER_REGNUM	 7
 #define HARD_FRAME_POINTER_REGNUM		\
   (TARGET_ARM					\
    ? ARM_HARD_FRAME_POINTER_REGNUM		\
    : THUMB_HARD_FRAME_POINTER_REGNUM)
 #define FP_REGNUM	                HARD_FRAME_POINTER_REGNUM
 /* Register to use for pushing function arguments.  */
 #define STACK_POINTER_REGNUM	SP_REGNUM
 /* ARM floating pointer registers.  */
 #define FIRST_FPA_REGNUM 	16
 #define LAST_FPA_REGNUM  	23
 #define IS_FPA_REGNUM(REGNUM) \
   (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM))
 #define FIRST_IWMMXT_GR_REGNUM	43
 #define LAST_IWMMXT_GR_REGNUM	46
 #define FIRST_IWMMXT_REGNUM	47
 #define LAST_IWMMXT_REGNUM	62
 #define IS_IWMMXT_REGNUM(REGNUM) \
   (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM))
 #define IS_IWMMXT_GR_REGNUM(REGNUM) \
   (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM))
 /* Base register for access to local variables of the function.  */
 #define FRAME_POINTER_REGNUM	25
 /* Base register for access to arguments of the function.  */
 #define ARG_POINTER_REGNUM	26
 #define FIRST_CIRRUS_FP_REGNUM	27
 #define LAST_CIRRUS_FP_REGNUM	42
 #define IS_CIRRUS_REGNUM(REGNUM) \
   (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM))
 #define FIRST_VFP_REGNUM	63
 #define LAST_VFP_REGNUM		94
 #define IS_VFP_REGNUM(REGNUM) \
   (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM))
 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP.  */
 /* + 16 Cirrus registers take us up to 43.  */
 /* Intel Wireless MMX Technology registers add 16 + 4 more.  */
 /* VFP adds 32 + 1 more.  */
 #define FIRST_PSEUDO_REGISTER   96
 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO)
 /* Value should be nonzero if functions must have frame pointers.
    Zero means the frame pointer need not be set up (and parms may be accessed
    via the stack pointer) in functions that seem suitable.
    If we have to have a frame pointer we might as well make use of it.
    APCS says that the frame pointer does not need to be pushed in leaf
    functions, or simple tail call functions.  */
 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
 #endif
 #define FRAME_POINTER_REQUIRED					\
   (current_function_has_nonlocal_label				\
    || SUBTARGET_FRAME_POINTER_REQUIRED				\
    || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
 /* Return number of consecutive hard regs needed starting at reg REGNO
    to hold something of mode MODE.
    This is ordinarily the length in words of a value of mode MODE
    but can be less for certain modes in special long registers.
    On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP
    mode.  */
 #define HARD_REGNO_NREGS(REGNO, MODE)  	\
   ((TARGET_ARM 				\
     && REGNO >= FIRST_FPA_REGNUM	\
     && REGNO != FRAME_POINTER_REGNUM	\
     && REGNO != ARG_POINTER_REGNUM)	\
     && !IS_VFP_REGNUM (REGNO)		\
    ? 1 : ARM_NUM_REGS (MODE))
 /* Return true if REGNO is suitable for holding a quantity of type MODE.  */
 #define HARD_REGNO_MODE_OK(REGNO, MODE)					\
   arm_hard_regno_mode_ok ((REGNO), (MODE))
 /* Value is 1 if it is a good idea to tie two pseudo registers
    when one has mode MODE1 and one has mode MODE2.
    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
    for any hard reg, then this must be 0 for correct output.  */
 #define MODES_TIEABLE_P(MODE1, MODE2)  \
   (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
 #define VALID_IWMMXT_REG_MODE(MODE) \
  (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
 /* The order in which register should be allocated.  It is good to use ip
    since no saving is required (though calls clobber it) and it never contains
    function parameters.  It is quite good to use lr since other calls may
    clobber it anyway.  Allocate r0 through r3 in reverse order since r3 is
    least likely to contain a function parameter; in addition results are
    returned in r0.  */
 #define REG_ALLOC_ORDER  	    \
 {                                   \
 ,  2,  1,  0, 12, 14,  4,  5, \
 ,  7,  8, 10,  9, 11, 13, 15, \
 , 17, 18, 19, 20, 21, 22, 23, \
 , 28, 29, 30, 31, 32, 33, 34, \
 , 36, 37, 38, 39, 40, 41, 42, \
 , 44, 45, 46, 47, 48, 49, 50, \
 , 52, 53, 54, 55, 56, 57, 58, \
 , 60, 61, 62,		    \
 , 25, 26,			    \
 , 77, 76, 75, 74, 73, 72, 71, \
 , 69, 68, 67, 66, 65, 64, 63, \
 , 80, 81, 82, 83, 84, 85, 86, \
 , 88, 89, 90, 91, 92, 93, 94, \
 				    \
+}
 /* Interrupt functions can only use registers that have already been
    saved by the prologue, even if they would normally be
    call-clobbered.  */
 #define HARD_REGNO_RENAME_OK(SRC, DST)					\
 	(! IS_INTERRUPT (cfun->machine->func_type) ||			\
 		regs_ever_live[DST])
 /* Register and constant classes.  */
 /* Register classes: used to be simple, just all ARM regs or all FPA regs
    Now that the Thumb is involved it has become more complicated.  */
 enum reg_class
+{
   NO_REGS,
   FPA_REGS,
   CIRRUS_REGS,
   VFP_REGS,
   IWMMXT_GR_REGS,
   IWMMXT_REGS,
   LO_REGS,
   STACK_REG,
   BASE_REGS,
   HI_REGS,
   CC_REG,
   VFPCC_REG,
   GENERAL_REGS,
   ALL_REGS,
   LIM_REG_CLASSES
 };
 #define N_REG_CLASSES  (int) LIM_REG_CLASSES
 /* Give names of register classes as strings for dump file.  */
 #define REG_CLASS_NAMES  \
 {			\
   "NO_REGS",		\
   "FPA_REGS",		\
   "CIRRUS_REGS",	\
   "VFP_REGS",		\
   "IWMMXT_GR_REGS",	\
   "IWMMXT_REGS",	\
   "LO_REGS",		\
   "STACK_REG",		\
   "BASE_REGS",		\
   "HI_REGS",		\
   "CC_REG",		\
   "VFPCC_REG",		\
   "GENERAL_REGS",	\
   "ALL_REGS",		\
+}
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */
 #define REG_CLASS_CONTENTS					\
 {								\
   { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS  */	\
   { 0x00FF0000, 0x00000000, 0x00000000 }, /* FPA_REGS */	\
   { 0xF8000000, 0x000007FF, 0x00000000 }, /* CIRRUS_REGS */	\
   { 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_REGS  */	\
   { 0x00000000, 0x00007800, 0x00000000 }, /* IWMMXT_GR_REGS */	\
   { 0x00000000, 0x7FFF8000, 0x00000000 }, /* IWMMXT_REGS */	\
   { 0x000000FF, 0x00000000, 0x00000000 }, /* LO_REGS */		\
   { 0x00002000, 0x00000000, 0x00000000 }, /* STACK_REG */	\
   { 0x000020FF, 0x00000000, 0x00000000 }, /* BASE_REGS */	\
   { 0x0000FF00, 0x00000000, 0x00000000 }, /* HI_REGS */		\
   { 0x01000000, 0x00000000, 0x00000000 }, /* CC_REG */		\
   { 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */	\
   { 0x0200FFFF, 0x00000000, 0x00000000 }, /* GENERAL_REGS */	\
   { 0xFAFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF }  /* ALL_REGS */	\
+}
 /* The same information, inverted:
    Return the class number of the smallest class containing
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 #define REGNO_REG_CLASS(REGNO)  arm_regno_class (REGNO)
 /* FPA registers can't do subreg as all values are reformatted to internal
    precision.  VFP registers may only be accessed in the mode they
    were set.  */
 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)	\
   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)		\
    ? reg_classes_intersect_p (FPA_REGS, (CLASS))	\
      || reg_classes_intersect_p (VFP_REGS, (CLASS))	\
    : 0)
 /* We need to define this for LO_REGS on thumb.  Otherwise we can end up
    using r0-r4 for function arguments, r7 for the stack frame and don't
    have enough left over to do doubleword arithmetic.  */
 #define CLASS_LIKELY_SPILLED_P(CLASS)	\
     ((TARGET_THUMB && (CLASS) == LO_REGS)	\
      || (CLASS) == CC_REG)
 /* The class value for index registers, and the one for base regs.  */
 #define INDEX_REG_CLASS  (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
 #define BASE_REG_CLASS   (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
 /* For the Thumb the high registers cannot be used as base registers
    when addressing quantities in QI or HI mode; if we don't know the
    mode, then we must be conservative.  */
 #define MODE_BASE_REG_CLASS(MODE)					\
     (TARGET_ARM ? GENERAL_REGS :					\
      (((MODE) == SImode) ? BASE_REGS : LO_REGS))
 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
    instead of BASE_REGS.  */
 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS
 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
    registers explicitly used in the rtl to be used as spill registers
    but prevents the compiler from extending the lifetime of these
    registers.  */
 #define SMALL_REGISTER_CLASSES   TARGET_THUMB
 /* Get reg_class from a letter such as appears in the machine description.
    We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the
    ARM, but several more letters for the Thumb.  */
 #define REG_CLASS_FROM_LETTER(C)  	\
   (  (C) == 'f' ? FPA_REGS		\
    : (C) == 'v' ? CIRRUS_REGS		\
    : (C) == 'w' ? VFP_REGS		\
    : (C) == 'y' ? IWMMXT_REGS		\
    : (C) == 'z' ? IWMMXT_GR_REGS	\
    : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS)	\
    : TARGET_ARM ? NO_REGS		\
    : (C) == 'h' ? HI_REGS		\
    : (C) == 'b' ? BASE_REGS		\
    : (C) == 'k' ? STACK_REG		\
    : (C) == 'c' ? CC_REG		\
    : NO_REGS)