Fri Jan 25 22:38:00 2013 UTC ()
Fix a few c&p errors.


(matt)
diff -r1.12 -r1.13 src/sys/arch/arm/broadcom/bcm53xx_reg.h

cvs diff -r1.12 -r1.13 src/sys/arch/arm/broadcom/bcm53xx_reg.h (expand / switch to unified diff)

--- src/sys/arch/arm/broadcom/bcm53xx_reg.h 2012/12/12 00:00:38 1.12
+++ src/sys/arch/arm/broadcom/bcm53xx_reg.h 2013/01/25 22:37:59 1.13
@@ -227,34 +227,34 @@ @@ -227,34 +227,34 @@
227#define SRAB_RDL 0x003c 227#define SRAB_RDL 0x003c
228#endif 228#endif
229 229
230#ifdef MII_PRIVATE 230#ifdef MII_PRIVATE
231#define MII_INTERNAL 0x0038003 /* internal phy bitmask */ 231#define MII_INTERNAL 0x0038003 /* internal phy bitmask */
232#define MIIMGT 0x000 232#define MIIMGT 0x000
233#define MIIMGT_BYP __BIT(10) 233#define MIIMGT_BYP __BIT(10)
234#define MIIMGT_EXT __BIT(9) 234#define MIIMGT_EXT __BIT(9)
235#define MIIMGT_BSY __BIT(8) 235#define MIIMGT_BSY __BIT(8)
236#define MIIMGT_PRE __BIT(7) 236#define MIIMGT_PRE __BIT(7)
237#define MIIMGT_MDCDIV __BITS(6,0) 237#define MIIMGT_MDCDIV __BITS(6,0)
238#define MIICMD 0x004 238#define MIICMD 0x004
239#define MIICMD_SB __BITS(31,30) 239#define MIICMD_SB __BITS(31,30)
240#define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_OP) 240#define MIICMD_SB_DEF __SHIFTIN(1, MIICMD_SB)
241#define MIICMD_OP __BITS(29,28) 241#define MIICMD_OP __BITS(29,28)
242#define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP) 242#define MIICMD_OP_RD __SHIFTIN(2, MIICMD_OP)
243#define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP) 243#define MIICMD_OP_WR __SHIFTIN(1, MIICMD_OP)
244#define MIICMD_PHY __BITS(27,23) 244#define MIICMD_PHY __BITS(27,23)
245#define MIICMD_REG __BITS(22,18) 245#define MIICMD_REG __BITS(22,18)
246#define MIICMD_TA __BITS(17,16) 246#define MIICMD_TA __BITS(17,16)
247#define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_OP) 247#define MIICMD_TA_DEF __SHIFTIN(2, MIICMD_TA)
248#define MIICMD_DATA __BITS(15,0) 248#define MIICMD_DATA __BITS(15,0)
249 249
250#define MIICMD_RD_DEF (MIICMD_SB_DEF|MIICMD_OP_RD|MIICMD_TA_DEF) 250#define MIICMD_RD_DEF (MIICMD_SB_DEF|MIICMD_OP_RD|MIICMD_TA_DEF)
251#define MIICMD_WR_DEF (MIICMD_SB_DEF|MIICMD_OP_WR|MIICMD_TA_DEF) 251#define MIICMD_WR_DEF (MIICMD_SB_DEF|MIICMD_OP_WR|MIICMD_TA_DEF)
252#define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG)) 252#define MIICMD__PHYREG(p,r) (__SHIFTIN(p,MIICMD_PHY)|__SHIFTIN(r,MIICMD_REG))
253#define MIICMD_RD(p,r) (MIICMD_RD_DEF|MIICMD__PHYREG((p),(r))) 253#define MIICMD_RD(p,r) (MIICMD_RD_DEF|MIICMD__PHYREG((p),(r)))
254#define MIICMD_WR(p,r,v) (MIICMD_WR_DEF|MIICMD__PHYREG((p),(r))|(v)) 254#define MIICMD_WR(p,r,v) (MIICMD_WR_DEF|MIICMD__PHYREG((p),(r))|(v))
255#endif /* MII_PRIVATE */ 255#endif /* MII_PRIVATE */
256 256
257#ifdef RNG_PRIVATE 257#ifdef RNG_PRIVATE
258#define RNG_CTRL 0x000 258#define RNG_CTRL 0x000
259#define RNG_COMBLK2_OSC_DIS __BITS(27,22) 259#define RNG_COMBLK2_OSC_DIS __BITS(27,22)
260#define RNG_COMBLK1_OSC_DIS __BITS(21,16) 260#define RNG_COMBLK1_OSC_DIS __BITS(21,16)