When building for earm*, compile __aeabi_[df]cmpun.c and __aeabi_[il]div0.cdiff -r1.17 -r1.18 src/lib/libc/arch/arm/Makefile.inc
(matt)
--- src/lib/libc/arch/arm/Makefile.inc 2013/01/11 13:55:25 1.17
+++ src/lib/libc/arch/arm/Makefile.inc 2013/01/26 07:09:41 1.18
@@ -1,25 +1,24 @@ | @@ -1,25 +1,24 @@ | |||
1 | # $NetBSD: Makefile.inc,v 1.17 2013/01/11 13:55:25 matt Exp $ | 1 | # $NetBSD: Makefile.inc,v 1.18 2013/01/26 07:09:41 matt Exp $ | |
2 | 2 | |||
3 | .include <bsd.own.mk> | 3 | .include <bsd.own.mk> | |
4 | 4 | |||
5 | SRCS+= __aeabi_read_tp.S __sigaction14_sigtramp.c __sigtramp2.S | 5 | SRCS+= __aeabi_read_tp.S __sigaction14_sigtramp.c __sigtramp2.S | |
6 | 6 | |||
7 | CPPFLAGS += -I. | 7 | CPPFLAGS += -I. | |
8 | 8 | |||
9 | .if ${MACHINE_ARCH} == "earm" || ${MACHINE_ARCH} == "earmeb" | 9 | .if ${MACHINE_ARCH} == "earm" || ${MACHINE_ARCH} == "earmeb" | |
10 | SRCS+= __aeabi_ldivmod.S __aeabi_uldivmod.S | 10 | SRCS+= __aeabi_ldivmod.S __aeabi_uldivmod.S | |
11 | SRCS+= __aeabi_lcmp.c __aeabi_ulcmp.c | 11 | SRCS+= __aeabi_lcmp.c __aeabi_ulcmp.c | |
12 | #SRCS+= __aeabi_idiv0.c __aeabi_ldiv0.c | |||
13 | SRCS+= fixunsgen_ieee754.c fixunssfsi_ieee754.c | 12 | SRCS+= fixunsgen_ieee754.c fixunssfsi_ieee754.c | |
14 | SRCS+= fixunsgen64_ieee754.c fixunsdfsi_ieee754.c | 13 | SRCS+= fixunsgen64_ieee754.c fixunsdfsi_ieee754.c | |
15 | .endif | 14 | .endif | |
16 | 15 | |||
17 | .if ${MKSOFTFLOAT} != "no" | 16 | .if ${MKSOFTFLOAT} != "no" | |
18 | CPPFLAGS += -DSOFTFLOAT | 17 | CPPFLAGS += -DSOFTFLOAT | |
19 | 18 | |||
20 | # for earm, use the 64-bit softfloat | 19 | # for earm, use the 64-bit softfloat | |
21 | .if ${MACHINE_ARCH} == "arm" || ${MACHINE_ARCH} == "armeb" | 20 | .if ${MACHINE_ARCH} == "arm" || ${MACHINE_ARCH} == "armeb" | |
22 | SOFTFLOAT_BITS=32 | 21 | SOFTFLOAT_BITS=32 | |
23 | .endif | 22 | .endif | |
24 | 23 | |||
25 | .include <softfloat/Makefile.inc> | 24 | .include <softfloat/Makefile.inc> |
--- src/lib/libc/arch/arm/gen/Makefile.inc 2012/10/30 12:42:37 1.20
+++ src/lib/libc/arch/arm/gen/Makefile.inc 2013/01/26 07:09:41 1.21
@@ -1,26 +1,31 @@ | @@ -1,26 +1,31 @@ | |||
1 | # $NetBSD: Makefile.inc,v 1.20 2012/10/30 12:42:37 christos Exp $ | 1 | # $NetBSD: Makefile.inc,v 1.21 2013/01/26 07:09:41 matt Exp $ | |
2 | 2 | |||
3 | SRCS+= alloca.S byte_swap_2.S byte_swap_4.S bswap64.c divsi3.S \ | 3 | SRCS+= alloca.S byte_swap_2.S byte_swap_4.S bswap64.c divsi3.S \ | |
4 | fabs.c flt_rounds.c modsi3.S umodsi3.S divide.S divsi3.S udivsi3.S | 4 | fabs.c flt_rounds.c modsi3.S umodsi3.S divide.S divsi3.S udivsi3.S | |
5 | 5 | |||
6 | # Common ieee754 constants and functions | 6 | # Common ieee754 constants and functions | |
7 | SRCS+= infinityf_ieee754.c infinity_ieee754.c infinityl_dbl_ieee754.c | 7 | SRCS+= infinityf_ieee754.c infinity_ieee754.c infinityl_dbl_ieee754.c | |
8 | SRCS+= fpclassifyf_ieee754.c fpclassifyd_ieee754.c | 8 | SRCS+= fpclassifyf_ieee754.c fpclassifyd_ieee754.c | |
9 | SRCS+= isfinitef_ieee754.c isfinited_ieee754.c | 9 | SRCS+= isfinitef_ieee754.c isfinited_ieee754.c | |
10 | SRCS+= isinff_ieee754.c isinfd_ieee754.c | 10 | SRCS+= isinff_ieee754.c isinfd_ieee754.c | |
11 | SRCS+= isnanf_ieee754.c isnand_ieee754.c | 11 | SRCS+= isnanf_ieee754.c isnand_ieee754.c | |
12 | SRCS+= signbitf_ieee754.c signbitd_ieee754.c | 12 | SRCS+= signbitf_ieee754.c signbitd_ieee754.c | |
13 | 13 | |||
14 | .if ${MACHINE_ARCH:Mearm*} != "" | |||
15 | SRCS+= __aeabi_fcmpun.c __aeabi_dcmpun.c | |||
16 | SRCS+= __aeabi_idiv0.c __aeabi_ldiv0.c | |||
17 | .endif | |||
18 | ||||
14 | SRCS+= nanf.c | 19 | SRCS+= nanf.c | |
15 | 20 | |||
16 | SRCS+= setjmp.S | 21 | SRCS+= setjmp.S | |
17 | SRCS+= _setjmp.S | 22 | SRCS+= _setjmp.S | |
18 | SRCS+= sigsetjmp.S | 23 | SRCS+= sigsetjmp.S | |
19 | 24 | |||
20 | SRCS+= makecontext.c resumecontext.c swapcontext.S | 25 | SRCS+= makecontext.c resumecontext.c swapcontext.S | |
21 | 26 | |||
22 | SRCS+= _lwp.c | 27 | SRCS+= _lwp.c | |
23 | 28 | |||
24 | LSRCS.arm.gen= Lint_bswap16.c Lint_bswap32.c Lint_swapcontext.c | 29 | LSRCS.arm.gen= Lint_bswap16.c Lint_bswap32.c Lint_swapcontext.c | |
25 | LSRCS+= ${LSRCS.arm.gen} | 30 | LSRCS+= ${LSRCS.arm.gen} | |
26 | DPSRCS+= ${LSRCS.arm.gen} | 31 | DPSRCS+= ${LSRCS.arm.gen} |