Sat Jan 26 11:58:43 2013 UTC ()
add vchiq base and size


(jmcneill)
diff -r1.9 -r1.10 src/sys/arch/arm/broadcom/bcm2835reg.h
cvs diff -r1.9 -r1.10 src/sys/arch/arm/broadcom/bcm2835reg.h (expand / switch to unified diff)

--- src/sys/arch/arm/broadcom/bcm2835reg.h 2013/01/26 08:01:49 1.9
+++ src/sys/arch/arm/broadcom/bcm2835reg.h 2013/01/26 11:58:43 1.10
@@ -1,14 +1,14 @@ @@ -1,14 +1,14 @@
1/* $NetBSD: bcm2835reg.h,v 1.9 2013/01/26 08:01:49 skrll Exp $ */ 1/* $NetBSD: bcm2835reg.h,v 1.10 2013/01/26 11:58:43 jmcneill Exp $ */
2 2
3/*- 3/*-
4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved. 5 * All rights reserved.
6 * 6 *
7 * This code is derived from software contributed to The NetBSD Foundation 7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Nick Hudson 8 * by Nick Hudson
9 * 9 *
10 * Redistribution and use in source and binary forms, with or without 10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions 11 * modification, are permitted provided that the following conditions
12 * are met: 12 * are met:
13 * 1. Redistributions of source code must retain the above copyright 13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer. 14 * notice, this list of conditions and the following disclaimer.
@@ -83,26 +83,29 @@ @@ -83,26 +83,29 @@
83#define BCM2835_BUSADDR_CACHE_L2ONLY 0x80000000 83#define BCM2835_BUSADDR_CACHE_L2ONLY 0x80000000
84#define BCM2835_BUSADDR_CACHE_DIRECT 0xc0000000 84#define BCM2835_BUSADDR_CACHE_DIRECT 0xc0000000
85 85
86#define BCM2835_PERIPHERALS_VBASE \ 86#define BCM2835_PERIPHERALS_VBASE \
87 BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE) 87 BCM2835_IOPHYSTOVIRT(BCM2835_PERIPHERALS_BASE)
88#define BCM2835_STIMER_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ST_BASE) 88#define BCM2835_STIMER_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ST_BASE)
89#define BCM2835_PM_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_PM_BASE) 89#define BCM2835_PM_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_PM_BASE)
90#define BCM2835_UART0_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_UART0_BASE) 90#define BCM2835_UART0_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_UART0_BASE)
91#define BCM2835_EMMC_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_EMMC_BASE) 91#define BCM2835_EMMC_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_EMMC_BASE)
92 92
93#define BCM2835_ARMICU_BASE (BCM2835_ARM_BASE + 0x0200) 93#define BCM2835_ARMICU_BASE (BCM2835_ARM_BASE + 0x0200)
94#define BCM2835_ARMICU_SIZE 0x200 94#define BCM2835_ARMICU_SIZE 0x200
95 95
 96#define BCM2835_VCHIQ_BASE (BCM2835_ARM_BASE + 0x0800)
 97#define BCM2835_VCHIQ_SIZE 0x50
 98
96#define BCM2835_ARMMBOX_BASE (BCM2835_ARM_BASE + 0x0880) 99#define BCM2835_ARMMBOX_BASE (BCM2835_ARM_BASE + 0x0880)
97#define BCM2835_ARMMBOX_SIZE 0x40 100#define BCM2835_ARMMBOX_SIZE 0x40
98 101
99#define BCM2835_ARMICU_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ARMICU_BASE) 102#define BCM2835_ARMICU_VBASE BCM2835_IOPHYSTOVIRT(BCM2835_ARMICU_BASE)
100 103
101#define BCM2835_INTC_BASE (0x0) /* Relative to BCM2835_ARMICU_BASE */ 104#define BCM2835_INTC_BASE (0x0) /* Relative to BCM2835_ARMICU_BASE */
102 105
103/* Interrupt controller */ 106/* Interrupt controller */
104#define BCM2835_INTC_IRQBPENDING (BCM2835_INTC_BASE + 0x00) /* IRQ Basic pending */ 107#define BCM2835_INTC_IRQBPENDING (BCM2835_INTC_BASE + 0x00) /* IRQ Basic pending */
105#define BCM2835_INTC_IRQ1PENDING (BCM2835_INTC_BASE + 0x04) /* IRQ pending 1 */ 108#define BCM2835_INTC_IRQ1PENDING (BCM2835_INTC_BASE + 0x04) /* IRQ pending 1 */
106#define BCM2835_INTC_IRQ2PENDING (BCM2835_INTC_BASE + 0x08) /* IRQ pending 2 */ 109#define BCM2835_INTC_IRQ2PENDING (BCM2835_INTC_BASE + 0x08) /* IRQ pending 2 */
107#define BCM2835_INTC_FIQCTL (BCM2835_INTC_BASE + 0x0c) /* FIQ control */ 110#define BCM2835_INTC_FIQCTL (BCM2835_INTC_BASE + 0x0c) /* FIQ control */
108#define BCM2835_INTC_IRQ1ENABLE (BCM2835_INTC_BASE + 0x10) /* Enable IRQs 1 */ 111#define BCM2835_INTC_IRQ1ENABLE (BCM2835_INTC_BASE + 0x10) /* Enable IRQs 1 */