 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_bge.c,v 1.205 2013/02/26 11:03:17 msaitoh Exp $	*/
+/*	$NetBSD: if_bge.c,v 1.206 2013/02/26 11:06:23 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
 @@ -69,27 +69,27 @@
  * does not support external SSRAM.
+ *
  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  * brand name, which is functionally similar but lacks PCI-X support.
+ *
  * Without external SSRAM, you can only have at most 4 TX rings,
  * and the use of the mini RX ring is disabled. This seems to imply
  * that these features are simply not available on the BCM5701. As a
  * result, this driver does not implement any support for the mini RX
  * ring.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.205 2013/02/26 11:03:17 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_bge.c,v 1.206 2013/02/26 11:06:23 msaitoh Exp $");
 #include "vlan.h"
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/sockio.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/device.h>
 #include <sys/socket.h>
 #include <sys/sysctl.h>
 @@ -689,26 +689,27 @@ static const struct bge_revision {
 	{ BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
 	{ BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
 	{ BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
 	{ BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
 	{ BGE_CHIPID_BCM5755_C0, "BCM5755 C0" },
 	{ BGE_CHIPID_BCM5761_A0, "BCM5761 A0" },
 	{ BGE_CHIPID_BCM5761_A1, "BCM5761 A1" },
 	{ BGE_CHIPID_BCM5784_A0, "BCM5784 A0" },
 	{ BGE_CHIPID_BCM5784_A1, "BCM5784 A1" },
 	/* 5754 and 5787 share the same ASIC ID */
 	{ BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
 	{ BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
 	{ BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
 	{ BGE_CHIPID_BCM5906_A0, "BCM5906 A0" },
 	{ BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
 	{ BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
 	{ BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
 	{ BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
 	{ 0, NULL }
 };
 /*
  * Some defaults for major revisions, so that newer steppings
  * that we don't know about have a shot at working.
  */
 static const struct bge_revision bge_majorrevs[] = {
 @@ -2087,26 +2088,34 @@ bge_blockinit(struct bge_softc *sc)
 		/* Set up dummy disabled mini ring RCB */
 		rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
 		    BGE_RCB_FLAG_RING_DISABLED);
 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
 		    rcb->bge_maxlen_flags);
 		bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
 		    offsetof(struct bge_ring_data, bge_info),
 		    sizeof (struct bge_gib),
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
+	}
 	/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906) {
 		if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
 			CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
 			    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
+	}
 	/*
 	 * Set the BD ring replenish thresholds. The recommended
 	 * values are 1/8th the number of descriptors allocated to
 	 * each ring.
 	 */
 	i = BGE_STD_RX_RING_CNT / 8;
 	/*
 	 * Use a value of 8 for the following chips to workaround HW errata.
 	 * Some of these chips have been added based on empirical
 	 * evidence (they don't work unless this is done).
 	 */
 	if (BGE_IS_5705_PLUS(sc))
 @@ -2299,26 +2308,29 @@ bge_blockinit(struct bge_softc *sc)
 #endif
 	CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, sc->bge_local_ctrl_reg);
 	/* Turn on DMA completion state machine */
 	if (BGE_IS_5700_FAMILY(sc))
 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
 	/* Enable host coalescing bug fix; see Linux tg3.c */
 	if (BGE_IS_5755_PLUS(sc))
 		val |= BGE_WDMAMODE_STATUS_TAG_FIX;
 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785)
 		val |= BGE_WDMAMODE_BURST_ALL_DATA;
 	/* Turn on write DMA state machine */
 	CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
 	val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
 	if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5784 ||
 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5785 ||
 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM57780)
 		val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
 		    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
 		    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
 	if (sc->bge_flags & BGE_PCIE)
 		val |= BGE_RDMAMODE_FIFO_LONG_BURST;
 @@ -4294,26 +4306,27 @@ bge_start(struct ifnet *ifp)
 	sc->bge_tx_prodidx = prodidx;
 	/*
 	 * Set a timeout in case the chip goes out to lunch.
 	 */
 	ifp->if_timer = 5;
+}
 static int
 bge_init(struct ifnet *ifp)
+{
 	struct bge_softc *sc = ifp->if_softc;
 	const uint16_t *m;
 	uint32_t mode;
 	int s, error = 0;
 	s = splnet();
 	ifp = &sc->ethercom.ec_if;
 	/* Cancel pending I/O and flush buffers. */
 	bge_stop(ifp, 0);
 	bge_stop_fw(sc);
 	bge_sig_pre_reset(sc, BGE_RESET_START);
 	bge_reset(sc);
 	bge_sig_legacy(sc, BGE_RESET_START);
 @@ -4374,31 +4387,39 @@ bge_init(struct ifnet *ifp)
 			    "5705 A0 chip failed to load RX ring\n");
+	}
 	/* Init jumbo RX ring. */
 	if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
 		bge_init_rx_ring_jumbo(sc);
 	/* Init our RX return ring index */
 	sc->bge_rx_saved_considx = 0;
 	/* Init TX ring. */
 	bge_init_tx_ring(sc);
 	/* Enable TX MAC state machine lockup fix. */
 	mode = CSR_READ_4(sc, BGE_TX_MODE);
 	if (BGE_IS_5755_PLUS(sc) ||
 	    BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
 		mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
 	/* Turn on transmitter */
-	BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
+	CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
 	DELAY(100);
 	/* Turn on receiver */
 	BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 	DELAY(10);
 	CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
 	/* Tell firmware we're alive. */
 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 	/* Enable host interrupts. */
 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
 	if ((error = bge_ifmedia_upd(ifp)) != 0)
 		goto out;

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_bgereg.h,v 1.59 2013/02/26 11:03:17 msaitoh Exp $	*/
+/*	$NetBSD: if_bgereg.h,v 1.60 2013/02/26 11:06:23 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001 Wind River Systems
  * Copyright (c) 1997, 1998, 1999, 2001
  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
 @@ -308,26 +308,27 @@
 #define BGE_CHIPID_BCM5752_A2		0x6002
 #define BGE_CHIPID_BCM5714_B0		0x8000
 #define BGE_CHIPID_BCM5714_B3		0x8003
 #define BGE_CHIPID_BCM5715_A0		0x9000
 #define BGE_CHIPID_BCM5715_A1		0x9001
 #define BGE_CHIPID_BCM5715_A3		0x9003
 #define BGE_CHIPID_BCM5755_A0		0xa000
 #define BGE_CHIPID_BCM5755_A1		0xa001
 #define BGE_CHIPID_BCM5755_A2		0xa002
 #define BGE_CHIPID_BCM5755_C0		0xa200
 #define BGE_CHIPID_BCM5787_A0		0xb000
 #define BGE_CHIPID_BCM5787_A1		0xb001
 #define BGE_CHIPID_BCM5787_A2		0xb002
 #define	BGE_CHIPID_BCM5906_A0		0xc000
 #define BGE_CHIPID_BCM5906_A1		0xc001
 #define BGE_CHIPID_BCM5906_A2		0xc002
 #define BGE_CHIPID_BCM57762		0x57766000
 #define BGE_CHIPID_BCM57780_A0		0x57780000
 #define BGE_CHIPID_BCM57780_A1		0x57780001
 /* shorthand one */
 #define BGE_ASICREV(x)			((x) >> 12)
 #define BGE_ASICREV_BCM5700		0x07
 #define BGE_ASICREV_BCM5701		0x00
 #define BGE_ASICREV_BCM5703		0x01
 #define BGE_ASICREV_BCM5704		0x02
 #define BGE_ASICREV_BCM5705		0x03
 @@ -724,26 +725,27 @@
 /* TX backoff seed register */
 #define BGE_TX_BACKOFF_SEED_MASK	0x3F
 /* Autopoll status register */
 #define BGE_AUTOPOLLSTS_ERROR		0x00000001
 /* Transmit MAC mode register */
 #define BGE_TXMODE_RESET		0x00000001
 #define BGE_TXMODE_ENABLE		0x00000002
 #define BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
 #define BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
 #define BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
 #define	BGE_TXMODE_MBUF_LOCKUP_FIX	0x00000100
 /* Transmit MAC status register */
 #define BGE_TXSTAT_RX_XOFFED		0x00000001
 #define BGE_TXSTAT_SENT_XOFF		0x00000002
 #define BGE_TXSTAT_SENT_XON		0x00000004
 #define BGE_TXSTAT_LINK_UP		0x00000008
 #define BGE_TXSTAT_ODI_UFLOW		0x00000010
 #define BGE_TXSTAT_ODI_OFLOW		0x00000020
 /* Transmit MAC lengths register */
 #define BGE_TXLEN_SLOTTIME		0x000000FF
 #define BGE_TXLEN_IPG			0x00000F00
 #define BGE_TXLEN_CRS			0x00003000
 @@ -810,26 +812,27 @@
 #define BGE_MIMODE_SHORTPREAMBLE	0x00000002
 #define BGE_MIMODE_AUTOPOLL		0x00000010
 #define BGE_MIMODE_CLKCNT		0x001F0000
 /*
  * Send data initiator control registers.
  */
 #define BGE_SDI_MODE			0x0C00
 #define BGE_SDI_STATUS			0x0C04
 #define BGE_SDI_STATS_CTL		0x0C08
 #define BGE_SDI_STATS_ENABLE_MASK	0x0C0C
 #define BGE_SDI_STATS_INCREMENT_MASK	0x0C10
 #define	BGE_ISO_PKT_TX			0x0C20
 #define BGE_LOCSTATS_COS0		0x0C80
 #define BGE_LOCSTATS_COS1		0x0C84
 #define BGE_LOCSTATS_COS2		0x0C88
 #define BGE_LOCSTATS_COS3		0x0C8C
 #define BGE_LOCSTATS_COS4		0x0C90
 #define BGE_LOCSTATS_COS5		0x0C84
 #define BGE_LOCSTATS_COS6		0x0C98
 #define BGE_LOCSTATS_COS7		0x0C9C
 #define BGE_LOCSTATS_COS8		0x0CA0
 #define BGE_LOCSTATS_COS9		0x0CA4
 #define BGE_LOCSTATS_COS10		0x0CA8
 #define BGE_LOCSTATS_COS11		0x0CAC
 #define BGE_LOCSTATS_COS12		0x0CB0
 @@ -1425,26 +1428,27 @@
 /* Write DMA mode register */
 #define BGE_WDMAMODE_RESET		0x00000001
 #define BGE_WDMAMODE_ENABLE		0x00000002
 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_WDMAMODE_PCI_PERR_ATTN	0x00000010
 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_WDMAMODE_LOCREAD_TOOBIG	0x00000200
 #define BGE_WDMAMODE_ALL_ATTNS		0x000003FC
 #define BGE_WDMAMODE_STATUS_TAG_FIX	0x20000000
 #define	BGE_WDMAMODE_BURST_ALL_DATA	0xC0000000
 /* Write DMA status register */
 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
 #define BGE_WDMASTAT_PCI_PERR_ATTN	0x00000010
 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
 #define BGE_WDMASTAT_LOCREAD_TOOBIG	0x00000200
 /*