 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wm.c,v 1.248 2013/04/21 19:59:41 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.249 2013/06/02 09:36:22 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -66,27 +66,27 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.248 2013/04/21 19:59:41 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.249 2013/06/02 09:36:22 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 @@ -1035,26 +1035,38 @@ static const struct wm_product {
 	  "I210 Gigabit Ethernet (Fiber)",
 	  WM_T_I210,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
 	  "I210 Gigabit Ethernet (SERDES)",
 	  WM_T_I210,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
 	  "I210 Gigabit Ethernet (SGMII)",
 	  WM_T_I210,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
 	  "I211 Ethernet (COPPER)",
 	  WM_T_I211,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
 	  "I217 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
 	  "I217 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
 	  "I218 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
 	  "I218 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ 0,			0,
 	  NULL,
 ,			0 },
 };
 #ifdef WM_EVENT_COUNTERS
 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
 #endif /* WM_EVENT_COUNTERS */
 #if 0 /* Not currently used */
 static inline uint32_t
 wm_io_read(struct wm_softc *sc, int reg)
+{
 @@ -1337,27 +1349,28 @@ wm_attach(device_t parent, device_t self
 		    "Communication Streaming Architecture\n");
 		if (sc->sc_type == WM_T_82547) {
 			callout_init(&sc->sc_txfifo_ch, 0);
 			callout_setfunc(&sc->sc_txfifo_ch,
 					wm_82547_txfifo_stall, sc);
 			aprint_verbose_dev(sc->sc_dev,
 			    "using 82547 Tx FIFO stall work-around\n");
+		}
 	} else if (sc->sc_type >= WM_T_82571) {
 		sc->sc_flags |= WM_F_PCIE;
 		if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 		    && (sc->sc_type != WM_T_ICH10)
 		    && (sc->sc_type != WM_T_PCH)
-		    && (sc->sc_type != WM_T_PCH2)) {
+		    && (sc->sc_type != WM_T_PCH2)
 		    && (sc->sc_type != WM_T_PCH_LPT)) {
 			sc->sc_flags |= WM_F_EEPROM_SEMAPHORE;
 			/* ICH* and PCH* have no PCIe capability registers */
 			if (pci_get_capability(pa->pa_pc, pa->pa_tag,
 				PCI_CAP_PCIEXPRESS, &sc->sc_pcixe_capoff,
 				NULL) == 0)
 				aprint_error_dev(sc->sc_dev,
 				    "unable to find PCIe capability\n");
+		}
 		aprint_verbose_dev(sc->sc_dev, "PCI-Express bus\n");
 	} else {
 		reg = CSR_READ(sc, WMREG_STATUS);
 		if (reg & STATUS_BUS64)
 			sc->sc_flags |= WM_F_BUS64;
 @@ -1506,46 +1519,48 @@ wm_attach(device_t parent, device_t self
 			aprint_error_dev(sc->sc_dev,
 			    "unable to create Rx DMA map %d error = %d\n",
 			    i, error);
 			goto fail_5;
+		}
 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
+	}
 	/* clear interesting stat counters */
 	CSR_READ(sc, WMREG_COLC);
 	CSR_READ(sc, WMREG_RXERRC);
 	/* get PHY control from SMBus to PCIe */
-	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2))
+	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT))
 		wm_smbustopci(sc);
 	/*
 	 * Reset the chip to a known state.
 	 */
 	wm_reset(sc);
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		if (wm_check_mng_mode(sc) != 0)
 			wm_get_hw_control(sc);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * Get some information about the EEPROM.
 	 */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 @@ -1602,26 +1617,27 @@ wm_attach(device_t parent, device_t self
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_80003:
 		/* SPI */
 		wm_set_spiaddrbits(sc);
 		sc->sc_flags |= WM_F_EEPROM_EERDEEWR | WM_F_SWFW_SYNC;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* FLASH */
 		sc->sc_flags |= WM_F_EEPROM_FLASH | WM_F_SWFWHW_SYNC;
 		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, WM_ICH8_FLASH);
 		if (pci_mapreg_map(pa, WM_ICH8_FLASH, memtype, 0,
 		    &sc->sc_flasht, &sc->sc_flashh, NULL, NULL)) {
 			aprint_error_dev(sc->sc_dev,
 			    "can't map FLASH registers\n");
 			return;
+		}
 		reg = ICH8_FLASH_READ32(sc, ICH_FLASH_GFPREG);
 		sc->sc_ich8_flash_base = (reg & ICH_GFPREG_BASE_MASK) *
 						ICH_FLASH_SECTOR_SIZE;
 		sc->sc_ich8_flash_bank_size =
 @@ -1752,26 +1768,27 @@ wm_attach(device_t parent, device_t self
 		wm_read_eeprom(sc, (sc->sc_funcid == 1) ? EEPROM_OFF_CFG3_PORTB
 		    : EEPROM_OFF_CFG3_PORTA, 1, &eeprom_data);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* XXX The funcid should be checked on some devices */
 		apme_mask = WUC_APME;
 		eeprom_data = CSR_READ(sc, WMREG_WUC);
 		break;
+	}
 	/* Check for WM_F_WOL flag after the setting of the EEPROM stuff */
 	if ((eeprom_data & apme_mask) != 0)
 		sc->sc_flags |= WM_F_WOL;
 #ifdef WM_DEBUG
 	if ((sc->sc_flags & WM_F_WOL) != 0)
 		printf("WOL\n");
 #endif
 @@ -1854,27 +1871,28 @@ wm_attach(device_t parent, device_t self
 		if ((val & EEPROM_K1_CONFIG_ENABLE) != 0)
 			sc->sc_nvm_k1_enabled = 1;
 		else
 			sc->sc_nvm_k1_enabled = 0;
+	}
 	/*
 	 * Determine if we're TBI,GMII or SGMII mode, and initialize the
 	 * media structures accordingly.
 	 */
 	if (sc->sc_type == WM_T_ICH8 || sc->sc_type == WM_T_ICH9
 	    || sc->sc_type == WM_T_ICH10 || sc->sc_type == WM_T_PCH
-	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_82573
+	    || sc->sc_type == WM_T_PCH2 || sc->sc_type == WM_T_PCH_LPT
 	    || sc->sc_type == WM_T_82573
 	    || sc->sc_type == WM_T_82574 || sc->sc_type == WM_T_82583) {
 		/* STATUS_TBIMODE reserved/reused, can't rely on it */
 		wm_gmii_mediainit(sc, wmp->wmp_product);
 	} else if (sc->sc_type < WM_T_82543 ||
 	    (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
 		if (wmp->wmp_flags & WMP_F_1000T)
 			aprint_error_dev(sc->sc_dev,
 			    "WARNING: TBIMODE set on 1000BASE-T product!\n");
 		wm_tbi_mediainit(sc);
 	} else {
 		switch (sc->sc_type) {
 		case WM_T_82575:
 		case WM_T_82576:
 @@ -1943,26 +1961,27 @@ wm_attach(device_t parent, device_t self
 	case WM_T_82572:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH2:	/* PCH2 supports 9K frame size */
 	case WM_T_PCH_LPT:
 		/* XXX limited to 9234 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_PCH:
 		/* XXX limited to 4096 */
 		sc->sc_ethercom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82583:
 	case WM_T_ICH8:
 		/* No support for jumbo frame */
 		break;
 @@ -4044,26 +4063,27 @@ wm_reset(struct wm_softc *sc)
 	case WM_T_82583:
 		sc->sc_pba = PBA_20K;
 		break;
 	case WM_T_ICH8:
 		sc->sc_pba = PBA_8K;
 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
 		break;
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 		sc->sc_pba = PBA_10K;
 		break;
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->sc_pba = PBA_26K;
 		break;
 	default:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
 		    PBA_40K : PBA_48K;
 		break;
+	}
 	CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
 	/* Prevent the PCI-E bus from sticking */
 	if (sc->sc_flags & WM_F_PCIE) {
 		int timeout = 800;
 @@ -4158,26 +4178,27 @@ wm_reset(struct wm_softc *sc)
 		break;
 	case WM_T_80003:
 		mask = swfwphysem[sc->sc_funcid];
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		wm_get_swfw_semaphore(sc, mask);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		wm_put_swfw_semaphore(sc, mask);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (wm_check_reset_block(sc) == 0) {
 			/*
 			 * Gate automatic PHY configuration by hardware on
 			 * non-managed 82579
 			 */
 			if ((sc->sc_type == WM_T_PCH2)
 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
 				!= 0))
 				wm_gate_hw_phy_config_ich8lan(sc, 1);
 			reg |= CTRL_PHY_RESET;
 @@ -4267,26 +4288,27 @@ wm_reset(struct wm_softc *sc)
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		break;
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		wm_lan_init_done(sc);
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
+	}
 	/* Check whether EEPROM is present or not */
 	switch (sc->sc_type) {
 	case WM_T_82575:
 	case WM_T_82576:
 #if 0 /* XXX */
 	case WM_T_82580:
 	case WM_T_82580ER:
 @@ -4400,26 +4422,27 @@ wm_init(struct ifnet *ifp)
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		if (wm_check_mng_mode(sc) != 0)
 			wm_get_hw_control(sc);
 		break;
 	default:
 		break;
+	}
 	/* Reset the PHY. */
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_gmii_reset(sc);
 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
 @@ -4582,26 +4605,27 @@ wm_init(struct ifnet *ifp)
 	/* Writes the control register. */
 	wm_set_vlan(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		int val;
 		switch (sc->sc_type) {
 		case WM_T_80003:
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
 			 * polling the phy; this fixes erroneous timeouts at
 			 * 10Mbps.
 			 */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
 xFFFF);
 			val = wm_kmrn_readreg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM);
 			val |= 0x3F;
 			wm_kmrn_writereg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM, val);
 @@ -4922,26 +4946,27 @@ wm_get_auto_rd_done(struct wm_softc *sc)
+}
 void
 wm_lan_init_done(struct wm_softc *sc)
+{
 	uint32_t reg = 0;
 	int i;
 	/* wait for eeprom to reload */
 	switch (sc->sc_type) {
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		for (i = 0; i < WM_ICH8_LAN_INIT_TIMEOUT; i++) {
 			reg = CSR_READ(sc, WMREG_STATUS);
 			if ((reg & STATUS_LAN_INIT_DONE) != 0)
 				break;
 			delay(100);
+		}
 		if (i >= WM_ICH8_LAN_INIT_TIMEOUT) {
 			log(LOG_ERR, "%s: %s: lan_init_done failed to "
 			    "complete\n", device_xname(sc->sc_dev), __func__);
+		}
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 @@ -5003,26 +5028,27 @@ wm_get_cfg_done(struct wm_softc *sc)
 				break;
 			delay(1000);
+		}
 		if (i >= WM_PHY_CFG_TIMEOUT) {
 			DPRINTF(WM_DEBUG_GMII, ("%s: %s failed\n",
 				device_xname(sc->sc_dev), __func__));
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		if (sc->sc_type >= WM_T_PCH) {
 			reg = CSR_READ(sc, WMREG_STATUS);
 			if ((reg & STATUS_PHYRA) != 0)
 				CSR_WRITE(sc, WMREG_STATUS,
 				    reg & ~STATUS_PHYRA);
+		}
 		delay(10*1000);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 @@ -5287,104 +5313,131 @@ wm_read_eeprom_spi(struct wm_softc *sc,
 	for (i = 0; i < wordcnt; i++) {
 		wm_eeprom_recvbits(sc, &val, 16);
 		data[i] = ((val >> 8) & 0xff) | ((val & 0xff) << 8);
+	}
 	/* Raise CS and clear SK. */
 	reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
 	CSR_WRITE(sc, WMREG_EECD, reg);
 	delay(2);
 	return 0;
+}
-#define EEPROM_CHECKSUM		0xBABA
+#define NVM_CHECKSUM			0xBABA
-#define EEPROM_SIZE		0x0040
+#define EEPROM_SIZE			0x0040
 #define NVM_COMPAT			0x0003
 #define NVM_COMPAT_VALID_CHECKSUM	0x0001
 #define NVM_FUTURE_INIT_WORD1			0x0019
 #define NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM	0x0040
 /*
  * wm_validate_eeprom_checksum
+ *
  * The checksum is defined as the sum of the first 64 (16 bit) words.
  */
 static int
 wm_validate_eeprom_checksum(struct wm_softc *sc)
+{
-	uint16_t checksum;
+	uint16_t checksum, valid_checksum;
 	uint16_t eeprom_data;
 	uint16_t csum_wordaddr;
 	int i;
 	checksum = 0;
 	/* Don't check for I211 */
 	if (sc->sc_type == WM_T_I211)
 		return 0;
 	if (sc->sc_type == WM_T_PCH_LPT) {
 		printf("[PCH_LPT]");
 		csum_wordaddr = NVM_COMPAT;
 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
 	} else {
 		csum_wordaddr = NVM_FUTURE_INIT_WORD1;
 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
+	}
 #ifdef WM_DEBUG
 	/* Dump EEPROM image for debug */
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
-	    || (sc->sc_type == WM_T_PCH2)) {
+	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
-		wm_read_eeprom(sc, 0x19, 1, &eeprom_data);
+		wm_read_eeprom(sc, csum_wordaddr, 1, &eeprom_data);
-		if ((eeprom_data & 0x40) == 0) {
+		if ((eeprom_data & valid_checksum) == 0) {
-			DPRINTF(WM_DEBUG_NVM,("%s: NVM need to be updated\n",
+			DPRINTF(WM_DEBUG_NVM,
-				device_xname(sc->sc_dev)));
+			    ("%s: NVM need to be updated (%04x != %04x)\n",
 				device_xname(sc->sc_dev), eeprom_data,
 				    valid_checksum));
+		}
+	}
 	if ((wm_debug & WM_DEBUG_NVM) != 0) {
 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
 		for (i = 0; i < EEPROM_SIZE; i++) {
 			if (wm_read_eeprom(sc, i, 1, &eeprom_data))
 				printf("XX ");
 			else
 				printf("%04x ", eeprom_data);
 			if (i % 8 == 7)
 				printf("\n");
+		}
+	}
 #endif /* WM_DEBUG */
 	for (i = 0; i < EEPROM_SIZE; i++) {
 		if (wm_read_eeprom(sc, i, 1, &eeprom_data))
 			return 1;
 		checksum += eeprom_data;
+	}
-	if (checksum != (uint16_t) EEPROM_CHECKSUM)
+	if (checksum != (uint16_t) NVM_CHECKSUM) {
-		return 1;
+#ifdef WM_DEBUG
 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
 #endif
 		/*
 		 * XXX quick hack for non-updated NVM.
 		 * Check only last 12bit until wm_write_eeprom() will be
 		 * implemented.
 		 */
 		if ((checksum & 0x0fff) != ((uint16_t)NVM_CHECKSUM & 0x0fff))
 			return 1;
+	}
 	return 0;
+}
 /*
  * wm_read_eeprom:
+ *
  *	Read data from the serial EEPROM.
  */
 static int
 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 	int rv;
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		return 1;
 	if (wm_acquire_eeprom(sc))
 		return 1;
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
-	    || (sc->sc_type == WM_T_PCH2))
+	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
 		rv = wm_read_eeprom_ich8(sc, word, wordcnt, data);
 	else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
 		rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
 	else if (sc->sc_flags & WM_F_EEPROM_SPI)
 		rv = wm_read_eeprom_spi(sc, word, wordcnt, data);
 	else
 		rv = wm_read_eeprom_uwire(sc, word, wordcnt, data);
 	wm_release_eeprom(sc);
 	return rv;
+}
 static int
 @@ -5644,27 +5697,27 @@ wm_set_ral(struct wm_softc *sc, const ui
  *	multicast filter.
  */
 static uint32_t
 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
+{
 	static const int lo_shift[4] = { 4, 3, 2, 0 };
 	static const int hi_shift[4] = { 4, 5, 6, 8 };
 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
 	uint32_t hash;
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
-	    || (sc->sc_type == WM_T_PCH2)) {
+	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
 		return (hash & 0x3ff);
+	}
 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
 	return (hash & 0xfff);
+}
 /*
  * wm_set_filter:
+ *
 @@ -5692,70 +5745,72 @@ wm_set_filter(struct wm_softc *sc)
 		sc->sc_rctl |= RCTL_BAM;
 	if (ifp->if_flags & IFF_PROMISC) {
 		sc->sc_rctl |= RCTL_UPE;
 		goto allmulti;
+	}
 	/*
 	 * Set the station address in the first RAL slot, and
 	 * clear the remaining slots.
 	 */
 	if (sc->sc_type == WM_T_ICH8)
 		size = WM_RAL_TABSIZE_ICH8 -1;
 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
-	    || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2))
+	    || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_RAL_TABSIZE_ICH8;
 	else if (sc->sc_type == WM_T_82575)
 		size = WM_RAL_TABSIZE_82575;
 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
 		size = WM_RAL_TABSIZE_82576;
 	else if (sc->sc_type == WM_T_I350)
 		size = WM_RAL_TABSIZE_I350;
 	else
 		size = WM_RAL_TABSIZE;
 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 	for (i = 1; i < size; i++)
 		wm_set_ral(sc, NULL, i);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
-	    || (sc->sc_type == WM_T_PCH2))
+	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_ICH8_MC_TABSIZE;
 	else
 		size = WM_MC_TABSIZE;
 	/* Clear out the multicast table. */
 	for (i = 0; i < size; i++)
 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			goto allmulti;
+		}
 		hash = wm_mchash(sc, enm->enm_addrlo);
 		reg = (hash >> 5);
 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
-		    || (sc->sc_type == WM_T_PCH2))
+		    || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT))
 			reg &= 0x1f;
 		else
 			reg &= 0x7f;
 		bit = hash & 0x1f;
 		hash = CSR_READ(sc, mta_reg + (reg << 2));
 		hash |= 1U << bit;
 		/* XXX Hardware bug?? */
 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
 @@ -6088,26 +6143,27 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		rv = wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		rv = wm_get_swfwhw_semaphore(sc);
 		break;
 	default:
 		/* nothing to do*/
 		rv = 0;
 		break;
+	}
 	if (rv != 0) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 @@ -6174,26 +6230,27 @@ wm_gmii_reset(struct wm_softc *sc)
 		if ((sc->sc_type == WM_T_82541)
 		    || (sc->sc_type == WM_T_82541_2)
 		    || (sc->sc_type == WM_T_82547)
 		    || (sc->sc_type == WM_T_82547_2)) {
 			/* workaround for igp are done in igp_reset() */
 			/* XXX add code to set LED after phy reset */
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		delay(100);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		delay(150);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	/* release PHY semaphore */
 @@ -6211,26 +6268,27 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		wm_put_swfwhw_semaphore(sc);
 		break;
 	default:
 		/* nothing to do*/
 		rv = 0;
 		break;
+	}
 	/* get_cfg_done */
 	wm_get_cfg_done(sc);
 	/* extra setup */
 	switch (sc->sc_type) {
 @@ -6259,26 +6317,27 @@ wm_gmii_reset(struct wm_softc *sc)
 	case WM_T_82583:
 	case WM_T_80003:
 		/* null */
 		break;
 	case WM_T_82541:
 	case WM_T_82547:
 		/* XXX Configure actively LED after PHY reset */
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* Allow time for h/w to get to a quiescent state afer reset */
 		delay(10*1000);
 		if (sc->sc_type == WM_T_PCH)
 			wm_hv_phy_workaround_ich8lan(sc);
 		if (sc->sc_type == WM_T_PCH2)
 			wm_lv_phy_workaround_ich8lan(sc);
 		if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) {
 			/*
 			 * dummy read to clear the phy wakeup bit after lcd
 			 * reset
 @@ -6440,30 +6499,30 @@ wm_gmii_mediainit(struct wm_softc *sc, p
 			for (i = 1; i < 8; i++)
 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
 				    i, MII_OFFSET_ANY, MIIF_DOPAUSE);
 			/* restore previous sfp cage power state */
 			CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
+		}
 	} else {
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
-	 * If the MAC is PCH2 and failed to detect MII PHY, call
+	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
 	 */
-	if ((sc->sc_type == WM_T_PCH2) &&
+	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
 	    (LIST_FIRST(&mii->mii_phys) == NULL)) {
 		wm_set_mdio_slow_mode_hv(sc);
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
 	 * (For ICH8 variants)
 	 * If PHY detection failed, use BM's r/w function and retry.
 	 */
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* if failed, retry with *_bm_* */
 		mii->mii_readreg = wm_gmii_bm_readreg;
 @@ -7759,26 +7818,27 @@ wm_read_ich8_word(struct wm_softc *sc, u
+}
 static int
 wm_check_mng_mode(struct wm_softc *sc)
+{
 	int rv;
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		rv = wm_check_mng_mode_ich8lan(sc);
 		break;
 	case WM_T_82574:
 	case WM_T_82583:
 		rv = wm_check_mng_mode_82574(sc);
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_80003:
 		rv = wm_check_mng_mode_generic(sc);
 		break;
 	default:
 @@ -7860,26 +7920,27 @@ wm_enable_mng_pass_thru(struct wm_softc
+}
 static int
 wm_check_reset_block(struct wm_softc *sc)
+{
 	uint32_t reg;
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_FWSM);
 		if ((reg & FWSM_RSPCIPHY) != 0)
 			return 0;
 		else
 			return -1;
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 		reg = CSR_READ(sc, WMREG_MANC);
 @@ -7906,26 +7967,27 @@ wm_get_hw_control(struct wm_softc *sc)
 		reg = CSR_READ(sc, WMREG_SWSM);
 		CSR_WRITE(sc, WMREG_SWSM, reg | SWSM_DRV_LOAD);
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_DRV_LOAD);
 		break;
 	default:
 		break;
+	}
+}
 static void
 wm_release_hw_control(struct wm_softc *sc)
+{
 	uint32_t reg;
 @@ -8371,26 +8433,27 @@ wm_get_wakeup(struct wm_softc *sc)
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 #endif
 		if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE_MASK) != 0)
 			sc->sc_flags |= WM_F_ARC_SUBSYS_VALID;
 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->sc_flags |= WM_F_HAS_AMT;
 		sc->sc_flags |= WM_F_ASF_FIRMWARE_PRES;
 		break;
 	default:
 		break;
+	}
 	/* 1: HAS_MANAGE */
 	if (wm_enable_mng_pass_thru(sc) != 0)
 		sc->sc_flags |= WM_F_HAS_MANAGE;
 #ifdef WM_DEBUG
 	printf("\n");
 @@ -8446,26 +8509,27 @@ wm_enable_wakeup(struct wm_softc *sc)
 	/* Advertise the wakeup capability */
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_SWDPIN(2)
 	    | CTRL_SWDPIN(3));
 	CSR_WRITE(sc, WMREG_WUC, WUC_APME);
 	/* ICH workaround */
 	switch (sc->sc_type) {
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* Disable gig during WOL */
 		reg = CSR_READ(sc, WMREG_PHY_CTRL);
 		reg |= PHY_CTRL_D0A_LPLU | PHY_CTRL_GBE_DIS;
 		CSR_WRITE(sc, WMREG_PHY_CTRL, reg);
 		if (sc->sc_type == WM_T_PCH)
 			wm_gmii_reset(sc);
 		/* Power down workaround */
 		if (sc->sc_phytype == WMPHY_82577) {
 			struct mii_softc *child;
 			/* Assume that the PHY is copper */
 			child = LIST_FIRST(&sc->sc_mii.mii_phys);

 @@ -1,14 +1,14 @@
-/*	$NetBSD: if_wmvar.h,v 1.15 2013/04/18 12:42:03 msaitoh Exp $	*/
+/*	$NetBSD: if_wmvar.h,v 1.16 2013/06/02 09:36:22 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
 @@ -119,29 +119,27 @@ typedef enum {
 	WM_T_82575,			/* i82575 */
 	WM_T_82576,			/* i82576 */
 	WM_T_82580,			/* i82580 */
 	WM_T_82580ER,			/* i82580ER */
 	WM_T_I350,			/* I350 */
 	WM_T_I210,			/* I210 */
 	WM_T_I211,			/* I211 */
 	WM_T_80003,			/* i80003 */
 	WM_T_ICH8,			/* ICH8 LAN */
 	WM_T_ICH9,			/* ICH9 LAN */
 	WM_T_ICH10,			/* ICH10 LAN */
 	WM_T_PCH,			/* PCH LAN */
 	WM_T_PCH2,			/* PCH2 LAN */
 #if 0
 	WM_T_PCH_LPT,			/* PCH LPT LAN (I21[78]) */
 #endif
 } wm_chip_type;
 typedef enum {
 	WMPHY_UNKNOWN = 0,
 	WMPHY_NONE,
 	WMPHY_M88,
 	WMPHY_IGP,
 	WMPHY_IGP_2,
 	WMPHY_GG82563,
 	WMPHY_IGP_3,
 	WMPHY_IFE,
 	WMPHY_BM,
 	WMPHY_82577,