 @@ -1,1078 +1,1078 @@
-/*	$NetBSD: if_wm.c,v 1.253 2013/06/04 16:55:07 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.254 2013/06/11 10:07:09 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.253 2013/06/04 16:55:07 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.254 2013/06/11 10:07:09 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/rnd.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		0x01
 #define	WM_DEBUG_TX		0x02
 #define	WM_DEBUG_RX		0x04
 #define	WM_DEBUG_GMII		0x08
 #define	WM_DEBUG_MANAGE		0x10
 #define	WM_DEBUG_NVM		0x20
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(sc)	((sc)->sc_txnum)
 #define	WM_TXQUEUELEN_MASK(sc)	(WM_TXQUEUELEN(sc) - 1)
 #define	WM_TXQUEUE_GC(sc)	(WM_TXQUEUELEN(sc) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(sc)		((sc)->sc_ntxdesc)
 #define	WM_NTXDESC_MASK(sc)	(WM_NTXDESC(sc) - 1)
 #define	WM_TXDESCSIZE(sc)	(WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
 #define	WM_NEXTTX(sc, x)	(((x) + 1) & WM_NTXDESC_MASK(sc))
 #define	WM_NEXTTXS(sc, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(sc))
 #define	WM_MAXTXDMA		round_page(IP_MAXPACKET) /* for TSO */
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 /*
  * Control structures are DMA'd to the i82542 chip.  We allocate them in
  * a single clump that maps to a single DMA segment to make several things
  * easier.
  */
 struct wm_control_data_82544 {
 	/*
 	 * The receive descriptors.
 	 */
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	/*
 	 * The transmit descriptors.  Put these at the end, because
 	 * we might use a smaller number of them.
 	 */
 	union {
 		wiseman_txdesc_t wcdu_txdescs[WM_NTXDESC_82544];
 		nq_txdesc_t      wcdu_nq_txdescs[WM_NTXDESC_82544];
 	} wdc_u;
 };
 struct wm_control_data_82542 {
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
 };
 #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
 #define	WM_CDTXOFF(x)	WM_CDOFF(wdc_u.wcdu_txdescs[(x)])
 #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers.  Each descriptor gets a
  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
  * more than one buffer, we chain them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability register offset */
 	const struct wm_product *sc_wmp; /* Pointer to the wm_product entry */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	int sc_if_flags;		/* last if_flags */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	int sc_align_tweak;
 	void *sc_ih;			/* interrupt cookie */
 	callout_t sc_tick_ch;		/* tick callout */
 	int sc_ee_addrbits;		/* EEPROM address bits */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	/*
 	 * Software state for the transmit and receive descriptors.
 	 */
 	int sc_txnum;			/* must be a power of two */
 	struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
 	struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
 	/*
 	 * Control data structures.
 	 */
 	int sc_ntxdesc;			/* must be a power of two */
 	struct wm_control_data_82544 *sc_control_data;
 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
 	bus_dma_segment_t sc_cd_seg;	/* control data segment */
 	int sc_cd_rseg;			/* real number of control segment */
 	size_t sc_cd_size;		/* control data size */
 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
 #define	sc_txdescs	sc_control_data->wdc_u.wcdu_txdescs
 #define	sc_nq_txdescs	sc_control_data->wdc_u.wcdu_nq_txdescs
 #define	sc_rxdescs	sc_control_data->wcd_rxdescs
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound (IPv4) */
 	struct evcnt sc_ev_txtso6;	/* TCP seg offload out-bound (IPv6) */
 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
 	struct evcnt sc_ev_tu;		/* Tx underrun */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
 	int	sc_txfree;		/* number of free Tx descriptors */
 	int	sc_txnext;		/* next ready Tx descriptor */
 	int	sc_txsfree;		/* number of free Tx jobs */
 	int	sc_txsnext;		/* next free Tx job */
 	int	sc_txsdirty;		/* dirty Tx jobs */
 	/* These 5 variables are used only on the 82547. */
 	int	sc_txfifo_size;		/* Tx FIFO size */
 	int	sc_txfifo_head;		/* current head of FIFO */
 	uint32_t sc_txfifo_addr;	/* internal address of start of FIFO */
 	int	sc_txfifo_stall;	/* Tx FIFO is stalled */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
 	int	sc_rxdiscard;
 	int	sc_rxlen;
 	struct mbuf *sc_rxhead;
 	struct mbuf *sc_rxtail;
 	struct mbuf **sc_rxtailp;
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_anegticks;		/* autonegotiation ticks */
 	int sc_tbi_ticks;		/* tbi ticks */
 	int sc_tbi_nrxcfg;		/* count of ICR_RXCFG */
 	int sc_tbi_lastnrxcfg;		/* count of ICR_RXCFG (on last tick) */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 };
 #define	WM_RXCHAIN_RESET(sc)						\
 do {									\
 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
 	*(sc)->sc_rxtailp = NULL;					\
 	(sc)->sc_rxlen = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(sc, m)						\
 do {									\
 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
 	(sc)->sc_rxtailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #else
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #endif
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg) \
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE32(sc, reg, data) \
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define ICH8_FLASH_READ16(sc, reg) \
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE16(sc, reg, data) \
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
 #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
 #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDTXSYNC(sc, x, n, ops)					\
 do {									\
 	int __x, __n;							\
+									\
 	__x = (x);							\
 	__n = (n);							\
+									\
 	/* If it will wrap around, sync to the end of the ring. */	\
 	if ((__x + __n) > WM_NTXDESC(sc)) {				\
 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
 		    (WM_NTXDESC(sc) - __x), (ops));			\
 		__n -= (WM_NTXDESC(sc) - __x);				\
 		__x = 0;						\
 	}								\
+									\
 	/* Now sync whatever is left. */				\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
 } while (/*CONSTCOND*/0)
 #define	WM_CDRXSYNC(sc, x, ops)						\
 do {									\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
 } while (/*CONSTCOND*/0)
 #define	WM_INIT_RXDESC(sc, x)						\
 do {									\
 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
 	struct mbuf *__m = __rxs->rxs_mbuf;				\
+									\
 	/*								\
 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
 	 * so that the payload after the Ethernet header is aligned	\
 	 * to a 4-byte boundary.					\
 	 *								\
 	 * XXX BRAINDAMAGE ALERT!					\
 	 * The stupid chip uses the same size for every buffer, which	\
 	 * is set in the Receive Control register.  We are using the 2K	\
 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
 	 * reason, we can't "scoot" packets longer than the standard	\
 	 * Ethernet MTU.  On strict-alignment platforms, if the total	\
 	 * size exceeds (2K - 2) we set align_tweak to 0 and let	\
 	 * the upper layer copy the headers.				\
 	 */								\
 	__m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak;	\
+									\
 	wm_set_dma_addr(&__rxd->wrx_addr,				\
 	    __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
 	__rxd->wrx_len = 0;						\
 	__rxd->wrx_cksum = 0;						\
 	__rxd->wrx_status = 0;						\
 	__rxd->wrx_errors = 0;						\
 	__rxd->wrx_special = 0;						\
 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
+									\
 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
 } while (/*CONSTCOND*/0)
 static void	wm_start(struct ifnet *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_watchdog(struct ifnet *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 static int	wm_init(struct ifnet *);
 static void	wm_stop(struct ifnet *, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_reset(struct wm_softc *);
 static void	wm_rxdrain(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_softc *, int);
 static int	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_validate_eeprom_checksum(struct wm_softc *);
 static int	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_tick(void *);
 static void	wm_set_filter(struct wm_softc *);
 static void	wm_set_vlan(struct wm_softc *);
 static int	wm_intr(void *);
 static void	wm_txintr(struct wm_softc *);
 static void	wm_rxintr(struct wm_softc *);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_tbi_set_linkled(struct wm_softc *);
 static void	wm_tbi_check_link(struct wm_softc *);
 static void	wm_gmii_reset(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static int	wm_gmii_bm_readreg(device_t, int, int);
 static void	wm_gmii_bm_writereg(device_t, int, int, int);
 static int	wm_gmii_hv_readreg(device_t, int, int);
 static void	wm_gmii_hv_writereg(device_t, int, int, int);
 static int	wm_gmii_82580_readreg(device_t, int, int);
 static void	wm_gmii_82580_writereg(device_t, int, int, int);
 static int	wm_sgmii_readreg(device_t, int, int);
 static void	wm_sgmii_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(struct ifnet *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_kmrn_readreg(struct wm_softc *, int);
 static void	wm_kmrn_writereg(struct wm_softc *, int, int);
 static void	wm_set_spiaddrbits(struct wm_softc *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static int	wm_is_onboard_nvm_eeprom(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *);
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *);
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_read_eeprom_ich8(struct wm_softc *, int, int, uint16_t *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t,
 		     uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static void	wm_82547_txfifo_stall(void *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static int	wm_check_reset_block(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 #ifdef WM_WOL
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 #endif
 static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_smbustopci(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 #ifdef WM_WOL
 static void	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 #endif
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_set_eee_i350(struct wm_softc *);
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	int			wmp_flags;
 #define	WMP_F_1000X		0x01
 #define	WMP_F_1000T		0x02
 #define	WMP_F_SERDES		0x04
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
 	  "Intel i82541GI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
 	  "Intel i82541PI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
 	  "Intel i82547EI 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
 	  "Intel i82547GI 1000BASE-T Ethernet",
 	  WM_T_82547_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
 	  "Intel PRO/1000 PT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
 	  "Intel PRO/1000 PF (82571EB)",
 	  WM_T_82571,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
 	  "Intel PRO/1000 PB (82571EB)",
 	  WM_T_82571,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
 	  "Intel PRO/1000 QT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
 	  "Intel PRO/1000 PT Quad Port Server Adapter",
 	  WM_T_82571,		WMP_F_1000T, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
 	  "Intel i82572EI 1000baseX Ethernet",
 	  WM_T_82572,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
 	  WM_T_82572,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
 	  "Intel i82573E",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
 	  "Intel i82573E IAMT",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
 	  "Intel i82573L Gigabit Ethernet",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
 	  "Intel i82583V",
 	  WM_T_82583,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
 	  "i80003 dual 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
 	  "i80003 dual 1000baseX Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
 	  "Intel i80003 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
 	  "Intel i80003 Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
 	  "Intel i82801H (M_AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
 	  "Intel i82801H (AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
 	  "Intel i82801H LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
 	  "Intel i82801H (IFE) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
 	  "Intel i82801H (M) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
 	  "Intel i82801H IFE (GT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
 	  "Intel i82801H IFE (G) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
 	  "82801I (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
 	  "82801I LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
 	  "82801I (G) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
 	  "82801I (GT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
 	  "82801I (C) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
 	  "82801I mobile LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IGP_M_V,
 	  "82801I mobile (V) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
 	  "82801I mobile (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
 	  "82567LM-4 LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_82567V_3,
 	  "82567V-3 LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
 	  "82567LM-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
 	  "82567LF-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
 	  "82567LM-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
 	  "82567LF-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
 	  "82567V-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_V,
 	  "82567V-3? LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_HANKSVILLE,
 	  "HANKSVILLE LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LM,
 	  "PCH LAN (82577LM) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LC,
 	  "PCH LAN (82577LC) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DM,
 	  "PCH LAN (82578DM) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DC,
 	  "PCH LAN (82578DC) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_LM,
 	  "PCH2 LAN (82579LM) Controller",
 	  WM_T_PCH2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_V,
 	  "PCH2 LAN (82579V) Controller",
 	  WM_T_PCH2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_COPPER,
 	  "82575EB dual-1000baseT Ethernet",
 	  WM_T_82575,		WMP_F_1000T },
 #if 0
 	/*
 	 * not sure if WMP_F_1000X or WMP_F_SERDES - we do not have it - so
 	 * disabled for now ...
 	 */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
 	  "82575EB dual-1000baseX Ethernet (SERDES)",
 	  WM_T_82575,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
 	  "82575GB quad-1000baseT Ethernet",
 	  WM_T_82575,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
 	  "82575GB quad-1000baseT Ethernet (PM)",
 	  WM_T_82575,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_COPPER,
 	  "82576 1000BaseT Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_FIBER,
 	  "82576 1000BaseX Ethernet",
 	  WM_T_82576,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES,
 	  "82576 gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
 	  "82576 quad-1000BaseT Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS,
 	  "82576 gigabit Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS_SERDES,
 	  "82576 gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
 	  "82576 quad-gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER,
 	  "82580 1000BaseT Ethernet",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_FIBER,
 	  "82580 1000BaseX Ethernet",
 	  WM_T_82580,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SERDES,
 	  "82580 1000BaseT Ethernet (SERDES)",
 	  WM_T_82580,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SGMII,
 	  "82580 gigabit Ethernet (SGMII)",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
 	  "82580 dual-1000BaseT Ethernet",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_ER,
 	  "82580 1000BaseT Ethernet",
 	  WM_T_82580ER,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_ER_DUAL,
 	  "82580 dual-1000BaseT Ethernet",
 	  WM_T_82580ER,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
 	  "82580 quad-1000BaseX Ethernet",
 	  WM_T_82580,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_COPPER,
 	  "I350 Gigabit Network Connection",
 	  WM_T_I350,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_FIBER,
 	  "I350 Gigabit Fiber Network Connection",
 	  WM_T_I350,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SERDES,
 	  "I350 Gigabit Backplane Connection",
 	  WM_T_I350,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SGMII,
 	  "I350 Gigabit Connection",
 	  WM_T_I350,		WMP_F_1000T },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_T1,
 	  "I210-T1 Ethernet Server Adapter",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
 	  "I210 Ethernet (Copper OEM)",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_IT,
 	  "I210 Ethernet (Copper IT)",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_FIBER,
 	  "I210 Gigabit Ethernet (Fiber)",
 	  WM_T_I210,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
 	  "I210 Gigabit Ethernet (SERDES)",
 	  WM_T_I210,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
 	  "I210 Gigabit Ethernet (SGMII)",
 	  WM_T_I210,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
 	  "I211 Ethernet (COPPER)",
 	  WM_T_I211,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
 	  "I217 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
 	  "I217 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
 	  "I218 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
 	  "I218 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ 0,			0,
 	  NULL,
 ,			0 },
 };
 #ifdef WM_EVENT_COUNTERS
 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
 #endif /* WM_EVENT_COUNTERS */
 #if 0 /* Not currently used */
 static inline uint32_t
 wm_io_read(struct wm_softc *sc, int reg)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
+}
 #endif
 @@ -2824,2001 +2824,2001 @@ wm_start(struct ifnet *ifp)
+	}
+}
 /*
  * wm_nq_tx_offload:
+ *
  *	Set up TCP/IP checksumming parameters for the
  *	specified packet, for NEWQUEUE devices
  */
 static int
 wm_nq_tx_offload(struct wm_softc *sc, struct wm_txsoft *txs,
     uint32_t *cmdlenp, uint32_t *fieldsp, bool *do_csum)
+{
 	struct mbuf *m0 = txs->txs_mbuf;
 	struct m_tag *mtag;
 	uint32_t vl_len, mssidx, cmdc;
 	struct ether_header *eh;
 	int offset, iphl;
 	/*
 	 * XXX It would be nice if the mbuf pkthdr had offset
 	 * fields for the protocol headers.
 	 */
 	*cmdlenp = 0;
 	*fieldsp = 0;
 	eh = mtod(m0, struct ether_header *);
 	switch (htons(eh->ether_type)) {
 	case ETHERTYPE_IP:
 	case ETHERTYPE_IPV6:
 		offset = ETHER_HDR_LEN;
 		break;
 	case ETHERTYPE_VLAN:
 		offset = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		break;
 	default:
 		/*
 		 * Don't support this protocol or encapsulation.
 		 */
 		*do_csum = false;
 		return 0;
+	}
 	*do_csum = true;
 	*cmdlenp = NQTX_DTYP_D | NQTX_CMD_DEXT | NQTX_CMD_IFCS;
 	cmdc = NQTX_DTYP_C | NQTX_CMD_DEXT;
 	vl_len = (offset << NQTXC_VLLEN_MACLEN_SHIFT);
 	KASSERT((offset & ~NQTXC_VLLEN_MACLEN_MASK) == 0);
 	if ((m0->m_pkthdr.csum_flags &
 	    (M_CSUM_TSOv4|M_CSUM_UDPv4|M_CSUM_TCPv4|M_CSUM_IPv4)) != 0) {
 		iphl = M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
 	} else {
 		iphl = M_CSUM_DATA_IPv6_HL(m0->m_pkthdr.csum_data);
+	}
 	vl_len |= (iphl << NQTXC_VLLEN_IPLEN_SHIFT);
 	KASSERT((iphl & ~NQTXC_VLLEN_IPLEN_MASK) == 0);
 	if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) != NULL) {
 		vl_len |= ((VLAN_TAG_VALUE(mtag) & NQTXC_VLLEN_VLAN_MASK)
 		     << NQTXC_VLLEN_VLAN_SHIFT);
 		*cmdlenp |= NQTX_CMD_VLE;
+	}
 	mssidx = 0;
 	if ((m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4 | M_CSUM_TSOv6)) != 0) {
 		int hlen = offset + iphl;
 		int tcp_hlen;
 		bool v4 = (m0->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0;
 		if (__predict_false(m0->m_len <
 				    (hlen + sizeof(struct tcphdr)))) {
 			/*
 			 * TCP/IP headers are not in the first mbuf; we need
 			 * to do this the slow and painful way.  Let's just
 			 * hope this doesn't happen very often.
 			 */
 			struct tcphdr th;
 			WM_EVCNT_INCR(&sc->sc_ev_txtsopain);
 			m_copydata(m0, hlen, sizeof(th), &th);
 			if (v4) {
 				struct ip ip;
 				m_copydata(m0, offset, sizeof(ip), &ip);
 				ip.ip_len = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip, ip_len),
 				    sizeof(ip.ip_len), &ip.ip_len);
 				th.th_sum = in_cksum_phdr(ip.ip_src.s_addr,
 				    ip.ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr ip6;
 				m_copydata(m0, offset, sizeof(ip6), &ip6);
 				ip6.ip6_plen = 0;
 				m_copyback(m0,
 				    offset + offsetof(struct ip6_hdr, ip6_plen),
 				    sizeof(ip6.ip6_plen), &ip6.ip6_plen);
 				th.th_sum = in6_cksum_phdr(&ip6.ip6_src,
 				    &ip6.ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			m_copyback(m0, hlen + offsetof(struct tcphdr, th_sum),
 			    sizeof(th.th_sum), &th.th_sum);
 			tcp_hlen = th.th_off << 2;
 		} else {
 			/*
 			 * TCP/IP headers are in the first mbuf; we can do
 			 * this the easy way.
 			 */
 			struct tcphdr *th;
 			if (v4) {
 				struct ip *ip =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip->ip_len = 0;
 				th->th_sum = in_cksum_phdr(ip->ip_src.s_addr,
 				    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 			} else {
 				struct ip6_hdr *ip6 =
 				    (void *)(mtod(m0, char *) + offset);
 				th = (void *)(mtod(m0, char *) + hlen);
 				ip6->ip6_plen = 0;
 				th->th_sum = in6_cksum_phdr(&ip6->ip6_src,
 				    &ip6->ip6_dst, 0, htonl(IPPROTO_TCP));
+			}
 			tcp_hlen = th->th_off << 2;
+		}
 		hlen += tcp_hlen;
 		*cmdlenp |= NQTX_CMD_TSE;
 		if (v4) {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso);
 			*fieldsp |= NQTXD_FIELDS_IXSM | NQTXD_FIELDS_TUXSM;
 		} else {
 			WM_EVCNT_INCR(&sc->sc_ev_txtso6);
 			*fieldsp |= NQTXD_FIELDS_TUXSM;
+		}
 		*fieldsp |= ((m0->m_pkthdr.len - hlen) << NQTXD_FIELDS_PAYLEN_SHIFT);
 		KASSERT(((m0->m_pkthdr.len - hlen) & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
 		mssidx |= (m0->m_pkthdr.segsz << NQTXC_MSSIDX_MSS_SHIFT);
 		KASSERT((m0->m_pkthdr.segsz & ~NQTXC_MSSIDX_MSS_MASK) == 0);
 		mssidx |= (tcp_hlen << NQTXC_MSSIDX_L4LEN_SHIFT);
 		KASSERT((tcp_hlen & ~NQTXC_MSSIDX_L4LEN_MASK) == 0);
 	} else {
 		*fieldsp |= (m0->m_pkthdr.len << NQTXD_FIELDS_PAYLEN_SHIFT);
 		KASSERT((m0->m_pkthdr.len & ~NQTXD_FIELDS_PAYLEN_MASK) == 0);
+	}
 	if (m0->m_pkthdr.csum_flags & M_CSUM_IPv4) {
 		*fieldsp |= NQTXD_FIELDS_IXSM;
 		cmdc |= NQTXC_CMD_IP4;
+	}
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_UDPv4 | M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
 		WM_EVCNT_INCR(&sc->sc_ev_txtusum);
 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_TSOv4)) {
 			cmdc |= NQTXC_CMD_TCP;
 		} else {
 			cmdc |= NQTXC_CMD_UDP;
+		}
 		cmdc |= NQTXC_CMD_IP4;
 		*fieldsp |= NQTXD_FIELDS_TUXSM;
+	}
 	if (m0->m_pkthdr.csum_flags &
 	    (M_CSUM_UDPv6 | M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
 		WM_EVCNT_INCR(&sc->sc_ev_txtusum6);
 		if (m0->m_pkthdr.csum_flags & (M_CSUM_TCPv6 | M_CSUM_TSOv6)) {
 			cmdc |= NQTXC_CMD_TCP;
 		} else {
 			cmdc |= NQTXC_CMD_UDP;
+		}
 		cmdc |= NQTXC_CMD_IP6;
 		*fieldsp |= NQTXD_FIELDS_TUXSM;
+	}
 	/* Fill in the context descriptor. */
 	sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_vl_len =
 	    htole32(vl_len);
 	sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_sn = 0;
 	sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_cmd =
 	    htole32(cmdc);
 	sc->sc_nq_txdescs[sc->sc_txnext].nqrx_ctx.nqtxc_mssidx =
 	    htole32(mssidx);
 	WM_CDTXSYNC(sc, sc->sc_txnext, 1, BUS_DMASYNC_PREWRITE);
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: TX: context desc %d 0x%08x%08x\n", device_xname(sc->sc_dev),
 	    sc->sc_txnext, 0, vl_len));
 	DPRINTF(WM_DEBUG_TX, ("\t0x%08x%08x\n", mssidx, cmdc));
 	sc->sc_txnext = WM_NEXTTX(sc, sc->sc_txnext);
 	txs->txs_ndesc++;
 	return 0;
+}
 /*
  * wm_nq_start:		[ifnet interface function]
+ *
  *	Start packet transmission on the interface for NEWQUEUE devices
  */
 static void
 wm_nq_start(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct mbuf *m0;
 	struct m_tag *mtag;
 	struct wm_txsoft *txs;
 	bus_dmamap_t dmamap;
 	int error, nexttx, lasttx = -1, seg, segs_needed;
 	bool do_csum, sent;
 	if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
 		return;
 	sent = false;
 	/*
 	 * Loop through the send queue, setting up transmit descriptors
 	 * until we drain the queue, or use up all available transmit
 	 * descriptors.
 	 */
 	for (;;) {
 		/* Grab a packet off the queue. */
 		IFQ_POLL(&ifp->if_snd, m0);
 		if (m0 == NULL)
 			break;
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: have packet to transmit: %p\n",
 		    device_xname(sc->sc_dev), m0));
 		/* Get a work queue entry. */
 		if (sc->sc_txsfree < WM_TXQUEUE_GC(sc)) {
 			wm_txintr(sc);
 			if (sc->sc_txsfree == 0) {
 				DPRINTF(WM_DEBUG_TX,
 				    ("%s: TX: no free job descriptors\n",
 					device_xname(sc->sc_dev)));
 				WM_EVCNT_INCR(&sc->sc_ev_txsstall);
 				break;
+			}
+		}
 		txs = &sc->sc_txsoft[sc->sc_txsnext];
 		dmamap = txs->txs_dmamap;
 		/*
 		 * Load the DMA map.  If this fails, the packet either
 		 * didn't fit in the allotted number of segments, or we
 		 * were short on resources.  For the too-many-segments
 		 * case, we simply report an error and drop the packet,
 		 * since we can't sanely copy a jumbo packet to a single
 		 * buffer.
 		 */
 		error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
 		    BUS_DMA_WRITE|BUS_DMA_NOWAIT);
 		if (error) {
 			if (error == EFBIG) {
 				WM_EVCNT_INCR(&sc->sc_ev_txdrop);
 				log(LOG_ERR, "%s: Tx packet consumes too many "
 				    "DMA segments, dropping...\n",
 				    device_xname(sc->sc_dev));
 				IFQ_DEQUEUE(&ifp->if_snd, m0);
 				wm_dump_mbuf_chain(sc, m0);
 				m_freem(m0);
 				continue;
+			}
 			/*
 			 * Short on resources, just stop for now.
 			 */
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: dmamap load failed: %d\n",
 			    device_xname(sc->sc_dev), error));
 			break;
+		}
 		segs_needed = dmamap->dm_nsegs;
 		/*
 		 * Ensure we have enough descriptors free to describe
 		 * the packet.  Note, we always reserve one descriptor
 		 * at the end of the ring due to the semantics of the
 		 * TDT register, plus one more in the event we need
 		 * to load offload context.
 		 */
 		if (segs_needed > sc->sc_txfree - 2) {
 			/*
 			 * Not enough free descriptors to transmit this
 			 * packet.  We haven't committed anything yet,
 			 * so just unload the DMA map, put the packet
 			 * pack on the queue, and punt.  Notify the upper
 			 * layer that there are no more slots left.
 			 */
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: need %d (%d) descriptors, have %d\n",
 			    device_xname(sc->sc_dev), dmamap->dm_nsegs,
 			    segs_needed, sc->sc_txfree - 1));
 			ifp->if_flags |= IFF_OACTIVE;
 			bus_dmamap_unload(sc->sc_dmat, dmamap);
 			WM_EVCNT_INCR(&sc->sc_ev_txdstall);
 			break;
+		}
 		IFQ_DEQUEUE(&ifp->if_snd, m0);
 		/*
 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
 		 */
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: packet has %d (%d) DMA segments\n",
 		    device_xname(sc->sc_dev), dmamap->dm_nsegs, segs_needed));
 		WM_EVCNT_INCR(&sc->sc_ev_txseg[dmamap->dm_nsegs - 1]);
 		/*
 		 * Store a pointer to the packet so that we can free it
 		 * later.
+		 *
 		 * Initially, we consider the number of descriptors the
 		 * packet uses the number of DMA segments.  This may be
 		 * incremented by 1 if we do checksum offload (a descriptor
 		 * is used to set the checksum context).
 		 */
 		txs->txs_mbuf = m0;
 		txs->txs_firstdesc = sc->sc_txnext;
 		txs->txs_ndesc = segs_needed;
 		/* Set up offload parameters for this packet. */
 		uint32_t cmdlen, fields, dcmdlen;
 		if (m0->m_pkthdr.csum_flags &
 		    (M_CSUM_TSOv4|M_CSUM_TSOv6|
 		    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
 		    M_CSUM_TCPv6|M_CSUM_UDPv6)) {
 			if (wm_nq_tx_offload(sc, txs, &cmdlen, &fields,
 			    &do_csum) != 0) {
 				/* Error message already displayed. */
 				bus_dmamap_unload(sc->sc_dmat, dmamap);
 				continue;
+			}
 		} else {
 			do_csum = false;
 			cmdlen = 0;
 			fields = 0;
+		}
 		/* Sync the DMA map. */
 		bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
 		    BUS_DMASYNC_PREWRITE);
 		/*
 		 * Initialize the first transmit descriptor.
 		 */
 		nexttx = sc->sc_txnext;
 		if (!do_csum) {
 			/* setup a legacy descriptor */
 			wm_set_dma_addr(
 			    &sc->sc_txdescs[nexttx].wtx_addr,
 			    dmamap->dm_segs[0].ds_addr);
 			sc->sc_txdescs[nexttx].wtx_cmdlen =
 			    htole32(WTX_CMD_IFCS | dmamap->dm_segs[0].ds_len);
 			sc->sc_txdescs[nexttx].wtx_fields.wtxu_status = 0;
 			sc->sc_txdescs[nexttx].wtx_fields.wtxu_options = 0;
 			if ((mtag = VLAN_OUTPUT_TAG(&sc->sc_ethercom, m0)) !=
 			    NULL) {
 				sc->sc_txdescs[nexttx].wtx_cmdlen |=
 				    htole32(WTX_CMD_VLE);
 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan =
 				    htole16(VLAN_TAG_VALUE(mtag) & 0xffff);
 			} else {
 				sc->sc_txdescs[nexttx].wtx_fields.wtxu_vlan = 0;
+			}
 			dcmdlen = 0;
 		} else {
 			/* setup an advanced data descriptor */
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_addr =
 			    htole64(dmamap->dm_segs[0].ds_addr);
 			KASSERT((dmamap->dm_segs[0].ds_len & cmdlen) == 0);
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_cmdlen =
 			    htole32(dmamap->dm_segs[0].ds_len | cmdlen );
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_fields =
 			    htole32(fields);
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: adv data desc %d 0x%" PRIx64 "\n",
 			    device_xname(sc->sc_dev), nexttx,
 			    (uint64_t)dmamap->dm_segs[0].ds_addr));
 			DPRINTF(WM_DEBUG_TX,
 			    ("\t 0x%08x%08x\n", fields,
 			    (uint32_t)dmamap->dm_segs[0].ds_len | cmdlen));
 			dcmdlen = NQTX_DTYP_D | NQTX_CMD_DEXT;
+		}
 		lasttx = nexttx;
 		nexttx = WM_NEXTTX(sc, nexttx);
 		/*
 		 * fill in the next descriptors. legacy or adcanced format
 		 * is the same here
 		 */
 		for (seg = 1; seg < dmamap->dm_nsegs;
 		    seg++, nexttx = WM_NEXTTX(sc, nexttx)) {
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_addr =
 			    htole64(dmamap->dm_segs[seg].ds_addr);
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_cmdlen =
 			    htole32(dcmdlen | dmamap->dm_segs[seg].ds_len);
 			KASSERT((dcmdlen & dmamap->dm_segs[seg].ds_len) == 0);
 			sc->sc_nq_txdescs[nexttx].nqtx_data.nqtxd_fields = 0;
 			lasttx = nexttx;
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: desc %d: %#" PRIx64 ", "
 			     "len %#04zx\n",
 			    device_xname(sc->sc_dev), nexttx,
 			    (uint64_t)dmamap->dm_segs[seg].ds_addr,
 			    dmamap->dm_segs[seg].ds_len));
+		}
 		KASSERT(lasttx != -1);
 		/*
 		 * Set up the command byte on the last descriptor of
 		 * the packet.  If we're in the interrupt delay window,
 		 * delay the interrupt.
 		 */
 		KASSERT((WTX_CMD_EOP | WTX_CMD_RS) ==
 		    (NQTX_CMD_EOP | NQTX_CMD_RS));
 		sc->sc_txdescs[lasttx].wtx_cmdlen |=
 		    htole32(WTX_CMD_EOP | WTX_CMD_RS);
 		txs->txs_lastdesc = lasttx;
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: desc %d: cmdlen 0x%08x\n",
 		    device_xname(sc->sc_dev),
 		    lasttx, le32toh(sc->sc_txdescs[lasttx].wtx_cmdlen)));
 		/* Sync the descriptors we're using. */
 		WM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndesc,
 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 		/* Give the packet to the chip. */
 		CSR_WRITE(sc, sc->sc_tdt_reg, nexttx);
 		sent = true;
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: TDT -> %d\n", device_xname(sc->sc_dev), nexttx));
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: finished transmitting packet, job %d\n",
 		    device_xname(sc->sc_dev), sc->sc_txsnext));
 		/* Advance the tx pointer. */
 		sc->sc_txfree -= txs->txs_ndesc;
 		sc->sc_txnext = nexttx;
 		sc->sc_txsfree--;
 		sc->sc_txsnext = WM_NEXTTXS(sc, sc->sc_txsnext);
 		/* Pass the packet to any BPF listeners. */
 		bpf_mtap(ifp, m0);
+	}
 	if (sc->sc_txsfree == 0 || sc->sc_txfree <= 2) {
 		/* No more slots; notify upper layer. */
 		ifp->if_flags |= IFF_OACTIVE;
+	}
 	if (sent) {
 		/* Set a watchdog timer in case the chip flakes out. */
 		ifp->if_timer = 5;
+	}
+}
 /*
  * wm_watchdog:		[ifnet interface function]
+ *
  *	Watchdog timer handler.
  */
 static void
 wm_watchdog(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	/*
 	 * Since we're using delayed interrupts, sweep up
 	 * before we report an error.
 	 */
 	wm_txintr(sc);
 	if (sc->sc_txfree != WM_NTXDESC(sc)) {
 #ifdef WM_DEBUG
 		int i, j;
 		struct wm_txsoft *txs;
 #endif
 		log(LOG_ERR,
 		    "%s: device timeout (txfree %d txsfree %d txnext %d)\n",
 		    device_xname(sc->sc_dev), sc->sc_txfree, sc->sc_txsfree,
 		    sc->sc_txnext);
 		ifp->if_oerrors++;
 #ifdef WM_DEBUG
 		for (i = sc->sc_txsdirty; i != sc->sc_txsnext ;
 		    i = WM_NEXTTXS(sc, i)) {
 		    txs = &sc->sc_txsoft[i];
 		    printf("txs %d tx %d -> %d\n",
 			i, txs->txs_firstdesc, txs->txs_lastdesc);
 		    for (j = txs->txs_firstdesc; ;
 			j = WM_NEXTTX(sc, j)) {
 			printf("\tdesc %d: 0x%" PRIx64 "\n", j,
 			    sc->sc_nq_txdescs[j].nqtx_data.nqtxd_addr);
 			printf("\t %#08x%08x\n",
 			    sc->sc_nq_txdescs[j].nqtx_data.nqtxd_fields,
 			    sc->sc_nq_txdescs[j].nqtx_data.nqtxd_cmdlen);
 			if (j == txs->txs_lastdesc)
 				break;
+			}
+		}
 #endif
 		/* Reset the interface. */
 		(void) wm_init(ifp);
+	}
 	/* Try to get more packets going. */
 	ifp->if_start(ifp);
+}
 static int
 wm_ifflags_cb(struct ethercom *ec)
+{
 	struct ifnet *ifp = &ec->ec_if;
 	struct wm_softc *sc = ifp->if_softc;
 	int change = ifp->if_flags ^ sc->sc_if_flags;
 	if (change != 0)
 		sc->sc_if_flags = ifp->if_flags;
 	if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0)
 		return ENETRESET;
 	if ((change & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
 		wm_set_filter(sc);
 	wm_set_vlan(sc);
 	return 0;
+}
 /*
  * wm_ioctl:		[ifnet interface function]
+ *
  *	Handle control requests from the operator.
  */
 static int
 wm_ioctl(struct ifnet *ifp, u_long cmd, void *data)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifreq *ifr = (struct ifreq *) data;
 	struct ifaddr *ifa = (struct ifaddr *)data;
 	struct sockaddr_dl *sdl;
 	int s, error;
 	s = splnet();
 	switch (cmd) {
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 		/* Flow control requires full-duplex mode. */
 		if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
 		    (ifr->ifr_media & IFM_FDX) == 0)
 			ifr->ifr_media &= ~IFM_ETH_FMASK;
 		if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
 			if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
 				/* We can do both TXPAUSE and RXPAUSE. */
 				ifr->ifr_media |=
 				    IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
+			}
 			sc->sc_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
+		}
 		error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
 		break;
 	case SIOCINITIFADDR:
 		if (ifa->ifa_addr->sa_family == AF_LINK) {
 			sdl = satosdl(ifp->if_dl->ifa_addr);
 			(void)sockaddr_dl_setaddr(sdl, sdl->sdl_len,
 			    LLADDR(satosdl(ifa->ifa_addr)), ifp->if_addrlen);
 			/* unicast address is first multicast entry */
 			wm_set_filter(sc);
 			error = 0;
 			break;
+		}
 		/*FALLTHROUGH*/
 	default:
 		if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
 			break;
 		error = 0;
 		if (cmd == SIOCSIFCAP)
 			error = (*ifp->if_init)(ifp);
 		else if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
+			;
 		else if (ifp->if_flags & IFF_RUNNING) {
 			/*
 			 * Multicast list has changed; set the hardware filter
 			 * accordingly.
 			 */
 			wm_set_filter(sc);
+		}
 		break;
+	}
 	/* Try to get more packets going. */
 	ifp->if_start(ifp);
 	splx(s);
 	return error;
+}
 /*
  * wm_intr:
+ *
  *	Interrupt service routine.
  */
 static int
 wm_intr(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	uint32_t icr;
 	int handled = 0;
 	while (1 /* CONSTCOND */) {
 		icr = CSR_READ(sc, WMREG_ICR);
 		if ((icr & sc->sc_icr) == 0)
 			break;
 		rnd_add_uint32(&sc->rnd_source, icr);
 		handled = 1;
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 		if (icr & (ICR_RXDMT0|ICR_RXT0)) {
 			DPRINTF(WM_DEBUG_RX,
 			    ("%s: RX: got Rx intr 0x%08x\n",
 			    device_xname(sc->sc_dev),
 			    icr & (ICR_RXDMT0|ICR_RXT0)));
 			WM_EVCNT_INCR(&sc->sc_ev_rxintr);
+		}
 #endif
 		wm_rxintr(sc);
 #if defined(WM_DEBUG) || defined(WM_EVENT_COUNTERS)
 		if (icr & ICR_TXDW) {
 			DPRINTF(WM_DEBUG_TX,
 			    ("%s: TX: got TXDW interrupt\n",
 			    device_xname(sc->sc_dev)));
 			WM_EVCNT_INCR(&sc->sc_ev_txdw);
+		}
 #endif
 		wm_txintr(sc);
 		if (icr & (ICR_LSC|ICR_RXSEQ|ICR_RXCFG)) {
 			WM_EVCNT_INCR(&sc->sc_ev_linkintr);
 			wm_linkintr(sc, icr);
+		}
 		if (icr & ICR_RXO) {
 #if defined(WM_DEBUG)
 			log(LOG_WARNING, "%s: Receive overrun\n",
 			    device_xname(sc->sc_dev));
 #endif /* defined(WM_DEBUG) */
+		}
+	}
 	if (handled) {
 		/* Try to get more packets going. */
 		ifp->if_start(ifp);
+	}
 	return handled;
+}
 /*
  * wm_txintr:
+ *
  *	Helper; handle transmit interrupts.
  */
 static void
 wm_txintr(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_txsoft *txs;
 	uint8_t status;
 	int i;
 	ifp->if_flags &= ~IFF_OACTIVE;
 	/*
 	 * Go through the Tx list and free mbufs for those
 	 * frames which have been transmitted.
 	 */
 	for (i = sc->sc_txsdirty; sc->sc_txsfree != WM_TXQUEUELEN(sc);
 	     i = WM_NEXTTXS(sc, i), sc->sc_txsfree++) {
 		txs = &sc->sc_txsoft[i];
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: checking job %d\n", device_xname(sc->sc_dev), i));
 		WM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndesc,
 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		status =
 		    sc->sc_txdescs[txs->txs_lastdesc].wtx_fields.wtxu_status;
 		if ((status & WTX_ST_DD) == 0) {
 			WM_CDTXSYNC(sc, txs->txs_lastdesc, 1,
 			    BUS_DMASYNC_PREREAD);
 			break;
+		}
 		DPRINTF(WM_DEBUG_TX,
 		    ("%s: TX: job %d done: descs %d..%d\n",
 		    device_xname(sc->sc_dev), i, txs->txs_firstdesc,
 		    txs->txs_lastdesc));
 		/*
 		 * XXX We should probably be using the statistics
 		 * XXX registers, but I don't know if they exist
 		 * XXX on chips before the i82544.
 		 */
 #ifdef WM_EVENT_COUNTERS
 		if (status & WTX_ST_TU)
 			WM_EVCNT_INCR(&sc->sc_ev_tu);
 #endif /* WM_EVENT_COUNTERS */
 		if (status & (WTX_ST_EC|WTX_ST_LC)) {
 			ifp->if_oerrors++;
 			if (status & WTX_ST_LC)
 				log(LOG_WARNING, "%s: late collision\n",
 				    device_xname(sc->sc_dev));
 			else if (status & WTX_ST_EC) {
 				ifp->if_collisions += 16;
 				log(LOG_WARNING, "%s: excessive collisions\n",
 				    device_xname(sc->sc_dev));
+			}
 		} else
 			ifp->if_opackets++;
 		sc->sc_txfree += txs->txs_ndesc;
 		bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
 , txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
 		bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
 		m_freem(txs->txs_mbuf);
 		txs->txs_mbuf = NULL;
+	}
 	/* Update the dirty transmit buffer pointer. */
 	sc->sc_txsdirty = i;
 	DPRINTF(WM_DEBUG_TX,
 	    ("%s: TX: txsdirty -> %d\n", device_xname(sc->sc_dev), i));
 	/*
 	 * If there are no more pending transmissions, cancel the watchdog
 	 * timer.
 	 */
 	if (sc->sc_txsfree == WM_TXQUEUELEN(sc))
 		ifp->if_timer = 0;
+}
 /*
  * wm_rxintr:
+ *
  *	Helper; handle receive interrupts.
  */
 static void
 wm_rxintr(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct wm_rxsoft *rxs;
 	struct mbuf *m;
 	int i, len;
 	uint8_t status, errors;
 	uint16_t vlantag;
 	for (i = sc->sc_rxptr;; i = WM_NEXTRX(i)) {
 		rxs = &sc->sc_rxsoft[i];
 		DPRINTF(WM_DEBUG_RX,
 		    ("%s: RX: checking descriptor %d\n",
 		    device_xname(sc->sc_dev), i));
 		WM_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 		status = sc->sc_rxdescs[i].wrx_status;
 		errors = sc->sc_rxdescs[i].wrx_errors;
 		len = le16toh(sc->sc_rxdescs[i].wrx_len);
 		vlantag = sc->sc_rxdescs[i].wrx_special;
 		if ((status & WRX_ST_DD) == 0) {
 			/*
 			 * We have processed all of the receive descriptors.
 			 */
 			WM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
 			break;
+		}
 		if (__predict_false(sc->sc_rxdiscard)) {
 			DPRINTF(WM_DEBUG_RX,
 			    ("%s: RX: discarding contents of descriptor %d\n",
 			    device_xname(sc->sc_dev), i));
 			WM_INIT_RXDESC(sc, i);
 			if (status & WRX_ST_EOP) {
 				/* Reset our state. */
 				DPRINTF(WM_DEBUG_RX,
 				    ("%s: RX: resetting rxdiscard -> 0\n",
 				    device_xname(sc->sc_dev)));
 				sc->sc_rxdiscard = 0;
+			}
 			continue;
+		}
 		bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
 		m = rxs->rxs_mbuf;
 		/*
 		 * Add a new receive buffer to the ring, unless of
 		 * course the length is zero. Treat the latter as a
 		 * failed mapping.
 		 */
 		if ((len == 0) || (wm_add_rxbuf(sc, i) != 0)) {
 			/*
 			 * Failed, throw away what we've done so
 			 * far, and discard the rest of the packet.
 			 */
 			ifp->if_ierrors++;
 			bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 			WM_INIT_RXDESC(sc, i);
 			if ((status & WRX_ST_EOP) == 0)
 				sc->sc_rxdiscard = 1;
 			if (sc->sc_rxhead != NULL)
 				m_freem(sc->sc_rxhead);
 			WM_RXCHAIN_RESET(sc);
 			DPRINTF(WM_DEBUG_RX,
 			    ("%s: RX: Rx buffer allocation failed, "
 			    "dropping packet%s\n", device_xname(sc->sc_dev),
 			    sc->sc_rxdiscard ? " (discard)" : ""));
 			continue;
+		}
 		m->m_len = len;
 		sc->sc_rxlen += len;
 		DPRINTF(WM_DEBUG_RX,
 		    ("%s: RX: buffer at %p len %d\n",
 		    device_xname(sc->sc_dev), m->m_data, len));
 		/*
 		 * If this is not the end of the packet, keep
 		 * looking.
 		 */
 		if ((status & WRX_ST_EOP) == 0) {
 			WM_RXCHAIN_LINK(sc, m);
 			DPRINTF(WM_DEBUG_RX,
 			    ("%s: RX: not yet EOP, rxlen -> %d\n",
 			    device_xname(sc->sc_dev), sc->sc_rxlen));
 			continue;
+		}
 		/*
 		 * Okay, we have the entire packet now.  The chip is
 		 * configured to include the FCS except I350 and I21[01]
 		 * (not all chips can be configured to strip it),
 		 * so we need to trim it.
 		 * May need to adjust length of previous mbuf in the
 		 * chain if the current mbuf is too short.
 		 * For an eratta, the RCTL_SECRC bit in RCTL register
 		 * is always set in I350, so we don't trim it.
 		 */
 		if ((sc->sc_type != WM_T_I350) && (sc->sc_type != WM_T_I210)
 		    && (sc->sc_type != WM_T_I211)) {
 			if (m->m_len < ETHER_CRC_LEN) {
 				sc->sc_rxtail->m_len
 				    -= (ETHER_CRC_LEN - m->m_len);
 				m->m_len = 0;
 			} else
 				m->m_len -= ETHER_CRC_LEN;
 			len = sc->sc_rxlen - ETHER_CRC_LEN;
 		} else
 			len = sc->sc_rxlen;
 		WM_RXCHAIN_LINK(sc, m);
 		*sc->sc_rxtailp = NULL;
 		m = sc->sc_rxhead;
 		WM_RXCHAIN_RESET(sc);
 		DPRINTF(WM_DEBUG_RX,
 		    ("%s: RX: have entire packet, len -> %d\n",
 		    device_xname(sc->sc_dev), len));
 		/*
 		 * If an error occurred, update stats and drop the packet.
 		 */
 		if (errors &
 		     (WRX_ER_CE|WRX_ER_SE|WRX_ER_SEQ|WRX_ER_CXE|WRX_ER_RXE)) {
 			if (errors & WRX_ER_SE)
 				log(LOG_WARNING, "%s: symbol error\n",
 				    device_xname(sc->sc_dev));
 			else if (errors & WRX_ER_SEQ)
 				log(LOG_WARNING, "%s: receive sequence error\n",
 				    device_xname(sc->sc_dev));
 			else if (errors & WRX_ER_CE)
 				log(LOG_WARNING, "%s: CRC error\n",
 				    device_xname(sc->sc_dev));
 			m_freem(m);
 			continue;
+		}
 		/*
 		 * No errors.  Receive the packet.
 		 */
 		m->m_pkthdr.rcvif = ifp;
 		m->m_pkthdr.len = len;
 		/*
 		 * If VLANs are enabled, VLAN packets have been unwrapped
 		 * for us.  Associate the tag with the packet.
 		 */
 		if ((status & WRX_ST_VP) != 0) {
 			VLAN_INPUT_TAG(ifp, m,
 			    le16toh(vlantag),
 			    continue);
+		}
 		/*
 		 * Set up checksum info for this packet.
 		 */
 		if ((status & WRX_ST_IXSM) == 0) {
 			if (status & WRX_ST_IPCS) {
 				WM_EVCNT_INCR(&sc->sc_ev_rxipsum);
 				m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
 				if (errors & WRX_ER_IPE)
 					m->m_pkthdr.csum_flags |=
 					    M_CSUM_IPv4_BAD;
+			}
 			if (status & WRX_ST_TCPCS) {
 				/*
 				 * Note: we don't know if this was TCP or UDP,
 				 * so we just set both bits, and expect the
 				 * upper layers to deal.
 				 */
 				WM_EVCNT_INCR(&sc->sc_ev_rxtusum);
 				m->m_pkthdr.csum_flags |=
 				    M_CSUM_TCPv4 | M_CSUM_UDPv4 |
 				    M_CSUM_TCPv6 | M_CSUM_UDPv6;
 				if (errors & WRX_ER_TCPE)
 					m->m_pkthdr.csum_flags |=
 					    M_CSUM_TCP_UDP_BAD;
+			}
+		}
 		ifp->if_ipackets++;
 		/* Pass this up to any BPF listeners. */
 		bpf_mtap(ifp, m);
 		/* Pass it on. */
 		(*ifp->if_input)(ifp, m);
+	}
 	/* Update the receive pointer. */
 	sc->sc_rxptr = i;
 	DPRINTF(WM_DEBUG_RX,
 	    ("%s: RX: rxptr -> %d\n", device_xname(sc->sc_dev), i));
+}
 /*
  * wm_linkintr_gmii:
+ *
  *	Helper; handle link interrupts for GMII.
  */
 static void
 wm_linkintr_gmii(struct wm_softc *sc, uint32_t icr)
+{
 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	if (icr & ICR_LSC) {
 		DPRINTF(WM_DEBUG_LINK,
-		    ("%s: LINK: LSC -> mii_tick\n",
+		    ("%s: LINK: LSC -> mii_pollstat\n",
 			device_xname(sc->sc_dev)));
-		mii_tick(&sc->sc_mii);
+		mii_pollstat(&sc->sc_mii);
 		if (sc->sc_type == WM_T_82543) {
 			int miistatus, active;
 			/*
 			 * With 82543, we need to force speed and
 			 * duplex on the MAC equal to what the PHY
 			 * speed and duplex configuration is.
 			 */
 			miistatus = sc->sc_mii.mii_media_status;
 			if (miistatus & IFM_ACTIVE) {
 				active = sc->sc_mii.mii_media_active;
 				sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
 				switch (IFM_SUBTYPE(active)) {
 				case IFM_10_T:
 					sc->sc_ctrl |= CTRL_SPEED_10;
 					break;
 				case IFM_100_TX:
 					sc->sc_ctrl |= CTRL_SPEED_100;
 					break;
 				case IFM_1000_T:
 					sc->sc_ctrl |= CTRL_SPEED_1000;
 					break;
 				default:
 					/*
 					 * fiber?
 					 * Shoud not enter here.
 					 */
 					printf("unknown media (%x)\n",
 					    active);
 					break;
+				}
 				if (active & IFM_FDX)
 					sc->sc_ctrl |= CTRL_FD;
 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+			}
 		} else if ((sc->sc_type == WM_T_ICH8)
 		    && (sc->sc_phytype == WMPHY_IGP_3)) {
 			wm_kmrn_lock_loss_workaround_ich8lan(sc);
 		} else if (sc->sc_type == WM_T_PCH) {
 			wm_k1_gig_workaround_hv(sc,
 			    ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0));
+		}
 		if ((sc->sc_phytype == WMPHY_82578)
 		    && (IFM_SUBTYPE(sc->sc_mii.mii_media_active)
 			== IFM_1000_T)) {
 			if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0) {
 				delay(200*1000); /* XXX too big */
 				/* Link stall fix for link up */
 				wm_gmii_hv_writereg(sc->sc_dev, 1,
 				    HV_MUX_DATA_CTRL,
 				    HV_MUX_DATA_CTRL_GEN_TO_MAC
 				    | HV_MUX_DATA_CTRL_FORCE_SPEED);
 				wm_gmii_hv_writereg(sc->sc_dev, 1,
 				    HV_MUX_DATA_CTRL,
 				    HV_MUX_DATA_CTRL_GEN_TO_MAC);
+			}
+		}
 	} else if (icr & ICR_RXSEQ) {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK Receive sequence error\n",
 			device_xname(sc->sc_dev)));
+	}
+}
 /*
  * wm_linkintr_tbi:
+ *
  *	Helper; handle link interrupts for TBI mode.
  */
 static void
 wm_linkintr_tbi(struct wm_softc *sc, uint32_t icr)
+{
 	uint32_t status;
 	DPRINTF(WM_DEBUG_LINK, ("%s: %s:\n", device_xname(sc->sc_dev),
 		__func__));
 	status = CSR_READ(sc, WMREG_STATUS);
 	if (icr & ICR_LSC) {
 		if (status & STATUS_LU) {
 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> up %s\n",
 			    device_xname(sc->sc_dev),
 			    (status & STATUS_FD) ? "FDX" : "HDX"));
 			/*
 			 * NOTE: CTRL will update TFCE and RFCE automatically,
 			 * so we should update sc->sc_ctrl
 			 */
 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
 			sc->sc_fcrtl &= ~FCRTL_XONE;
 			if (status & STATUS_FD)
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 			else
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
 			if (sc->sc_ctrl & CTRL_TFCE)
 				sc->sc_fcrtl |= FCRTL_XONE;
 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
 				      sc->sc_fcrtl);
 			sc->sc_tbi_linkup = 1;
 		} else {
 			DPRINTF(WM_DEBUG_LINK, ("%s: LINK: LSC -> down\n",
 			    device_xname(sc->sc_dev)));
 			sc->sc_tbi_linkup = 0;
+		}
 		wm_tbi_set_linkled(sc);
 	} else if (icr & ICR_RXCFG) {
 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: receiving /C/\n",
 		    device_xname(sc->sc_dev)));
 		sc->sc_tbi_nrxcfg++;
 		wm_check_for_link(sc);
 	} else if (icr & ICR_RXSEQ) {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK: Receive sequence error\n",
 		    device_xname(sc->sc_dev)));
+	}
+}
 /*
  * wm_linkintr:
+ *
  *	Helper; handle link interrupts.
  */
 static void
 wm_linkintr(struct wm_softc *sc, uint32_t icr)
+{
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_linkintr_gmii(sc, icr);
 	else
 		wm_linkintr_tbi(sc, icr);
+}
 /*
  * wm_tick:
+ *
  *	One second timer, used to check link status, sweep up
  *	completed transmit jobs, etc.
  */
 static void
 wm_tick(void *arg)
+{
 	struct wm_softc *sc = arg;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	int s;
 	s = splnet();
 	if (sc->sc_type >= WM_T_82542_2_1) {
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
 		WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
 		WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
+	}
 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
 	ifp->if_ierrors += 0ULL + /* ensure quad_t */
 	    + CSR_READ(sc, WMREG_CRCERRS)
 	    + CSR_READ(sc, WMREG_ALGNERRC)
 	    + CSR_READ(sc, WMREG_SYMERRC)
 	    + CSR_READ(sc, WMREG_RXERRC)
 	    + CSR_READ(sc, WMREG_SEC)
 	    + CSR_READ(sc, WMREG_CEXTERR)
 	    + CSR_READ(sc, WMREG_RLEC);
 	ifp->if_iqdrops += CSR_READ(sc, WMREG_MPC) + CSR_READ(sc, WMREG_RNBC);
 	if (sc->sc_flags & WM_F_HAS_MII)
 		mii_tick(&sc->sc_mii);
 	else
 		wm_tbi_check_link(sc);
 	splx(s);
 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
+}
 /*
  * wm_reset:
+ *
  *	Reset the i82542 chip.
  */
 static void
 wm_reset(struct wm_softc *sc)
+{
 	int phy_reset = 0;
 	uint32_t reg, mask;
 	int i;
 	/*
 	 * Allocate on-chip memory according to the MTU size.
 	 * The Packet Buffer Allocation register must be written
 	 * before the chip is reset.
 	 */
 	switch (sc->sc_type) {
 	case WM_T_82547:
 	case WM_T_82547_2:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
 		    PBA_22K : PBA_30K;
 		sc->sc_txfifo_head = 0;
 		sc->sc_txfifo_addr = sc->sc_pba << PBA_ADDR_SHIFT;
 		sc->sc_txfifo_size =
 		    (PBA_40K - sc->sc_pba) << PBA_BYTE_SHIFT;
 		sc->sc_txfifo_stall = 0;
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82575:	/* XXX need special handing for jumbo frames */
 	case WM_T_I350:
 	case WM_T_80003:
 		sc->sc_pba = PBA_32K;
 		break;
 	case WM_T_82580:
 	case WM_T_82580ER:
 		sc->sc_pba = PBA_35K;
 		break;
 	case WM_T_I210:
 	case WM_T_I211:
 		sc->sc_pba = PBA_34K;
 		break;
 	case WM_T_82576:
 		sc->sc_pba = PBA_64K;
 		break;
 	case WM_T_82573:
 		sc->sc_pba = PBA_12K;
 		break;
 	case WM_T_82574:
 	case WM_T_82583:
 		sc->sc_pba = PBA_20K;
 		break;
 	case WM_T_ICH8:
 		sc->sc_pba = PBA_8K;
 		CSR_WRITE(sc, WMREG_PBS, PBA_16K);
 		break;
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 		sc->sc_pba = PBA_10K;
 		break;
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		sc->sc_pba = PBA_26K;
 		break;
 	default:
 		sc->sc_pba = sc->sc_ethercom.ec_if.if_mtu > 8192 ?
 		    PBA_40K : PBA_48K;
 		break;
+	}
 	CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
 	/* Prevent the PCI-E bus from sticking */
 	if (sc->sc_flags & WM_F_PCIE) {
 		int timeout = 800;
 		sc->sc_ctrl |= CTRL_GIO_M_DIS;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		while (timeout--) {
 			if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
 			    == 0)
 				break;
 			delay(100);
+		}
+	}
 	/* Set the completion timeout for interface */
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_I350))
 		wm_set_pcie_completion_timeout(sc);
 	/* Clear interrupt */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	/* Stop the transmit and receive processes. */
 	CSR_WRITE(sc, WMREG_RCTL, 0);
 	CSR_WRITE(sc, WMREG_TCTL, TCTL_PSP);
 	sc->sc_rctl &= ~RCTL_EN;
 	/* XXX set_tbi_sbp_82543() */
 	delay(10*1000);
 	/* Must acquire the MDIO ownership before MAC reset */
 	switch (sc->sc_type) {
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		i = 0;
 		reg = CSR_READ(sc, WMREG_EXTCNFCTR)
 		    | EXTCNFCTR_MDIO_SW_OWNERSHIP;
 		do {
 			CSR_WRITE(sc, WMREG_EXTCNFCTR,
 			    reg | EXTCNFCTR_MDIO_SW_OWNERSHIP);
 			reg = CSR_READ(sc, WMREG_EXTCNFCTR);
 			if ((reg & EXTCNFCTR_MDIO_SW_OWNERSHIP) != 0)
 				break;
 			reg |= EXTCNFCTR_MDIO_SW_OWNERSHIP;
 			delay(2*1000);
 			i++;
 		} while (i < WM_MDIO_OWNERSHIP_TIMEOUT);
 		break;
 	default:
 		break;
+	}
 	/*
 	 * 82541 Errata 29? & 82547 Errata 28?
 	 * See also the description about PHY_RST bit in CTRL register
 	 * in 8254x_GBe_SDM.pdf.
 	 */
 	if ((sc->sc_type == WM_T_82541) || (sc->sc_type == WM_T_82547)) {
 		CSR_WRITE(sc, WMREG_CTRL,
 		    CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
 		delay(5000);
+	}
 	switch (sc->sc_type) {
 	case WM_T_82544: /* XXX check whether WM_F_IOH_VALID is set */
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		/*
 		 * On some chipsets, a reset through a memory-mapped write
 		 * cycle can cause the chip to reset before completing the
 		 * write cycle.  This causes major headache that can be
 		 * avoided by issuing the reset via indirect register writes
 		 * through I/O space.
+		 *
 		 * So, if we successfully mapped the I/O BAR at attach time,
 		 * use that.  Otherwise, try our luck with a memory-mapped
 		 * reset.
 		 */
 		if (sc->sc_flags & WM_F_IOH_VALID)
 			wm_io_write(sc, WMREG_CTRL, CTRL_RST);
 		else
 			CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
 		break;
 	case WM_T_82545_3:
 	case WM_T_82546_3:
 		/* Use the shadow control register on these chips. */
 		CSR_WRITE(sc, WMREG_CTRL_SHADOW, CTRL_RST);
 		break;
 	case WM_T_80003:
 		mask = swfwphysem[sc->sc_funcid];
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		wm_get_swfw_semaphore(sc, mask);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		wm_put_swfw_semaphore(sc, mask);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
 		if (wm_check_reset_block(sc) == 0) {
 			/*
 			 * Gate automatic PHY configuration by hardware on
 			 * non-managed 82579
 			 */
 			if ((sc->sc_type == WM_T_PCH2)
 			    && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
 				!= 0))
 				wm_gate_hw_phy_config_ich8lan(sc, 1);
 			reg |= CTRL_PHY_RESET;
 			phy_reset = 1;
+		}
 		wm_get_swfwhw_semaphore(sc);
 		CSR_WRITE(sc, WMREG_CTRL, reg);
 		delay(20*1000);
 		wm_put_swfwhw_semaphore(sc);
 		break;
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82546:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_82583:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	default:
 		/* Everything else can safely use the documented method. */
 		CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
 		break;
+	}
 	if (phy_reset != 0)
 		wm_get_cfg_done(sc);
 	/* reload EEPROM */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 		delay(10);
 		reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		delay(2000);
 		break;
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 		delay(5*1000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 		delay(20000);
 		/* XXX Disable HW ARPs on ASF enabled adapters */
 		break;
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		if (sc->sc_flags & WM_F_EEPROM_FLASH) {
 			delay(10);
 			reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
+		}
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		/*
 		 * Phy configuration from NVM just starts after EECD_AUTO_RD
 		 * is set.
 		 */
 		if ((sc->sc_type == WM_T_82573) || (sc->sc_type == WM_T_82574)
 		    || (sc->sc_type == WM_T_82583))
 			delay(25*1000);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		/* check EECD_EE_AUTORD */
 		wm_get_auto_rd_done(sc);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
+	}
 	/* Check whether EEPROM is present or not */
 	switch (sc->sc_type) {
 	case WM_T_82575:
 	case WM_T_82576:
 #if 0 /* XXX */
 	case WM_T_82580:
 	case WM_T_82580ER:
 #endif
 	case WM_T_I350:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 		if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
 			/* Not found */
 			sc->sc_flags |= WM_F_EEPROM_INVALID;
 			if ((sc->sc_type == WM_T_82575)
 			    || (sc->sc_type == WM_T_82576)
 			    || (sc->sc_type == WM_T_82580)
 			    || (sc->sc_type == WM_T_82580ER)
 			    || (sc->sc_type == WM_T_I350))
 				wm_reset_init_script_82575(sc);
+		}
 		break;
 	default:
 		break;
+	}
 	if ((sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)
 	    || (sc->sc_type == WM_T_I350)) {
 		/* clear global device reset status bit */
 		CSR_WRITE(sc, WMREG_STATUS, STATUS_DEV_RST_SET);
+	}
 	/* Clear any pending interrupt events. */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	reg = CSR_READ(sc, WMREG_ICR);
 	/* reload sc_ctrl */
 	sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 	if (sc->sc_type == WM_T_I350)
 		wm_set_eee_i350(sc);
 	/* dummy read from WUC */
 	if (sc->sc_type == WM_T_PCH)
 		reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC);
 	/*
 	 * For PCH, this write will make sure that any noise will be detected
 	 * as a CRC error and be dropped rather than show up as a bad packet
 	 * to the DMA engine
 	 */
 	if (sc->sc_type == WM_T_PCH)
 		CSR_WRITE(sc, WMREG_CRC_OFFSET, 0x65656565);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		CSR_WRITE(sc, WMREG_WUC, 0);
 	/* XXX need special handling for 82580 */
+}
 static void
 wm_set_vlan(struct wm_softc *sc)
+{
 	/* Deal with VLAN enables. */
 	if (VLAN_ATTACHED(&sc->sc_ethercom))
 		sc->sc_ctrl |= CTRL_VME;
 	else
 		sc->sc_ctrl &= ~CTRL_VME;
 	/* Write the control registers. */
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 /*
  * wm_init:		[ifnet interface function]
+ *
  *	Initialize the interface.  Must be called at splnet().
  */
 static int
 wm_init(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct wm_rxsoft *rxs;
 	int i, j, trynum, error = 0;
 	uint32_t reg;
 	/*
 	 * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
 	 * There is a small but measurable benefit to avoiding the adjusment
 	 * of the descriptor so that the headers are aligned, for normal mtu,
 	 * on such platforms.  One possibility is that the DMA itself is
 	 * slightly more efficient if the front of the entire packet (instead
 	 * of the front of the headers) is aligned.
+	 *
 	 * Note we must always set align_tweak to 0 if we are using
 	 * jumbo frames.
 	 */
 #ifdef __NO_STRICT_ALIGNMENT
 	sc->sc_align_tweak = 0;
 #else
 	if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
 		sc->sc_align_tweak = 0;
 	else
 		sc->sc_align_tweak = 2;
 #endif /* __NO_STRICT_ALIGNMENT */
 	/* Cancel any pending I/O. */
 	wm_stop(ifp, 0);
 	/* update statistics before reset */
 	ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
 	ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
 	/* Reset the chip to a known state. */
 	wm_reset(sc);
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 	case WM_T_80003:
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		if (wm_check_mng_mode(sc) != 0)
 			wm_get_hw_control(sc);
 		break;
 	default:
 		break;
+	}
 	/* Reset the PHY. */
 	if (sc->sc_flags & WM_F_HAS_MII)
 		wm_gmii_reset(sc);
 	reg = CSR_READ(sc, WMREG_CTRL_EXT);
 	/* Enable PHY low-power state when MAC is at D3 w/o WoL */
 	if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2))
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_PHYPDEN);
 	/* Initialize the transmit descriptor ring. */
 	memset(sc->sc_txdescs, 0, WM_TXDESCSIZE(sc));
 	WM_CDTXSYNC(sc, 0, WM_NTXDESC(sc),
 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 	sc->sc_txfree = WM_NTXDESC(sc);
 	sc->sc_txnext = 0;
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_TDBAH, WM_CDTXADDR_HI(sc, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDBAL, WM_CDTXADDR_LO(sc, 0));
 		CSR_WRITE(sc, WMREG_OLD_TDLEN, WM_TXDESCSIZE(sc));
 		CSR_WRITE(sc, WMREG_OLD_TDH, 0);
 		CSR_WRITE(sc, WMREG_OLD_TDT, 0);
 		CSR_WRITE(sc, WMREG_OLD_TIDV, 128);
 	} else {
 		CSR_WRITE(sc, WMREG_TDBAH, WM_CDTXADDR_HI(sc, 0));
 		CSR_WRITE(sc, WMREG_TDBAL, WM_CDTXADDR_LO(sc, 0));
 		CSR_WRITE(sc, WMREG_TDLEN, WM_TXDESCSIZE(sc));
 		CSR_WRITE(sc, WMREG_TDH, 0);
 		CSR_WRITE(sc, WMREG_TIDV, 375);		/* ITR / 4 */
 		CSR_WRITE(sc, WMREG_TADV, 375);		/* should be same */
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			/*
 			 * Don't write TDT before TCTL.EN is set.
 			 * See the document.
 			 */
 			CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_QUEUE_ENABLE
 			    | TXDCTL_PTHRESH(0) | TXDCTL_HTHRESH(0)
 			    | TXDCTL_WTHRESH(0));
 		else {
 			CSR_WRITE(sc, WMREG_TDT, 0);
 			CSR_WRITE(sc, WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
 			    TXDCTL_HTHRESH(0) | TXDCTL_WTHRESH(0));
 			CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_PTHRESH(0) |
 			    RXDCTL_HTHRESH(0) | RXDCTL_WTHRESH(1));
+		}
+	}
 	CSR_WRITE(sc, WMREG_TQSA_LO, 0);
 	CSR_WRITE(sc, WMREG_TQSA_HI, 0);
 	/* Initialize the transmit job descriptors. */
 	for (i = 0; i < WM_TXQUEUELEN(sc); i++)
 		sc->sc_txsoft[i].txs_mbuf = NULL;
 	sc->sc_txsfree = WM_TXQUEUELEN(sc);
 	sc->sc_txsnext = 0;
 	sc->sc_txsdirty = 0;
 	/*
 	 * Initialize the receive descriptor and receive job
 	 * descriptor rings.
 	 */
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_RDBAH0, WM_CDRXADDR_HI(sc, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDBAL0, WM_CDRXADDR_LO(sc, 0));
 		CSR_WRITE(sc, WMREG_OLD_RDLEN0, sizeof(sc->sc_rxdescs));
 		CSR_WRITE(sc, WMREG_OLD_RDH0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT0, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR0, 28 | RDTR_FPD);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_HI, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDBA1_LO, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDLEN1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDH1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDT1, 0);
 		CSR_WRITE(sc, WMREG_OLD_RDTR1, 0);
 	} else {
 		CSR_WRITE(sc, WMREG_RDBAH, WM_CDRXADDR_HI(sc, 0));
 		CSR_WRITE(sc, WMREG_RDBAL, WM_CDRXADDR_LO(sc, 0));
 		CSR_WRITE(sc, WMREG_RDLEN, sizeof(sc->sc_rxdescs));
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 			CSR_WRITE(sc, WMREG_EITR(0), 450);
 			if (MCLBYTES & ((1 << SRRCTL_BSIZEPKT_SHIFT) - 1))
 				panic("%s: MCLBYTES %d unsupported for i2575 or higher\n", __func__, MCLBYTES);
 			CSR_WRITE(sc, WMREG_SRRCTL, SRRCTL_DESCTYPE_LEGACY
 			    | (MCLBYTES >> SRRCTL_BSIZEPKT_SHIFT));
 			CSR_WRITE(sc, WMREG_RXDCTL, RXDCTL_QUEUE_ENABLE
 			    | RXDCTL_PTHRESH(16) | RXDCTL_HTHRESH(8)
 			    | RXDCTL_WTHRESH(1));
 		} else {
 			CSR_WRITE(sc, WMREG_RDH, 0);
 			CSR_WRITE(sc, WMREG_RDT, 0);
 			CSR_WRITE(sc, WMREG_RDTR, 375 | RDTR_FPD); /* ITR/4 */
 			CSR_WRITE(sc, WMREG_RADV, 375);	/* MUST be same */
+		}
+	}
 	for (i = 0; i < WM_NRXDESC; i++) {
 		rxs = &sc->sc_rxsoft[i];
 		if (rxs->rxs_mbuf == NULL) {
 			if ((error = wm_add_rxbuf(sc, i)) != 0) {
 				log(LOG_ERR, "%s: unable to allocate or map "
 				    "rx buffer %d, error = %d\n",
 				    device_xname(sc->sc_dev), i, error);
 				/*
 				 * XXX Should attempt to run with fewer receive
 				 * XXX buffers instead of just failing.
 				 */
 				wm_rxdrain(sc);
 				goto out;
+			}
 		} else {
 			if ((sc->sc_flags & WM_F_NEWQUEUE) == 0)
 				WM_INIT_RXDESC(sc, i);
 			/*
 			 * For 82575 and newer device, the RX descriptors
 			 * must be initialized after the setting of RCTL.EN in
 			 * wm_set_filter()
 			 */
+		}
+	}
 	sc->sc_rxptr = 0;
 	sc->sc_rxdiscard = 0;
 	WM_RXCHAIN_RESET(sc);
 	/*
 	 * Clear out the VLAN table -- we don't use it (yet).
 	 */
 	CSR_WRITE(sc, WMREG_VET, 0);
 	if (sc->sc_type == WM_T_I350)
 		trynum = 10; /* Due to hw errata */
 	else
 		trynum = 1;
 	for (i = 0; i < WM_VLAN_TABSIZE; i++)
 		for (j = 0; j < trynum; j++)
 			CSR_WRITE(sc, WMREG_VFTA + (i << 2), 0);
 	/*
 	 * Set up flow-control parameters.
+	 *
 	 * XXX Values could probably stand some tuning.
 	 */
 	if ((sc->sc_type != WM_T_ICH8) && (sc->sc_type != WM_T_ICH9)
 	    && (sc->sc_type != WM_T_ICH10) && (sc->sc_type != WM_T_PCH)
 	    && (sc->sc_type != WM_T_PCH2)) {
 		CSR_WRITE(sc, WMREG_FCAL, FCAL_CONST);
 		CSR_WRITE(sc, WMREG_FCAH, FCAH_CONST);
 		CSR_WRITE(sc, WMREG_FCT, ETHERTYPE_FLOWCONTROL);
+	}
 	sc->sc_fcrtl = FCRTL_DFLT;
 	if (sc->sc_type < WM_T_82543) {
 		CSR_WRITE(sc, WMREG_OLD_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_OLD_FCRTL, sc->sc_fcrtl);
 	} else {
 		CSR_WRITE(sc, WMREG_FCRTH, FCRTH_DFLT);
 		CSR_WRITE(sc, WMREG_FCRTL, sc->sc_fcrtl);
+	}
 	if (sc->sc_type == WM_T_80003)
 		CSR_WRITE(sc, WMREG_FCTTV, 0xffff);
 	else
 		CSR_WRITE(sc, WMREG_FCTTV, FCTTV_DFLT);
 	/* Writes the control register. */
 	wm_set_vlan(sc);
 	if (sc->sc_flags & WM_F_HAS_MII) {
 		int val;
 		switch (sc->sc_type) {
 		case WM_T_80003:
 		case WM_T_ICH8:
 		case WM_T_ICH9:
 		case WM_T_ICH10:
 		case WM_T_PCH:
 		case WM_T_PCH2:
 		case WM_T_PCH_LPT:
 			/*
 			 * Set the mac to wait the maximum time between each
 			 * iteration and increase the max iterations when
 			 * polling the phy; this fixes erroneous timeouts at
 			 * 10Mbps.
 			 */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_TIMEOUTS,
 xFFFF);
 			val = wm_kmrn_readreg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM);
 			val |= 0x3F;
 			wm_kmrn_writereg(sc,
 			    KUMCTRLSTA_OFFSET_INB_PARAM, val);
 			break;
 		default:
 			break;
+		}
 		if (sc->sc_type == WM_T_80003) {
 			val = CSR_READ(sc, WMREG_CTRL_EXT);
 			val &= ~CTRL_EXT_LINK_MODE_MASK;
 			CSR_WRITE(sc, WMREG_CTRL_EXT, val);
 			/* Bypass RX and TX FIFO's */
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_FIFO_CTRL,
 			    KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
 			    | KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_INB_CTRL,
 			    KUMCTRLSTA_INB_CTRL_DIS_PADDING |
 			    KUMCTRLSTA_INB_CTRL_LINK_TMOUT_DFLT);
+		}
+	}
 #if 0
 	CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext);
 #endif
 	/*
 	 * Set up checksum offload parameters.
 	 */
 	reg = CSR_READ(sc, WMREG_RXCSUM);
 	reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
 	if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
 		reg |= RXCSUM_IPOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
 		reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
 	if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
 		reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
 	CSR_WRITE(sc, WMREG_RXCSUM, reg);
 	/* Reset TBI's RXCFG count */
 	sc->sc_tbi_nrxcfg = sc->sc_tbi_lastnrxcfg = 0;
 	/*
 	 * Set up the interrupt registers.
 	 */
 	CSR_WRITE(sc, WMREG_IMC, 0xffffffffU);
 	sc->sc_icr = ICR_TXDW | ICR_LSC | ICR_RXSEQ | ICR_RXDMT0 |
 	    ICR_RXO | ICR_RXT0;
 	if ((sc->sc_flags & WM_F_HAS_MII) == 0)
 		sc->sc_icr |= ICR_RXCFG;
 	CSR_WRITE(sc, WMREG_IMS, sc->sc_icr);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 		 || (sc->sc_type == WM_T_PCH2)) {
 		reg = CSR_READ(sc, WMREG_KABGTXD);
 		reg |= KABGTXD_BGSQLBIAS;
 		CSR_WRITE(sc, WMREG_KABGTXD, reg);
+	}
 	/* Set up the inter-packet gap. */
 	CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
 	if (sc->sc_type >= WM_T_82543) {
 		/*
 		 * Set up the interrupt throttling register (units of 256ns)
 		 * Note that a footnote in Intel's documentation says this
 		 * ticker runs at 1/4 the rate when the chip is in 100Mbit
 		 * or 10Mbit mode.  Empirically, it appears to be the case
 		 * that that is also true for the 1024ns units of the other
 		 * interrupt-related timer registers -- so, really, we ought
 		 * to divide this value by 4 when the link speed is low.
+		 *
 		 * XXX implement this division at link speed change!
 		 */
 		 /*
 		  * For N interrupts/sec, set this value to:
 		  * 1000000000 / (N * 256).  Note that we set the
 		  * absolute and packet timer values to this value
 		  * divided by 4 to get "simple timer" behavior.
 		  */
 		sc->sc_itr = 1500;		/* 2604 ints/sec */
 		CSR_WRITE(sc, WMREG_ITR, sc->sc_itr);
+	}
 	/* Set the VLAN ethernetype. */
 	CSR_WRITE(sc, WMREG_VET, ETHERTYPE_VLAN);
 	/*
 	 * Set up the transmit control register; we start out with
 	 * a collision distance suitable for FDX, but update it whe
 	 * we resolve the media type.
 	 */
 	sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_RTLC
 	    | TCTL_CT(TX_COLLISION_THRESHOLD)
 	    | TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 	if (sc->sc_type >= WM_T_82571)
 		sc->sc_tctl |= TCTL_MULR;
 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		/*
 		 * Write TDT after TCTL.EN is set.
 		 * See the document.
 		 */
 		CSR_WRITE(sc, WMREG_TDT, 0);
+	}
 	if (sc->sc_type == WM_T_80003) {
 		reg = CSR_READ(sc, WMREG_TCTL_EXT);
 		reg &= ~TCTL_EXT_GCEX_MASK;
 		reg |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
 		CSR_WRITE(sc, WMREG_TCTL_EXT, reg);
+	}
 	/* Set the media. */
 	if ((error = mii_ifmedia_change(&sc->sc_mii)) != 0)
 		goto out;
 	/* Configure for OS presence */
 	wm_init_manageability(sc);
 	/*
 	 * Set up the receive control register; we actually program
 	 * the register when we set the receive filter.  Use multicast
 	 * address offset type 0.
+	 *
 	 * Only the i82544 has the ability to strip the incoming
 	 * CRC, so we don't enable that feature.
 	 */
 	sc->sc_mchash_type = 0;
 	sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_DPF
 	    | RCTL_MO(sc->sc_mchash_type);
 	/*
 	 * The I350 has a bug where it always strips the CRC whether
 	 * asked to or not. So ask for stripped CRC here and cope in rxeof
 	 */
 	if ((sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210))
 		sc->sc_rctl |= RCTL_SECRC;
 	if (((sc->sc_ethercom.ec_capabilities & ETHERCAP_JUMBO_MTU) != 0)
 	    && (ifp->if_mtu > ETHERMTU)) {
 		sc->sc_rctl |= RCTL_LPE;
 		if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 			CSR_WRITE(sc, WMREG_RLPML, ETHER_MAX_LEN_JUMBO);
+	}
 	if (MCLBYTES == 2048) {
 		sc->sc_rctl |= RCTL_2k;
 	} else {
 		if (sc->sc_type >= WM_T_82543) {
 			switch (MCLBYTES) {
 			case 4096:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
 				break;
 			case 8192:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
 				break;
 			case 16384:
 				sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
 				break;
 			default:
 				panic("wm_init: MCLBYTES %d unsupported",
 				    MCLBYTES);
 				break;
+			}
 		} else panic("wm_init: i82542 requires MCLBYTES = 2048");
+	}
 	/* Set the receive filter. */
 	wm_set_filter(sc);
 	/* On 575 and later set RDT only if RX enabled */
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0)
 		for (i = 0; i < WM_NRXDESC; i++)
 			WM_INIT_RXDESC(sc, i);
 	/* Start the one second link check clock. */
 	callout_reset(&sc->sc_tick_ch, hz, wm_tick, sc);
 	/* ...all done! */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
  out:
 	sc->sc_if_flags = ifp->if_flags;
 	if (error)
 		log(LOG_ERR, "%s: interface not running\n",
 		    device_xname(sc->sc_dev));
 	return error;
+}
 /*
  * wm_rxdrain:
+ *
  *	Drain the receive queue.