 @@ -1,1078 +1,1078 @@
-/*	$NetBSD: if_wm.c,v 1.254 2013/06/11 10:07:09 msaitoh Exp $	*/
+/*	$NetBSD: if_wm.c,v 1.255 2013/06/11 14:39:35 msaitoh Exp $	*/
 /*
  * Copyright (c) 2001, 2002, 2003, 2004 Wasabi Systems, Inc.
  * All rights reserved.
+ *
  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  * 3. All advertising materials mentioning features or use of this software
  *    must display the following acknowledgement:
  *	This product includes software developed for the NetBSD Project by
  *	Wasabi Systems, Inc.
  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  *    or promote products derived from this software without specific prior
  *    written permission.
+ *
  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  */
 /*******************************************************************************
   Copyright (c) 2001-2005, Intel Corporation
   All rights reserved.
   Redistribution and use in source and binary forms, with or without
   modification, are permitted provided that the following conditions are met:
 . Redistributions of source code must retain the above copyright notice,
       this list of conditions and the following disclaimer.
 . Redistributions in binary form must reproduce the above copyright
       notice, this list of conditions and the following disclaimer in the
       documentation and/or other materials provided with the distribution.
 . Neither the name of the Intel Corporation nor the names of its
       contributors may be used to endorse or promote products derived from
       this software without specific prior written permission.
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 *******************************************************************************/
 /*
  * Device driver for the Intel i8254x family of Gigabit Ethernet chips.
+ *
  * TODO (in order of importance):
+ *
  *	- Rework how parameters are loaded from the EEPROM.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.254 2013/06/11 10:07:09 msaitoh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_wm.c,v 1.255 2013/06/11 14:39:35 msaitoh Exp $");
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/callout.h>
 #include <sys/mbuf.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/socket.h>
 #include <sys/ioctl.h>
 #include <sys/errno.h>
 #include <sys/device.h>
 #include <sys/queue.h>
 #include <sys/syslog.h>
 #include <sys/rnd.h>
 #include <net/if.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 #include <net/if_ether.h>
 #include <net/bpf.h>
 #include <netinet/in.h>			/* XXX for struct ip */
 #include <netinet/in_systm.h>		/* XXX for struct ip */
 #include <netinet/ip.h>			/* XXX for struct ip */
 #include <netinet/ip6.h>		/* XXX for struct ip6_hdr */
 #include <netinet/tcp.h>		/* XXX for struct tcphdr */
 #include <sys/bus.h>
 #include <sys/intr.h>
 #include <machine/endian.h>
 #include <dev/mii/mii.h>
 #include <dev/mii/miivar.h>
 #include <dev/mii/miidevs.h>
 #include <dev/mii/mii_bitbang.h>
 #include <dev/mii/ikphyreg.h>
 #include <dev/mii/igphyreg.h>
 #include <dev/mii/igphyvar.h>
 #include <dev/mii/inbmphyreg.h>
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcidevs.h>
 #include <dev/pci/if_wmreg.h>
 #include <dev/pci/if_wmvar.h>
 #ifdef WM_DEBUG
 #define	WM_DEBUG_LINK		0x01
 #define	WM_DEBUG_TX		0x02
 #define	WM_DEBUG_RX		0x04
 #define	WM_DEBUG_GMII		0x08
 #define	WM_DEBUG_MANAGE		0x10
 #define	WM_DEBUG_NVM		0x20
 int	wm_debug = WM_DEBUG_TX | WM_DEBUG_RX | WM_DEBUG_LINK | WM_DEBUG_GMII
     | WM_DEBUG_MANAGE | WM_DEBUG_NVM;
 #define	DPRINTF(x, y)	if (wm_debug & (x)) printf y
 #else
 #define	DPRINTF(x, y)	/* nothing */
 #endif /* WM_DEBUG */
 /*
  * Transmit descriptor list size.  Due to errata, we can only have
  * 256 hardware descriptors in the ring on < 82544, but we use 4096
  * on >= 82544.  We tell the upper layers that they can queue a lot
  * of packets, and we go ahead and manage up to 64 (16 for the i82547)
  * of them at a time.
+ *
  * We allow up to 256 (!) DMA segments per packet.  Pathological packet
  * chains containing many small mbufs have been observed in zero-copy
  * situations with jumbo frames.
  */
 #define	WM_NTXSEGS		256
 #define	WM_IFQUEUELEN		256
 #define	WM_TXQUEUELEN_MAX	64
 #define	WM_TXQUEUELEN_MAX_82547	16
 #define	WM_TXQUEUELEN(sc)	((sc)->sc_txnum)
 #define	WM_TXQUEUELEN_MASK(sc)	(WM_TXQUEUELEN(sc) - 1)
 #define	WM_TXQUEUE_GC(sc)	(WM_TXQUEUELEN(sc) / 8)
 #define	WM_NTXDESC_82542	256
 #define	WM_NTXDESC_82544	4096
 #define	WM_NTXDESC(sc)		((sc)->sc_ntxdesc)
 #define	WM_NTXDESC_MASK(sc)	(WM_NTXDESC(sc) - 1)
 #define	WM_TXDESCSIZE(sc)	(WM_NTXDESC(sc) * sizeof(wiseman_txdesc_t))
 #define	WM_NEXTTX(sc, x)	(((x) + 1) & WM_NTXDESC_MASK(sc))
 #define	WM_NEXTTXS(sc, x)	(((x) + 1) & WM_TXQUEUELEN_MASK(sc))
 #define	WM_MAXTXDMA		round_page(IP_MAXPACKET) /* for TSO */
 /*
  * Receive descriptor list size.  We have one Rx buffer for normal
  * sized packets.  Jumbo packets consume 5 Rx buffers for a full-sized
  * packet.  We allocate 256 receive descriptors, each with a 2k
  * buffer (MCLBYTES), which gives us room for 50 jumbo packets.
  */
 #define	WM_NRXDESC		256
 #define	WM_NRXDESC_MASK		(WM_NRXDESC - 1)
 #define	WM_NEXTRX(x)		(((x) + 1) & WM_NRXDESC_MASK)
 #define	WM_PREVRX(x)		(((x) - 1) & WM_NRXDESC_MASK)
 /*
  * Control structures are DMA'd to the i82542 chip.  We allocate them in
  * a single clump that maps to a single DMA segment to make several things
  * easier.
  */
 struct wm_control_data_82544 {
 	/*
 	 * The receive descriptors.
 	 */
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	/*
 	 * The transmit descriptors.  Put these at the end, because
 	 * we might use a smaller number of them.
 	 */
 	union {
 		wiseman_txdesc_t wcdu_txdescs[WM_NTXDESC_82544];
 		nq_txdesc_t      wcdu_nq_txdescs[WM_NTXDESC_82544];
 	} wdc_u;
 };
 struct wm_control_data_82542 {
 	wiseman_rxdesc_t wcd_rxdescs[WM_NRXDESC];
 	wiseman_txdesc_t wcd_txdescs[WM_NTXDESC_82542];
 };
 #define	WM_CDOFF(x)	offsetof(struct wm_control_data_82544, x)
 #define	WM_CDTXOFF(x)	WM_CDOFF(wdc_u.wcdu_txdescs[(x)])
 #define	WM_CDRXOFF(x)	WM_CDOFF(wcd_rxdescs[(x)])
 /*
  * Software state for transmit jobs.
  */
 struct wm_txsoft {
 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t txs_dmamap;	/* our DMA map */
 	int txs_firstdesc;		/* first descriptor in packet */
 	int txs_lastdesc;		/* last descriptor in packet */
 	int txs_ndesc;			/* # of descriptors used */
 };
 /*
  * Software state for receive buffers.  Each descriptor gets a
  * 2k (MCLBYTES) buffer and a DMA map.  For packets which fill
  * more than one buffer, we chain them together.
  */
 struct wm_rxsoft {
 	struct mbuf *rxs_mbuf;		/* head of our mbuf chain */
 	bus_dmamap_t rxs_dmamap;	/* our DMA map */
 };
 #define WM_LINKUP_TIMEOUT	50
 static uint16_t swfwphysem[] = {
 	SWFW_PHY0_SM,
 	SWFW_PHY1_SM,
 	SWFW_PHY2_SM,
 	SWFW_PHY3_SM
 };
 /*
  * Software state per device.
  */
 struct wm_softc {
 	device_t sc_dev;		/* generic device information */
 	bus_space_tag_t sc_st;		/* bus space tag */
 	bus_space_handle_t sc_sh;	/* bus space handle */
 	bus_size_t sc_ss;		/* bus space size */
 	bus_space_tag_t sc_iot;		/* I/O space tag */
 	bus_space_handle_t sc_ioh;	/* I/O space handle */
 	bus_size_t sc_ios;		/* I/O space size */
 	bus_space_tag_t sc_flasht;	/* flash registers space tag */
 	bus_space_handle_t sc_flashh;	/* flash registers space handle */
 	bus_dma_tag_t sc_dmat;		/* bus DMA tag */
 	struct ethercom sc_ethercom;	/* ethernet common data */
 	struct mii_data sc_mii;		/* MII/media information */
 	pci_chipset_tag_t sc_pc;
 	pcitag_t sc_pcitag;
 	int sc_bus_speed;		/* PCI/PCIX bus speed */
 	int sc_pcixe_capoff;		/* PCI[Xe] capability register offset */
 	const struct wm_product *sc_wmp; /* Pointer to the wm_product entry */
 	wm_chip_type sc_type;		/* MAC type */
 	int sc_rev;			/* MAC revision */
 	wm_phy_type sc_phytype;		/* PHY type */
 	int sc_funcid;			/* unit number of the chip (0 to 3) */
 	int sc_flags;			/* flags; see below */
 	int sc_if_flags;		/* last if_flags */
 	int sc_flowflags;		/* 802.3x flow control flags */
 	int sc_align_tweak;
 	void *sc_ih;			/* interrupt cookie */
 	callout_t sc_tick_ch;		/* tick callout */
 	int sc_ee_addrbits;		/* EEPROM address bits */
 	int sc_ich8_flash_base;
 	int sc_ich8_flash_bank_size;
 	int sc_nvm_k1_enabled;
 	/*
 	 * Software state for the transmit and receive descriptors.
 	 */
 	int sc_txnum;			/* must be a power of two */
 	struct wm_txsoft sc_txsoft[WM_TXQUEUELEN_MAX];
 	struct wm_rxsoft sc_rxsoft[WM_NRXDESC];
 	/*
 	 * Control data structures.
 	 */
 	int sc_ntxdesc;			/* must be a power of two */
 	struct wm_control_data_82544 *sc_control_data;
 	bus_dmamap_t sc_cddmamap;	/* control data DMA map */
 	bus_dma_segment_t sc_cd_seg;	/* control data segment */
 	int sc_cd_rseg;			/* real number of control segment */
 	size_t sc_cd_size;		/* control data size */
 #define	sc_cddma	sc_cddmamap->dm_segs[0].ds_addr
 #define	sc_txdescs	sc_control_data->wdc_u.wcdu_txdescs
 #define	sc_nq_txdescs	sc_control_data->wdc_u.wcdu_nq_txdescs
 #define	sc_rxdescs	sc_control_data->wcd_rxdescs
 #ifdef WM_EVENT_COUNTERS
 	/* Event counters. */
 	struct evcnt sc_ev_txsstall;	/* Tx stalled due to no txs */
 	struct evcnt sc_ev_txdstall;	/* Tx stalled due to no txd */
 	struct evcnt sc_ev_txfifo_stall;/* Tx FIFO stalls (82547) */
 	struct evcnt sc_ev_txdw;	/* Tx descriptor interrupts */
 	struct evcnt sc_ev_txqe;	/* Tx queue empty interrupts */
 	struct evcnt sc_ev_rxintr;	/* Rx interrupts */
 	struct evcnt sc_ev_linkintr;	/* Link interrupts */
 	struct evcnt sc_ev_rxipsum;	/* IP checksums checked in-bound */
 	struct evcnt sc_ev_rxtusum;	/* TCP/UDP cksums checked in-bound */
 	struct evcnt sc_ev_txipsum;	/* IP checksums comp. out-bound */
 	struct evcnt sc_ev_txtusum;	/* TCP/UDP cksums comp. out-bound */
 	struct evcnt sc_ev_txtusum6;	/* TCP/UDP v6 cksums comp. out-bound */
 	struct evcnt sc_ev_txtso;	/* TCP seg offload out-bound (IPv4) */
 	struct evcnt sc_ev_txtso6;	/* TCP seg offload out-bound (IPv6) */
 	struct evcnt sc_ev_txtsopain;	/* painful header manip. for TSO */
 	struct evcnt sc_ev_txseg[WM_NTXSEGS]; /* Tx packets w/ N segments */
 	struct evcnt sc_ev_txdrop;	/* Tx packets dropped (too many segs) */
 	struct evcnt sc_ev_tu;		/* Tx underrun */
 	struct evcnt sc_ev_tx_xoff;	/* Tx PAUSE(!0) frames */
 	struct evcnt sc_ev_tx_xon;	/* Tx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_xoff;	/* Rx PAUSE(!0) frames */
 	struct evcnt sc_ev_rx_xon;	/* Rx PAUSE(0) frames */
 	struct evcnt sc_ev_rx_macctl;	/* Rx Unsupported */
 #endif /* WM_EVENT_COUNTERS */
 	bus_addr_t sc_tdt_reg;		/* offset of TDT register */
 	int	sc_txfree;		/* number of free Tx descriptors */
 	int	sc_txnext;		/* next ready Tx descriptor */
 	int	sc_txsfree;		/* number of free Tx jobs */
 	int	sc_txsnext;		/* next free Tx job */
 	int	sc_txsdirty;		/* dirty Tx jobs */
 	/* These 5 variables are used only on the 82547. */
 	int	sc_txfifo_size;		/* Tx FIFO size */
 	int	sc_txfifo_head;		/* current head of FIFO */
 	uint32_t sc_txfifo_addr;	/* internal address of start of FIFO */
 	int	sc_txfifo_stall;	/* Tx FIFO is stalled */
 	callout_t sc_txfifo_ch;		/* Tx FIFO stall work-around timer */
 	bus_addr_t sc_rdt_reg;		/* offset of RDT register */
 	int	sc_rxptr;		/* next ready Rx descriptor/queue ent */
 	int	sc_rxdiscard;
 	int	sc_rxlen;
 	struct mbuf *sc_rxhead;
 	struct mbuf *sc_rxtail;
 	struct mbuf **sc_rxtailp;
 	uint32_t sc_ctrl;		/* prototype CTRL register */
 #if 0
 	uint32_t sc_ctrl_ext;		/* prototype CTRL_EXT register */
 #endif
 	uint32_t sc_icr;		/* prototype interrupt bits */
 	uint32_t sc_itr;		/* prototype intr throttling reg */
 	uint32_t sc_tctl;		/* prototype TCTL register */
 	uint32_t sc_rctl;		/* prototype RCTL register */
 	uint32_t sc_txcw;		/* prototype TXCW register */
 	uint32_t sc_tipg;		/* prototype TIPG register */
 	uint32_t sc_fcrtl;		/* prototype FCRTL register */
 	uint32_t sc_pba;		/* prototype PBA register */
 	int sc_tbi_linkup;		/* TBI link status */
 	int sc_tbi_anegticks;		/* autonegotiation ticks */
 	int sc_tbi_ticks;		/* tbi ticks */
 	int sc_tbi_nrxcfg;		/* count of ICR_RXCFG */
 	int sc_tbi_lastnrxcfg;		/* count of ICR_RXCFG (on last tick) */
 	int sc_mchash_type;		/* multicast filter offset */
 	krndsource_t rnd_source;	/* random source */
 };
 #define	WM_RXCHAIN_RESET(sc)						\
 do {									\
 	(sc)->sc_rxtailp = &(sc)->sc_rxhead;				\
 	*(sc)->sc_rxtailp = NULL;					\
 	(sc)->sc_rxlen = 0;						\
 } while (/*CONSTCOND*/0)
 #define	WM_RXCHAIN_LINK(sc, m)						\
 do {									\
 	*(sc)->sc_rxtailp = (sc)->sc_rxtail = (m);			\
 	(sc)->sc_rxtailp = &(m)->m_next;				\
 } while (/*CONSTCOND*/0)
 #ifdef WM_EVENT_COUNTERS
 #define	WM_EVCNT_INCR(ev)	(ev)->ev_count++
 #define	WM_EVCNT_ADD(ev, val)	(ev)->ev_count += (val)
 #else
 #define	WM_EVCNT_INCR(ev)	/* nothing */
 #define	WM_EVCNT_ADD(ev, val)	/* nothing */
 #endif
 #define	CSR_READ(sc, reg)						\
 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
 #define	CSR_WRITE(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
 #define	CSR_WRITE_FLUSH(sc)						\
 	(void) CSR_READ((sc), WMREG_STATUS)
 #define ICH8_FLASH_READ32(sc, reg) \
 	bus_space_read_4((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE32(sc, reg, data) \
 	bus_space_write_4((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define ICH8_FLASH_READ16(sc, reg) \
 	bus_space_read_2((sc)->sc_flasht, (sc)->sc_flashh, (reg))
 #define ICH8_FLASH_WRITE16(sc, reg, data) \
 	bus_space_write_2((sc)->sc_flasht, (sc)->sc_flashh, (reg), (data))
 #define	WM_CDTXADDR(sc, x)	((sc)->sc_cddma + WM_CDTXOFF((x)))
 #define	WM_CDRXADDR(sc, x)	((sc)->sc_cddma + WM_CDRXOFF((x)))
 #define	WM_CDTXADDR_LO(sc, x)	(WM_CDTXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDTXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDTXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDRXADDR_LO(sc, x)	(WM_CDRXADDR((sc), (x)) & 0xffffffffU)
 #define	WM_CDRXADDR_HI(sc, x)						\
 	(sizeof(bus_addr_t) == 8 ?					\
 	 (uint64_t)WM_CDRXADDR((sc), (x)) >> 32 : 0)
 #define	WM_CDTXSYNC(sc, x, n, ops)					\
 do {									\
 	int __x, __n;							\
+									\
 	__x = (x);							\
 	__n = (n);							\
+									\
 	/* If it will wrap around, sync to the end of the ring. */	\
 	if ((__x + __n) > WM_NTXDESC(sc)) {				\
 		bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,	\
 		    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) *		\
 		    (WM_NTXDESC(sc) - __x), (ops));			\
 		__n -= (WM_NTXDESC(sc) - __x);				\
 		__x = 0;						\
 	}								\
+									\
 	/* Now sync whatever is left. */				\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	    WM_CDTXOFF(__x), sizeof(wiseman_txdesc_t) * __n, (ops));	\
 } while (/*CONSTCOND*/0)
 #define	WM_CDRXSYNC(sc, x, ops)						\
 do {									\
 	bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,		\
 	   WM_CDRXOFF((x)), sizeof(wiseman_rxdesc_t), (ops));		\
 } while (/*CONSTCOND*/0)
 #define	WM_INIT_RXDESC(sc, x)						\
 do {									\
 	struct wm_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)];		\
 	wiseman_rxdesc_t *__rxd = &(sc)->sc_rxdescs[(x)];		\
 	struct mbuf *__m = __rxs->rxs_mbuf;				\
+									\
 	/*								\
 	 * Note: We scoot the packet forward 2 bytes in the buffer	\
 	 * so that the payload after the Ethernet header is aligned	\
 	 * to a 4-byte boundary.					\
 	 *								\
 	 * XXX BRAINDAMAGE ALERT!					\
 	 * The stupid chip uses the same size for every buffer, which	\
 	 * is set in the Receive Control register.  We are using the 2K	\
 	 * size option, but what we REALLY want is (2K - 2)!  For this	\
 	 * reason, we can't "scoot" packets longer than the standard	\
 	 * Ethernet MTU.  On strict-alignment platforms, if the total	\
 	 * size exceeds (2K - 2) we set align_tweak to 0 and let	\
 	 * the upper layer copy the headers.				\
 	 */								\
 	__m->m_data = __m->m_ext.ext_buf + (sc)->sc_align_tweak;	\
+									\
 	wm_set_dma_addr(&__rxd->wrx_addr,				\
 	    __rxs->rxs_dmamap->dm_segs[0].ds_addr + (sc)->sc_align_tweak); \
 	__rxd->wrx_len = 0;						\
 	__rxd->wrx_cksum = 0;						\
 	__rxd->wrx_status = 0;						\
 	__rxd->wrx_errors = 0;						\
 	__rxd->wrx_special = 0;						\
 	WM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
+									\
 	CSR_WRITE((sc), (sc)->sc_rdt_reg, (x));				\
 } while (/*CONSTCOND*/0)
 static void	wm_start(struct ifnet *);
 static void	wm_nq_start(struct ifnet *);
 static void	wm_watchdog(struct ifnet *);
 static int	wm_ifflags_cb(struct ethercom *);
 static int	wm_ioctl(struct ifnet *, u_long, void *);
 static int	wm_init(struct ifnet *);
 static void	wm_stop(struct ifnet *, int);
 static bool	wm_suspend(device_t, const pmf_qual_t *);
 static bool	wm_resume(device_t, const pmf_qual_t *);
 static void	wm_reset(struct wm_softc *);
 static void	wm_rxdrain(struct wm_softc *);
 static int	wm_add_rxbuf(struct wm_softc *, int);
 static int	wm_read_eeprom(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_read_eeprom_eerd(struct wm_softc *, int, int, u_int16_t *);
 static int	wm_validate_eeprom_checksum(struct wm_softc *);
 static int	wm_check_alt_mac_addr(struct wm_softc *);
 static int	wm_read_mac_addr(struct wm_softc *, uint8_t *);
 static void	wm_tick(void *);
 static void	wm_set_filter(struct wm_softc *);
 static void	wm_set_vlan(struct wm_softc *);
 static int	wm_intr(void *);
 static void	wm_txintr(struct wm_softc *);
 static void	wm_rxintr(struct wm_softc *);
 static void	wm_linkintr(struct wm_softc *, uint32_t);
 static void	wm_tbi_mediainit(struct wm_softc *);
 static int	wm_tbi_mediachange(struct ifnet *);
 static void	wm_tbi_mediastatus(struct ifnet *, struct ifmediareq *);
 static void	wm_tbi_set_linkled(struct wm_softc *);
 static void	wm_tbi_check_link(struct wm_softc *);
 static void	wm_gmii_reset(struct wm_softc *);
 static int	wm_gmii_i82543_readreg(device_t, int, int);
 static void	wm_gmii_i82543_writereg(device_t, int, int, int);
 static int	wm_gmii_i82544_readreg(device_t, int, int);
 static void	wm_gmii_i82544_writereg(device_t, int, int, int);
 static int	wm_gmii_i80003_readreg(device_t, int, int);
 static void	wm_gmii_i80003_writereg(device_t, int, int, int);
 static int	wm_gmii_bm_readreg(device_t, int, int);
 static void	wm_gmii_bm_writereg(device_t, int, int, int);
 static int	wm_gmii_hv_readreg(device_t, int, int);
 static void	wm_gmii_hv_writereg(device_t, int, int, int);
 static int	wm_gmii_82580_readreg(device_t, int, int);
 static void	wm_gmii_82580_writereg(device_t, int, int, int);
 static int	wm_sgmii_readreg(device_t, int, int);
 static void	wm_sgmii_writereg(device_t, int, int, int);
 static void	wm_gmii_statchg(struct ifnet *);
 static void	wm_gmii_mediainit(struct wm_softc *, pci_product_id_t);
 static int	wm_gmii_mediachange(struct ifnet *);
 static void	wm_gmii_mediastatus(struct ifnet *, struct ifmediareq *);
 static int	wm_kmrn_readreg(struct wm_softc *, int);
 static void	wm_kmrn_writereg(struct wm_softc *, int, int);
 static void	wm_set_spiaddrbits(struct wm_softc *);
 static int	wm_match(device_t, cfdata_t, void *);
 static void	wm_attach(device_t, device_t, void *);
 static int	wm_detach(device_t, int);
 static int	wm_is_onboard_nvm_eeprom(struct wm_softc *);
 static void	wm_get_auto_rd_done(struct wm_softc *);
 static void	wm_lan_init_done(struct wm_softc *);
 static void	wm_get_cfg_done(struct wm_softc *);
 static int	wm_get_swsm_semaphore(struct wm_softc *);
 static void	wm_put_swsm_semaphore(struct wm_softc *);
 static int	wm_poll_eerd_eewr_done(struct wm_softc *, int);
 static int	wm_get_swfw_semaphore(struct wm_softc *, uint16_t);
 static void	wm_put_swfw_semaphore(struct wm_softc *, uint16_t);
 static int	wm_get_swfwhw_semaphore(struct wm_softc *);
 static void	wm_put_swfwhw_semaphore(struct wm_softc *);
 static int	wm_read_eeprom_ich8(struct wm_softc *, int, int, uint16_t *);
 static int32_t	wm_ich8_cycle_init(struct wm_softc *);
 static int32_t	wm_ich8_flash_cycle(struct wm_softc *, uint32_t);
 static int32_t	wm_read_ich8_data(struct wm_softc *, uint32_t,
 		     uint32_t, uint16_t *);
 static int32_t	wm_read_ich8_byte(struct wm_softc *, uint32_t, uint8_t *);
 static int32_t	wm_read_ich8_word(struct wm_softc *, uint32_t, uint16_t *);
 static void	wm_82547_txfifo_stall(void *);
 static void	wm_gate_hw_phy_config_ich8lan(struct wm_softc *, int);
 static int	wm_check_mng_mode(struct wm_softc *);
 static int	wm_check_mng_mode_ich8lan(struct wm_softc *);
 static int	wm_check_mng_mode_82574(struct wm_softc *);
 static int	wm_check_mng_mode_generic(struct wm_softc *);
 static int	wm_enable_mng_pass_thru(struct wm_softc *);
 static int	wm_check_reset_block(struct wm_softc *);
 static void	wm_get_hw_control(struct wm_softc *);
 static int	wm_check_for_link(struct wm_softc *);
 static void	wm_kmrn_lock_loss_workaround_ich8lan(struct wm_softc *);
 static void	wm_gig_downshift_workaround_ich8lan(struct wm_softc *);
 #ifdef WM_WOL
 static void	wm_igp3_phy_powerdown_workaround_ich8lan(struct wm_softc *);
 #endif
 static void	wm_hv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_lv_phy_workaround_ich8lan(struct wm_softc *);
 static void	wm_k1_gig_workaround_hv(struct wm_softc *, int);
 static void	wm_set_mdio_slow_mode_hv(struct wm_softc *);
 static void	wm_configure_k1_ich8lan(struct wm_softc *, int);
 static void	wm_smbustopci(struct wm_softc *);
 static void	wm_set_pcie_completion_timeout(struct wm_softc *);
 static void	wm_reset_init_script_82575(struct wm_softc *);
 static void	wm_release_manageability(struct wm_softc *);
 static void	wm_release_hw_control(struct wm_softc *);
 static void	wm_get_wakeup(struct wm_softc *);
 #ifdef WM_WOL
 static void	wm_enable_phy_wakeup(struct wm_softc *);
 static void	wm_enable_wakeup(struct wm_softc *);
 #endif
 static void	wm_init_manageability(struct wm_softc *);
 static void	wm_set_eee_i350(struct wm_softc *);
 CFATTACH_DECL3_NEW(wm, sizeof(struct wm_softc),
     wm_match, wm_attach, wm_detach, NULL, NULL, NULL, DVF_DETACH_SHUTDOWN);
 /*
  * Devices supported by this driver.
  */
 static const struct wm_product {
 	pci_vendor_id_t		wmp_vendor;
 	pci_product_id_t	wmp_product;
 	const char		*wmp_name;
 	wm_chip_type		wmp_type;
 	int			wmp_flags;
 #define	WMP_F_1000X		0x01
 #define	WMP_F_1000T		0x02
 #define	WMP_F_SERDES		0x04
 } wm_products[] = {
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82542,
 	  "Intel i82542 1000BASE-X Ethernet",
 	  WM_T_82542_2_1,	WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_FIBER,
 	  "Intel i82543GC 1000BASE-X Ethernet",
 	  WM_T_82543,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82543GC_COPPER,
 	  "Intel i82543GC 1000BASE-T Ethernet",
 	  WM_T_82543,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_COPPER,
 	  "Intel i82544EI 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544EI_FIBER,
 	  "Intel i82544EI 1000BASE-X Ethernet",
 	  WM_T_82544,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_COPPER,
 	  "Intel i82544GC 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82544GC_LOM,
 	  "Intel i82544GC (LOM) 1000BASE-T Ethernet",
 	  WM_T_82544,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM,
 	  "Intel i82540EM 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EM_LOM,
 	  "Intel i82540EM (LOM) 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LOM,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82540EP_LP,
 	  "Intel i82540EP 1000BASE-T Ethernet",
 	  WM_T_82540,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_COPPER,
 	  "Intel i82545EM 1000BASE-T Ethernet",
 	  WM_T_82545,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_COPPER,
 	  "Intel i82545GM 1000BASE-T Ethernet",
 	  WM_T_82545_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_FIBER,
 	  "Intel i82545GM 1000BASE-X Ethernet",
 	  WM_T_82545_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545GM_SERDES,
 	  "Intel i82545GM Gigabit Ethernet (SERDES)",
 	  WM_T_82545_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_COPPER,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_QUAD,
 	  "Intel i82546EB 1000BASE-T Ethernet",
 	  WM_T_82546,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82545EM_FIBER,
 	  "Intel i82545EM 1000BASE-X Ethernet",
 	  WM_T_82545,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546EB_FIBER,
 	  "Intel i82546EB 1000BASE-X Ethernet",
 	  WM_T_82546,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_COPPER,
 	  "Intel i82546GB 1000BASE-T Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_FIBER,
 	  "Intel i82546GB 1000BASE-X Ethernet",
 	  WM_T_82546_3,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_SERDES,
 	  "Intel i82546GB Gigabit Ethernet (SERDES)",
 	  WM_T_82546_3,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER,
 	  "i82546GB quad-port Gigabit Ethernet",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER_KSP3,
 	  "i82546GB quad-port Gigabit Ethernet (KSP3)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82546GB_PCIE,
 	  "Intel PRO/1000MT (82546GB)",
 	  WM_T_82546_3,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI,
 	  "Intel i82541EI 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER_LOM,
 	  "Intel i82541ER (LOM) 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541EI_MOBILE,
 	  "Intel i82541EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541ER,
 	  "Intel i82541ER 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI,
 	  "Intel i82541GI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541GI_MOBILE,
 	  "Intel i82541GI Mobile 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82541PI,
 	  "Intel i82541PI 1000BASE-T Ethernet",
 	  WM_T_82541_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI,
 	  "Intel i82547EI 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547EI_MOBILE,
 	  "Intel i82547EI Mobile 1000BASE-T Ethernet",
 	  WM_T_82547,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82547GI,
 	  "Intel i82547GI 1000BASE-T Ethernet",
 	  WM_T_82547_2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_COPPER,
 	  "Intel PRO/1000 PT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_FIBER,
 	  "Intel PRO/1000 PF (82571EB)",
 	  WM_T_82571,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_SERDES,
 	  "Intel PRO/1000 PB (82571EB)",
 	  WM_T_82571,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571EB_QUAD_COPPER,
 	  "Intel PRO/1000 QT (82571EB)",
 	  WM_T_82571,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_COPPER,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82571GB_QUAD_COPPER,
 	  "Intel PRO/1000 PT Quad Port Server Adapter",
 	  WM_T_82571,		WMP_F_1000T, },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_FIBER,
 	  "Intel i82572EI 1000baseX Ethernet",
 	  WM_T_82572,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI_SERDES,
 	  "Intel i82572EI Gigabit Ethernet (SERDES)",
 	  WM_T_82572,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82572EI,
 	  "Intel i82572EI 1000baseT Ethernet",
 	  WM_T_82572,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E,
 	  "Intel i82573E",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573E_IAMT,
 	  "Intel i82573E IAMT",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82573L,
 	  "Intel i82573L Gigabit Ethernet",
 	  WM_T_82573,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82574L,
 	  "Intel i82574L",
 	  WM_T_82574,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82583V,
 	  "Intel i82583V",
 	  WM_T_82583,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_DPT,
 	  "i80003 dual 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_FIB_DPT,
 	  "i80003 dual 1000baseX Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_DPT,
 	  "Intel i80003ES2 dual Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_CPR_SPT,
 	  "Intel i80003 1000baseT Ethernet",
 	  WM_T_80003,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_80K3LAN_SDS_SPT,
 	  "Intel i80003 Gigabit Ethernet (SERDES)",
 	  WM_T_80003,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_AMT,
 	  "Intel i82801H (M_AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_AMT,
 	  "Intel i82801H (AMT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_LAN,
 	  "Intel i82801H LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_LAN,
 	  "Intel i82801H (IFE) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_M_LAN,
 	  "Intel i82801H (M) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_GT,
 	  "Intel i82801H IFE (GT) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IFE_G,
 	  "Intel i82801H IFE (G) LAN Controller",
 	  WM_T_ICH8,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_AMT,
 	  "82801I (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE,
 	  "82801I LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_G,
 	  "82801I (G) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IFE_GT,
 	  "82801I (GT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_C,
 	  "82801I (C) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M,
 	  "82801I mobile LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801H_IGP_M_V,
 	  "82801I mobile (V) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_IGP_M_AMT,
 	  "82801I mobile (AMT) LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_BM,
 	  "82567LM-4 LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801I_82567V_3,
 	  "82567V-3 LAN Controller",
 	  WM_T_ICH9,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LM,
 	  "82567LM-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_LF,
 	  "82567LF-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LM,
 	  "82567LM-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_LF,
 	  "82567LF-3 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_R_BM_V,
 	  "82567V-2 LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82801J_D_BM_V,
 	  "82567V-3? LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_HANKSVILLE,
 	  "HANKSVILLE LAN Controller",
 	  WM_T_ICH10,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LM,
 	  "PCH LAN (82577LM) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_M_LC,
 	  "PCH LAN (82577LC) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DM,
 	  "PCH LAN (82578DM) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH_D_DC,
 	  "PCH LAN (82578DC) Controller",
 	  WM_T_PCH,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_LM,
 	  "PCH2 LAN (82579LM) Controller",
 	  WM_T_PCH2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_PCH2_LV_V,
 	  "PCH2 LAN (82579V) Controller",
 	  WM_T_PCH2,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_COPPER,
 	  "82575EB dual-1000baseT Ethernet",
 	  WM_T_82575,		WMP_F_1000T },
 #if 0
 	/*
 	 * not sure if WMP_F_1000X or WMP_F_SERDES - we do not have it - so
 	 * disabled for now ...
 	 */
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575EB_FIBER_SERDES,
 	  "82575EB dual-1000baseX Ethernet (SERDES)",
 	  WM_T_82575,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER,
 	  "82575GB quad-1000baseT Ethernet",
 	  WM_T_82575,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82575GB_QUAD_COPPER_PM,
 	  "82575GB quad-1000baseT Ethernet (PM)",
 	  WM_T_82575,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_COPPER,
 	  "82576 1000BaseT Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_FIBER,
 	  "82576 1000BaseX Ethernet",
 	  WM_T_82576,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES,
 	  "82576 gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_QUAD_COPPER,
 	  "82576 quad-1000BaseT Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS,
 	  "82576 gigabit Ethernet",
 	  WM_T_82576,		WMP_F_1000T },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_NS_SERDES,
 	  "82576 gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82576_SERDES_QUAD,
 	  "82576 quad-gigabit Ethernet (SERDES)",
 	  WM_T_82576,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER,
 	  "82580 1000BaseT Ethernet",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_FIBER,
 	  "82580 1000BaseX Ethernet",
 	  WM_T_82580,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SERDES,
 	  "82580 1000BaseT Ethernet (SERDES)",
 	  WM_T_82580,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_SGMII,
 	  "82580 gigabit Ethernet (SGMII)",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_COPPER_DUAL,
 	  "82580 dual-1000BaseT Ethernet",
 	  WM_T_82580,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_ER,
 	  "82580 1000BaseT Ethernet",
 	  WM_T_82580ER,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_ER_DUAL,
 	  "82580 dual-1000BaseT Ethernet",
 	  WM_T_82580ER,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82580_QUAD_FIBER,
 	  "82580 quad-1000BaseX Ethernet",
 	  WM_T_82580,		WMP_F_1000X },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_COPPER,
 	  "I350 Gigabit Network Connection",
 	  WM_T_I350,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_FIBER,
 	  "I350 Gigabit Fiber Network Connection",
 	  WM_T_I350,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SERDES,
 	  "I350 Gigabit Backplane Connection",
 	  WM_T_I350,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I350_SGMII,
 	  "I350 Gigabit Connection",
 	  WM_T_I350,		WMP_F_1000T },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_T1,
 	  "I210-T1 Ethernet Server Adapter",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_OEM1,
 	  "I210 Ethernet (Copper OEM)",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_COPPER_IT,
 	  "I210 Ethernet (Copper IT)",
 	  WM_T_I210,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_FIBER,
 	  "I210 Gigabit Ethernet (Fiber)",
 	  WM_T_I210,		WMP_F_1000X },
 #if 0
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SERDES,
 	  "I210 Gigabit Ethernet (SERDES)",
 	  WM_T_I210,		WMP_F_SERDES },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I210_SGMII,
 	  "I210 Gigabit Ethernet (SGMII)",
 	  WM_T_I210,		WMP_F_SERDES },
 #endif
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I211_COPPER,
 	  "I211 Ethernet (COPPER)",
 	  WM_T_I211,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_V,
 	  "I217 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I217_LM,
 	  "I217 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_V,
 	  "I218 V Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_I218_LM,
 	  "I218 LM Ethernet Connection",
 	  WM_T_PCH_LPT,		WMP_F_1000T },
 	{ 0,			0,
 	  NULL,
 ,			0 },
 };
 #ifdef WM_EVENT_COUNTERS
 static char wm_txseg_evcnt_names[WM_NTXSEGS][sizeof("txsegXXX")];
 #endif /* WM_EVENT_COUNTERS */
 #if 0 /* Not currently used */
 static inline uint32_t
 wm_io_read(struct wm_softc *sc, int reg)
+{
 	bus_space_write_4(sc->sc_iot, sc->sc_ioh, 0, reg);
 	return (bus_space_read_4(sc->sc_iot, sc->sc_ioh, 4));
+}
 #endif
 @@ -5346,1999 +5346,2000 @@ wm_validate_eeprom_checksum(struct wm_so
 	/* Don't check for I211 */
 	if (sc->sc_type == WM_T_I211)
 		return 0;
 	if (sc->sc_type == WM_T_PCH_LPT) {
 		csum_wordaddr = NVM_COMPAT;
 		valid_checksum = NVM_COMPAT_VALID_CHECKSUM;
 	} else {
 		csum_wordaddr = NVM_FUTURE_INIT_WORD1;
 		valid_checksum = NVM_FUTURE_INIT_WORD1_VALID_CHECKSUM;
+	}
 #ifdef WM_DEBUG
 	/* Dump EEPROM image for debug */
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		wm_read_eeprom(sc, csum_wordaddr, 1, &eeprom_data);
 		if ((eeprom_data & valid_checksum) == 0) {
 			DPRINTF(WM_DEBUG_NVM,
 			    ("%s: NVM need to be updated (%04x != %04x)\n",
 				device_xname(sc->sc_dev), eeprom_data,
 				    valid_checksum));
+		}
+	}
 	if ((wm_debug & WM_DEBUG_NVM) != 0) {
 		printf("%s: NVM dump:\n", device_xname(sc->sc_dev));
 		for (i = 0; i < EEPROM_SIZE; i++) {
 			if (wm_read_eeprom(sc, i, 1, &eeprom_data))
 				printf("XX ");
 			else
 				printf("%04x ", eeprom_data);
 			if (i % 8 == 7)
 				printf("\n");
+		}
+	}
 #endif /* WM_DEBUG */
 	for (i = 0; i < EEPROM_SIZE; i++) {
 		if (wm_read_eeprom(sc, i, 1, &eeprom_data))
 			return 1;
 		checksum += eeprom_data;
+	}
 	if (checksum != (uint16_t) NVM_CHECKSUM) {
 #ifdef WM_DEBUG
 		printf("%s: NVM checksum mismatch (%04x != %04x)\n",
 		    device_xname(sc->sc_dev), checksum, NVM_CHECKSUM);
 #endif
+	}
 	return 0;
+}
 /*
  * wm_read_eeprom:
+ *
  *	Read data from the serial EEPROM.
  */
 static int
 wm_read_eeprom(struct wm_softc *sc, int word, int wordcnt, uint16_t *data)
+{
 	int rv;
 	if (sc->sc_flags & WM_F_EEPROM_INVALID)
 		return 1;
 	if (wm_acquire_eeprom(sc))
 		return 1;
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
 		rv = wm_read_eeprom_ich8(sc, word, wordcnt, data);
 	else if (sc->sc_flags & WM_F_EEPROM_EERDEEWR)
 		rv = wm_read_eeprom_eerd(sc, word, wordcnt, data);
 	else if (sc->sc_flags & WM_F_EEPROM_SPI)
 		rv = wm_read_eeprom_spi(sc, word, wordcnt, data);
 	else
 		rv = wm_read_eeprom_uwire(sc, word, wordcnt, data);
 	wm_release_eeprom(sc);
 	return rv;
+}
 static int
 wm_read_eeprom_eerd(struct wm_softc *sc, int offset, int wordcnt,
     uint16_t *data)
+{
 	int i, eerd = 0;
 	int error = 0;
 	for (i = 0; i < wordcnt; i++) {
 		eerd = ((offset + i) << EERD_ADDR_SHIFT) | EERD_START;
 		CSR_WRITE(sc, WMREG_EERD, eerd);
 		error = wm_poll_eerd_eewr_done(sc, WMREG_EERD);
 		if (error != 0)
 			break;
 		data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
+	}
 	return error;
+}
 static int
 wm_poll_eerd_eewr_done(struct wm_softc *sc, int rw)
+{
 	uint32_t attempts = 100000;
 	uint32_t i, reg = 0;
 	int32_t done = -1;
 	for (i = 0; i < attempts; i++) {
 		reg = CSR_READ(sc, rw);
 		if (reg & EERD_DONE) {
 			done = 0;
 			break;
+		}
 		delay(5);
+	}
 	return done;
+}
 static int
 wm_check_alt_mac_addr(struct wm_softc *sc)
+{
 	uint16_t myea[ETHER_ADDR_LEN / 2];
 	uint16_t offset = EEPROM_OFF_MACADDR;
 	/* Try to read alternative MAC address pointer */
 	if (wm_read_eeprom(sc, EEPROM_ALT_MAC_ADDR_PTR, 1, &offset) != 0)
 		return -1;
 	/* Check pointer */
 	if (offset == 0xffff)
 		return -1;
 	/*
 	 * Check whether alternative MAC address is valid or not.
 	 * Some cards have non 0xffff pointer but those don't use
 	 * alternative MAC address in reality.
+	 *
 	 * Check whether the broadcast bit is set or not.
 	 */
 	if (wm_read_eeprom(sc, offset, 1, myea) == 0)
 		if (((myea[0] & 0xff) & 0x01) == 0)
 			return 0; /* found! */
 	/* not found */
 	return -1;
+}
 static int
 wm_read_mac_addr(struct wm_softc *sc, uint8_t *enaddr)
+{
 	uint16_t myea[ETHER_ADDR_LEN / 2];
 	uint16_t offset = EEPROM_OFF_MACADDR;
 	int do_invert = 0;
 	switch (sc->sc_type) {
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 		switch (sc->sc_funcid) {
 		case 0:
 			/* default value (== EEPROM_OFF_MACADDR) */
 			break;
 		case 1:
 			offset = EEPROM_OFF_LAN1;
 			break;
 		case 2:
 			offset = EEPROM_OFF_LAN2;
 			break;
 		case 3:
 			offset = EEPROM_OFF_LAN3;
 			break;
 		default:
 			goto bad;
 			/* NOTREACHED */
 			break;
+		}
 		break;
 	case WM_T_82571:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_80003:
 	case WM_T_I210:
 	case WM_T_I211:
 		if (wm_check_alt_mac_addr(sc) != 0) {
 			/* reset the offset to LAN0 */
 			offset = EEPROM_OFF_MACADDR;
 			if ((sc->sc_funcid & 0x01) == 1)
 				do_invert = 1;
 			goto do_read;
+		}
 		switch (sc->sc_funcid) {
 		case 0:
 			/*
 			 * The offset is the value in EEPROM_ALT_MAC_ADDR_PTR
 			 * itself.
 			 */
 			break;
 		case 1:
 			offset += EEPROM_OFF_MACADDR_LAN1;
 			break;
 		case 2:
 			offset += EEPROM_OFF_MACADDR_LAN2;
 			break;
 		case 3:
 			offset += EEPROM_OFF_MACADDR_LAN3;
 			break;
 		default:
 			goto bad;
 			/* NOTREACHED */
 			break;
+		}
 		break;
 	default:
 		if ((sc->sc_funcid & 0x01) == 1)
 			do_invert = 1;
 		break;
+	}
  do_read:
 	if (wm_read_eeprom(sc, offset, sizeof(myea) / sizeof(myea[0]),
 		myea) != 0) {
 		goto bad;
+	}
 	enaddr[0] = myea[0] & 0xff;
 	enaddr[1] = myea[0] >> 8;
 	enaddr[2] = myea[1] & 0xff;
 	enaddr[3] = myea[1] >> 8;
 	enaddr[4] = myea[2] & 0xff;
 	enaddr[5] = myea[2] >> 8;
 	/*
 	 * Toggle the LSB of the MAC address on the second port
 	 * of some dual port cards.
 	 */
 	if (do_invert != 0)
 		enaddr[5] ^= 1;
 	return 0;
  bad:
 	aprint_error_dev(sc->sc_dev, "unable to read Ethernet address\n");
 	return -1;
+}
 /*
  * wm_add_rxbuf:
+ *
  *	Add a receive buffer to the indiciated descriptor.
  */
 static int
 wm_add_rxbuf(struct wm_softc *sc, int idx)
+{
 	struct wm_rxsoft *rxs = &sc->sc_rxsoft[idx];
 	struct mbuf *m;
 	int error;
 	MGETHDR(m, M_DONTWAIT, MT_DATA);
 	if (m == NULL)
 		return ENOBUFS;
 	MCLGET(m, M_DONTWAIT);
 	if ((m->m_flags & M_EXT) == 0) {
 		m_freem(m);
 		return ENOBUFS;
+	}
 	if (rxs->rxs_mbuf != NULL)
 		bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
 	rxs->rxs_mbuf = m;
 	m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
 	error = bus_dmamap_load_mbuf(sc->sc_dmat, rxs->rxs_dmamap, m,
 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
 	if (error) {
 		/* XXX XXX XXX */
 		aprint_error_dev(sc->sc_dev,
 		    "unable to load rx DMA map %d, error = %d\n",
 		    idx, error);
 		panic("wm_add_rxbuf");
+	}
 	bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 	if ((sc->sc_flags & WM_F_NEWQUEUE) != 0) {
 		if ((sc->sc_rctl & RCTL_EN) != 0)
 			WM_INIT_RXDESC(sc, idx);
 	} else
 		WM_INIT_RXDESC(sc, idx);
 	return 0;
+}
 /*
  * wm_set_ral:
+ *
  *	Set an entery in the receive address list.
  */
 static void
 wm_set_ral(struct wm_softc *sc, const uint8_t *enaddr, int idx)
+{
 	uint32_t ral_lo, ral_hi;
 	if (enaddr != NULL) {
 		ral_lo = enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) |
 		    (enaddr[3] << 24);
 		ral_hi = enaddr[4] | (enaddr[5] << 8);
 		ral_hi |= RAL_AV;
 	} else {
 		ral_lo = 0;
 		ral_hi = 0;
+	}
 	if (sc->sc_type >= WM_T_82544) {
 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_CORDOVA_RAL_BASE, idx),
 		    ral_lo);
 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_CORDOVA_RAL_BASE, idx),
 		    ral_hi);
 	} else {
 		CSR_WRITE(sc, WMREG_RAL_LO(WMREG_RAL_BASE, idx), ral_lo);
 		CSR_WRITE(sc, WMREG_RAL_HI(WMREG_RAL_BASE, idx), ral_hi);
+	}
+}
 /*
  * wm_mchash:
+ *
  *	Compute the hash of the multicast address for the 4096-bit
  *	multicast filter.
  */
 static uint32_t
 wm_mchash(struct wm_softc *sc, const uint8_t *enaddr)
+{
 	static const int lo_shift[4] = { 4, 3, 2, 0 };
 	static const int hi_shift[4] = { 4, 5, 6, 8 };
 	static const int ich8_lo_shift[4] = { 6, 5, 4, 2 };
 	static const int ich8_hi_shift[4] = { 2, 3, 4, 6 };
 	uint32_t hash;
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) {
 		hash = (enaddr[4] >> ich8_lo_shift[sc->sc_mchash_type]) |
 		    (((uint16_t) enaddr[5]) << ich8_hi_shift[sc->sc_mchash_type]);
 		return (hash & 0x3ff);
+	}
 	hash = (enaddr[4] >> lo_shift[sc->sc_mchash_type]) |
 	    (((uint16_t) enaddr[5]) << hi_shift[sc->sc_mchash_type]);
 	return (hash & 0xfff);
+}
 /*
  * wm_set_filter:
+ *
  *	Set up the receive filter.
  */
 static void
 wm_set_filter(struct wm_softc *sc)
+{
 	struct ethercom *ec = &sc->sc_ethercom;
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ether_multi *enm;
 	struct ether_multistep step;
 	bus_addr_t mta_reg;
 	uint32_t hash, reg, bit;
 	int i, size;
 	if (sc->sc_type >= WM_T_82544)
 		mta_reg = WMREG_CORDOVA_MTA;
 	else
 		mta_reg = WMREG_MTA;
 	sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
 	if (ifp->if_flags & IFF_BROADCAST)
 		sc->sc_rctl |= RCTL_BAM;
 	if (ifp->if_flags & IFF_PROMISC) {
 		sc->sc_rctl |= RCTL_UPE;
 		goto allmulti;
+	}
 	/*
 	 * Set the station address in the first RAL slot, and
 	 * clear the remaining slots.
 	 */
 	if (sc->sc_type == WM_T_ICH8)
 		size = WM_RAL_TABSIZE_ICH8 -1;
 	else if ((sc->sc_type == WM_T_ICH9) || (sc->sc_type == WM_T_ICH10)
 	    || (sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 	    || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_RAL_TABSIZE_ICH8;
 	else if (sc->sc_type == WM_T_82575)
 		size = WM_RAL_TABSIZE_82575;
 	else if ((sc->sc_type == WM_T_82576) || (sc->sc_type == WM_T_82580))
 		size = WM_RAL_TABSIZE_82576;
 	else if (sc->sc_type == WM_T_I350)
 		size = WM_RAL_TABSIZE_I350;
 	else
 		size = WM_RAL_TABSIZE;
 	wm_set_ral(sc, CLLADDR(ifp->if_sadl), 0);
 	for (i = 1; i < size; i++)
 		wm_set_ral(sc, NULL, i);
 	if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 	    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 	    || (sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT))
 		size = WM_ICH8_MC_TABSIZE;
 	else
 		size = WM_MC_TABSIZE;
 	/* Clear out the multicast table. */
 	for (i = 0; i < size; i++)
 		CSR_WRITE(sc, mta_reg + (i << 2), 0);
 	ETHER_FIRST_MULTI(step, ec, enm);
 	while (enm != NULL) {
 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 			/*
 			 * We must listen to a range of multicast addresses.
 			 * For now, just accept all multicasts, rather than
 			 * trying to set only those filter bits needed to match
 			 * the range.  (At this time, the only use of address
 			 * ranges is for IP multicast routing, for which the
 			 * range is big enough to require all bits set.)
 			 */
 			goto allmulti;
+		}
 		hash = wm_mchash(sc, enm->enm_addrlo);
 		reg = (hash >> 5);
 		if ((sc->sc_type == WM_T_ICH8) || (sc->sc_type == WM_T_ICH9)
 		    || (sc->sc_type == WM_T_ICH10) || (sc->sc_type == WM_T_PCH)
 		    || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT))
 			reg &= 0x1f;
 		else
 			reg &= 0x7f;
 		bit = hash & 0x1f;
 		hash = CSR_READ(sc, mta_reg + (reg << 2));
 		hash |= 1U << bit;
 		/* XXX Hardware bug?? */
 		if (sc->sc_type == WM_T_82544 && (reg & 0xe) == 1) {
 			bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 			CSR_WRITE(sc, mta_reg + ((reg - 1) << 2), bit);
 		} else
 			CSR_WRITE(sc, mta_reg + (reg << 2), hash);
 		ETHER_NEXT_MULTI(step, enm);
+	}
 	ifp->if_flags &= ~IFF_ALLMULTI;
 	goto setit;
  allmulti:
 	ifp->if_flags |= IFF_ALLMULTI;
 	sc->sc_rctl |= RCTL_MPE;
  setit:
 	CSR_WRITE(sc, WMREG_RCTL, sc->sc_rctl);
+}
 /*
  * wm_tbi_mediainit:
+ *
  *	Initialize media for use on 1000BASE-X devices.
  */
 static void
 wm_tbi_mediainit(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	const char *sep = "";
 	if (sc->sc_type < WM_T_82543)
 		sc->sc_tipg = TIPG_WM_DFLT;
 	else
 		sc->sc_tipg = TIPG_LG_DFLT;
 	sc->sc_tbi_anegticks = 5;
 	/* Initialize our media structures */
 	sc->sc_mii.mii_ifp = ifp;
 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
 	ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_tbi_mediachange,
 	    wm_tbi_mediastatus);
 	/*
 	 * SWD Pins:
+	 *
 	 *	0 = Link LED (output)
 	 *	1 = Loss Of Signal (input)
 	 */
 	sc->sc_ctrl |= CTRL_SWDPIO(0);
 	sc->sc_ctrl &= ~CTRL_SWDPIO(1);
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 #define	ADD(ss, mm, dd)							\
 do {									\
 	aprint_normal("%s%s", sep, ss);					\
 	ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|(mm), (dd), NULL);	\
 	sep = ", ";							\
 } while (/*CONSTCOND*/0)
 	aprint_normal_dev(sc->sc_dev, "");
 	ADD("1000baseSX", IFM_1000_SX, ANAR_X_HD);
 	ADD("1000baseSX-FDX", IFM_1000_SX|IFM_FDX, ANAR_X_FD);
 	ADD("auto", IFM_AUTO, ANAR_X_FD|ANAR_X_HD);
 	aprint_normal("\n");
 #undef ADD
 	ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO);
+}
 /*
  * wm_tbi_mediastatus:	[ifmedia interface function]
+ *
  *	Get the current interface media status on a 1000BASE-X device.
  */
 static void
 wm_tbi_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	uint32_t ctrl, status;
 	ifmr->ifm_status = IFM_AVALID;
 	ifmr->ifm_active = IFM_ETHER;
 	status = CSR_READ(sc, WMREG_STATUS);
 	if ((status & STATUS_LU) == 0) {
 		ifmr->ifm_active |= IFM_NONE;
 		return;
+	}
 	ifmr->ifm_status |= IFM_ACTIVE;
 	ifmr->ifm_active |= IFM_1000_SX;
 	if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
 		ifmr->ifm_active |= IFM_FDX;
 	ctrl = CSR_READ(sc, WMREG_CTRL);
 	if (ctrl & CTRL_RFCE)
 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_RXPAUSE;
 	if (ctrl & CTRL_TFCE)
 		ifmr->ifm_active |= IFM_FLOW | IFM_ETH_TXPAUSE;
+}
 /*
  * wm_tbi_mediachange:	[ifmedia interface function]
+ *
  *	Set hardware to newly-selected media on a 1000BASE-X device.
  */
 static int
 wm_tbi_mediachange(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
 	uint32_t status;
 	int i;
 	sc->sc_txcw = 0;
 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
 	    (sc->sc_mii.mii_media.ifm_media & IFM_FLOW) != 0)
 		sc->sc_txcw |= TXCW_SYM_PAUSE | TXCW_ASYM_PAUSE;
 	if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 		sc->sc_txcw |= TXCW_ANE;
 	} else {
 		/*
 		 * If autonegotiation is turned off, force link up and turn on
 		 * full duplex
 		 */
 		sc->sc_txcw &= ~TXCW_ANE;
 		sc->sc_ctrl |= CTRL_SLU | CTRL_FD;
 		sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		delay(1000);
+	}
 	DPRINTF(WM_DEBUG_LINK,("%s: sc_txcw = 0x%x after autoneg check\n",
 		    device_xname(sc->sc_dev),sc->sc_txcw));
 	CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
 	delay(10000);
 	i = CSR_READ(sc, WMREG_CTRL) & CTRL_SWDPIN(1);
 	DPRINTF(WM_DEBUG_LINK,("%s: i = 0x%x\n", device_xname(sc->sc_dev),i));
 	/*
 	 * On 82544 chips and later, the CTRL_SWDPIN(1) bit will be set if the
 	 * optics detect a signal, 0 if they don't.
 	 */
 	if (((i != 0) && (sc->sc_type > WM_T_82544)) || (i == 0)) {
 		/* Have signal; wait for the link to come up. */
 		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/*
 			 * Reset the link, and let autonegotiation do its thing
 			 */
 			sc->sc_ctrl |= CTRL_LRST;
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 			delay(1000);
 			sc->sc_ctrl &= ~CTRL_LRST;
 			CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 			delay(1000);
+		}
 		for (i = 0; i < WM_LINKUP_TIMEOUT; i++) {
 			delay(10000);
 			if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
 				break;
+		}
 		DPRINTF(WM_DEBUG_LINK,("%s: i = %d after waiting for link\n",
 			    device_xname(sc->sc_dev),i));
 		status = CSR_READ(sc, WMREG_STATUS);
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: status after final read = 0x%x, STATUS_LU = 0x%x\n",
 			device_xname(sc->sc_dev),status, STATUS_LU));
 		if (status & STATUS_LU) {
 			/* Link is up. */
 			DPRINTF(WM_DEBUG_LINK,
 			    ("%s: LINK: set media -> link up %s\n",
 			    device_xname(sc->sc_dev),
 			    (status & STATUS_FD) ? "FDX" : "HDX"));
 			/*
 			 * NOTE: CTRL will update TFCE and RFCE automatically,
 			 * so we should update sc->sc_ctrl
 			 */
 			sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
 			sc->sc_tctl &= ~TCTL_COLD(0x3ff);
 			sc->sc_fcrtl &= ~FCRTL_XONE;
 			if (status & STATUS_FD)
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 			else
 				sc->sc_tctl |=
 				    TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
 			if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
 				sc->sc_fcrtl |= FCRTL_XONE;
 			CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 			CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ?
 				      WMREG_OLD_FCRTL : WMREG_FCRTL,
 				      sc->sc_fcrtl);
 			sc->sc_tbi_linkup = 1;
 		} else {
 			if (i == WM_LINKUP_TIMEOUT)
 				wm_check_for_link(sc);
 			/* Link is down. */
 			DPRINTF(WM_DEBUG_LINK,
 			    ("%s: LINK: set media -> link down\n",
 			    device_xname(sc->sc_dev)));
 			sc->sc_tbi_linkup = 0;
+		}
 	} else {
 		DPRINTF(WM_DEBUG_LINK, ("%s: LINK: set media -> no signal\n",
 		    device_xname(sc->sc_dev)));
 		sc->sc_tbi_linkup = 0;
+	}
 	wm_tbi_set_linkled(sc);
 	return 0;
+}
 /*
  * wm_tbi_set_linkled:
+ *
  *	Update the link LED on 1000BASE-X devices.
  */
 static void
 wm_tbi_set_linkled(struct wm_softc *sc)
+{
 	if (sc->sc_tbi_linkup)
 		sc->sc_ctrl |= CTRL_SWDPIN(0);
 	else
 		sc->sc_ctrl &= ~CTRL_SWDPIN(0);
 	/* 82540 or newer devices are active low */
 	sc->sc_ctrl ^= (sc->sc_type >= WM_T_82540) ? CTRL_SWDPIN(0) : 0;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
+}
 /*
  * wm_tbi_check_link:
+ *
  *	Check the link on 1000BASE-X devices.
  */
 static void
 wm_tbi_check_link(struct wm_softc *sc)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
 	uint32_t rxcw, ctrl, status;
 	status = CSR_READ(sc, WMREG_STATUS);
 	rxcw = CSR_READ(sc, WMREG_RXCW);
 	ctrl = CSR_READ(sc, WMREG_CTRL);
 	/* set link status */
 	if ((status & STATUS_LU) == 0) {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK: checklink -> down\n", device_xname(sc->sc_dev)));
 		sc->sc_tbi_linkup = 0;
 	} else if (sc->sc_tbi_linkup == 0) {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK: checklink -> up %s\n", device_xname(sc->sc_dev),
 		    (status & STATUS_FD) ? "FDX" : "HDX"));
 		sc->sc_tbi_linkup = 1;
+	}
 	if ((sc->sc_ethercom.ec_if.if_flags & IFF_UP)
 	    && ((status & STATUS_LU) == 0)) {
 		sc->sc_tbi_linkup = 0;
 		if (sc->sc_tbi_nrxcfg - sc->sc_tbi_lastnrxcfg > 100) {
 			/* RXCFG storm! */
 			DPRINTF(WM_DEBUG_LINK, ("RXCFG storm! (%d)\n",
 				sc->sc_tbi_nrxcfg - sc->sc_tbi_lastnrxcfg));
 			wm_init(ifp);
 			ifp->if_start(ifp);
 		} else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 			/* If the timer expired, retry autonegotiation */
 			if (++sc->sc_tbi_ticks >= sc->sc_tbi_anegticks) {
 				DPRINTF(WM_DEBUG_LINK, ("EXPIRE\n"));
 				sc->sc_tbi_ticks = 0;
 				/*
 				 * Reset the link, and let autonegotiation do
 				 * its thing
 				 */
 				sc->sc_ctrl |= CTRL_LRST;
 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 				delay(1000);
 				sc->sc_ctrl &= ~CTRL_LRST;
 				CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 				delay(1000);
 				CSR_WRITE(sc, WMREG_TXCW,
 				    sc->sc_txcw & ~TXCW_ANE);
 				CSR_WRITE(sc, WMREG_TXCW, sc->sc_txcw);
+			}
+		}
+	}
 	wm_tbi_set_linkled(sc);
+}
 /*
  * wm_gmii_reset:
+ *
  *	Reset the PHY.
  */
 static void
 wm_gmii_reset(struct wm_softc *sc)
+{
 	uint32_t reg;
 	int rv;
 	/* get phy semaphore */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		 /* XXX should get sw semaphore, too */
 		rv = wm_get_swsm_semaphore(sc);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		rv = wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		rv = wm_get_swfwhw_semaphore(sc);
 		break;
 	default:
 		/* nothing to do*/
 		rv = 0;
 		break;
+	}
 	if (rv != 0) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 		/* null */
 		break;
 	case WM_T_82543:
 		/*
 		 * With 82543, we need to force speed and duplex on the MAC
 		 * equal to what the PHY speed and duplex configuration is.
 		 * In addition, we need to perform a hardware reset on the PHY
 		 * to take it out of reset.
 		 */
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		/* The PHY reset pin is active-low. */
 		reg = CSR_READ(sc, WMREG_CTRL_EXT);
 		reg &= ~((CTRL_EXT_SWDPIO_MASK << CTRL_EXT_SWDPIO_SHIFT) |
 		    CTRL_EXT_SWDPIN(4));
 		reg |= CTRL_EXT_SWDPIO(4);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg);
 		delay(10*1000);
 		CSR_WRITE(sc, WMREG_CTRL_EXT, reg | CTRL_EXT_SWDPIN(4));
 		delay(150);
 #if 0
 		sc->sc_ctrl_ext = reg | CTRL_EXT_SWDPIN(4);
 #endif
 		delay(20*1000);	/* XXX extra delay to get PHY ID? */
 		break;
 	case WM_T_82544:	/* reset 10000us */
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541:
 	case WM_T_82541_2:
 	case WM_T_82547:
 	case WM_T_82547_2:
 	case WM_T_82571:	/* reset 100us */
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_82583:
 	case WM_T_80003:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		delay(20000);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		delay(20000);
 		if ((sc->sc_type == WM_T_82541)
 		    || (sc->sc_type == WM_T_82541_2)
 		    || (sc->sc_type == WM_T_82547)
 		    || (sc->sc_type == WM_T_82547_2)) {
 			/* workaround for igp are done in igp_reset() */
 			/* XXX add code to set LED after phy reset */
+		}
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* generic reset */
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
 		delay(100);
 		CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 		delay(150);
 		break;
 	default:
 		panic("%s: %s: unknown type\n", device_xname(sc->sc_dev),
 		    __func__);
 		break;
+	}
 	/* release PHY semaphore */
 	switch (sc->sc_type) {
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82583:
 		 /* XXX should put sw semaphore, too */
 		wm_put_swsm_semaphore(sc);
 		break;
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_80003:
 		wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		wm_put_swfwhw_semaphore(sc);
 		break;
 	default:
 		/* nothing to do*/
 		rv = 0;
 		break;
+	}
 	/* get_cfg_done */
 	wm_get_cfg_done(sc);
 	/* extra setup */
 	switch (sc->sc_type) {
 	case WM_T_82542_2_0:
 	case WM_T_82542_2_1:
 	case WM_T_82543:
 	case WM_T_82544:
 	case WM_T_82540:
 	case WM_T_82545:
 	case WM_T_82545_3:
 	case WM_T_82546:
 	case WM_T_82546_3:
 	case WM_T_82541_2:
 	case WM_T_82547_2:
 	case WM_T_82571:
 	case WM_T_82572:
 	case WM_T_82573:
 	case WM_T_82574:
 	case WM_T_82575:
 	case WM_T_82576:
 	case WM_T_82580:
 	case WM_T_82580ER:
 	case WM_T_I350:
 	case WM_T_I210:
 	case WM_T_I211:
 	case WM_T_82583:
 	case WM_T_80003:
 		/* null */
 		break;
 	case WM_T_82541:
 	case WM_T_82547:
 		/* XXX Configure actively LED after PHY reset */
 		break;
 	case WM_T_ICH8:
 	case WM_T_ICH9:
 	case WM_T_ICH10:
 	case WM_T_PCH:
 	case WM_T_PCH2:
 	case WM_T_PCH_LPT:
 		/* Allow time for h/w to get to a quiescent state afer reset */
 		delay(10*1000);
 		if (sc->sc_type == WM_T_PCH)
 			wm_hv_phy_workaround_ich8lan(sc);
 		if (sc->sc_type == WM_T_PCH2)
 			wm_lv_phy_workaround_ich8lan(sc);
 		if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) {
 			/*
 			 * dummy read to clear the phy wakeup bit after lcd
 			 * reset
 			 */
 			reg = wm_gmii_hv_readreg(sc->sc_dev, 1, BM_WUC);
+		}
 		/*
 		 * XXX Configure the LCD with th extended configuration region
 		 * in NVM
 		 */
 		/* Configure the LCD with the OEM bits in NVM */
-		if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)) {
+		if ((sc->sc_type == WM_T_PCH) || (sc->sc_type == WM_T_PCH2)
 		    || (sc->sc_type == WM_T_PCH_LPT)) {
 			/*
 			 * Disable LPLU.
 			 * XXX It seems that 82567 has LPLU, too.
 			 */
 			reg = wm_gmii_hv_readreg(sc->sc_dev, 1, HV_OEM_BITS);
 			reg &= ~(HV_OEM_BITS_A1KDIS| HV_OEM_BITS_LPLU);
 			reg |= HV_OEM_BITS_ANEGNOW;
 			wm_gmii_hv_writereg(sc->sc_dev, 1, HV_OEM_BITS, reg);
+		}
 		break;
 	default:
 		panic("%s: unknown type\n", __func__);
 		break;
+	}
+}
 /*
  * wm_gmii_mediainit:
+ *
  *	Initialize media for use on 1000BASE-T devices.
  */
 static void
 wm_gmii_mediainit(struct wm_softc *sc, pci_product_id_t prodid)
+{
 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 	struct mii_data *mii = &sc->sc_mii;
 	/* We have MII. */
 	sc->sc_flags |= WM_F_HAS_MII;
 	if (sc->sc_type == WM_T_80003)
 		sc->sc_tipg =  TIPG_1000T_80003_DFLT;
 	else
 		sc->sc_tipg = TIPG_1000T_DFLT;
 	/*
 	 * Let the chip set speed/duplex on its own based on
 	 * signals from the PHY.
 	 * XXXbouyer - I'm not sure this is right for the 80003,
 	 * the em driver only sets CTRL_SLU here - but it seems to work.
 	 */
 	sc->sc_ctrl |= CTRL_SLU;
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	/* Initialize our media structures and probe the GMII. */
 	mii->mii_ifp = ifp;
 	/*
 	 * Determine the PHY access method.
+	 *
 	 *  For SGMII, use SGMII specific method.
+	 *
 	 *  For some devices, we can determine the PHY access method
 	 * from sc_type.
+	 *
 	 *  For ICH8 variants, it's difficult to detemine the PHY access
 	 * method by sc_type, so use the PCI product ID for some devices.
 	 * For other ICH8 variants, try to use igp's method. If the PHY
 	 * can't detect, then use bm's method.
 	 */
 	switch (prodid) {
 	case PCI_PRODUCT_INTEL_PCH_M_LM:
 	case PCI_PRODUCT_INTEL_PCH_M_LC:
 		/* 82577 */
 		sc->sc_phytype = WMPHY_82577;
 		mii->mii_readreg = wm_gmii_hv_readreg;
 		mii->mii_writereg = wm_gmii_hv_writereg;
 		break;
 	case PCI_PRODUCT_INTEL_PCH_D_DM:
 	case PCI_PRODUCT_INTEL_PCH_D_DC:
 		/* 82578 */
 		sc->sc_phytype = WMPHY_82578;
 		mii->mii_readreg = wm_gmii_hv_readreg;
 		mii->mii_writereg = wm_gmii_hv_writereg;
 		break;
 	case PCI_PRODUCT_INTEL_PCH2_LV_LM:
 	case PCI_PRODUCT_INTEL_PCH2_LV_V:
 		/* 82579 */
 		sc->sc_phytype = WMPHY_82579;
 		mii->mii_readreg = wm_gmii_hv_readreg;
 		mii->mii_writereg = wm_gmii_hv_writereg;
 		break;
 	case PCI_PRODUCT_INTEL_I217_LM:
 	case PCI_PRODUCT_INTEL_I217_V:
 	case PCI_PRODUCT_INTEL_I218_LM:
 	case PCI_PRODUCT_INTEL_I218_V:
 		/* I21[78] */
 		mii->mii_readreg = wm_gmii_hv_readreg;
 		mii->mii_writereg = wm_gmii_hv_writereg;
 		break;
 	case PCI_PRODUCT_INTEL_82801I_BM:
 	case PCI_PRODUCT_INTEL_82801J_R_BM_LM:
 	case PCI_PRODUCT_INTEL_82801J_R_BM_LF:
 	case PCI_PRODUCT_INTEL_82801J_D_BM_LM:
 	case PCI_PRODUCT_INTEL_82801J_D_BM_LF:
 	case PCI_PRODUCT_INTEL_82801J_R_BM_V:
 		/* 82567 */
 		sc->sc_phytype = WMPHY_BM;
 		mii->mii_readreg = wm_gmii_bm_readreg;
 		mii->mii_writereg = wm_gmii_bm_writereg;
 		break;
 	default:
 		if ((sc->sc_flags & WM_F_SGMII) != 0) {
 			mii->mii_readreg = wm_sgmii_readreg;
 			mii->mii_writereg = wm_sgmii_writereg;
 		} else if (sc->sc_type >= WM_T_80003) {
 			mii->mii_readreg = wm_gmii_i80003_readreg;
 			mii->mii_writereg = wm_gmii_i80003_writereg;
 		} else if (sc->sc_type >= WM_T_I210) {
 			mii->mii_readreg = wm_gmii_i82544_readreg;
 			mii->mii_writereg = wm_gmii_i82544_writereg;
 		} else if (sc->sc_type >= WM_T_82580) {
 			sc->sc_phytype = WMPHY_82580;
 			mii->mii_readreg = wm_gmii_82580_readreg;
 			mii->mii_writereg = wm_gmii_82580_writereg;
 		} else if (sc->sc_type >= WM_T_82544) {
 			mii->mii_readreg = wm_gmii_i82544_readreg;
 			mii->mii_writereg = wm_gmii_i82544_writereg;
 		} else {
 			mii->mii_readreg = wm_gmii_i82543_readreg;
 			mii->mii_writereg = wm_gmii_i82543_writereg;
+		}
 		break;
+	}
 	mii->mii_statchg = wm_gmii_statchg;
 	wm_gmii_reset(sc);
 	sc->sc_ethercom.ec_mii = &sc->sc_mii;
 	ifmedia_init(&mii->mii_media, IFM_IMASK, wm_gmii_mediachange,
 	    wm_gmii_mediastatus);
 	if ((sc->sc_type == WM_T_82575) || (sc->sc_type == WM_T_82576)
 	    || (sc->sc_type == WM_T_82580) || (sc->sc_type == WM_T_82580ER)
 	    || (sc->sc_type == WM_T_I350) || (sc->sc_type == WM_T_I210)
 	    || (sc->sc_type == WM_T_I211)) {
 		if ((sc->sc_flags & WM_F_SGMII) == 0) {
 			/* Attach only one port */
 			mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 1,
 			    MII_OFFSET_ANY, MIIF_DOPAUSE);
 		} else {
 			int i;
 			uint32_t ctrl_ext;
 			/* Power on sgmii phy if it is disabled */
 			ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
 			CSR_WRITE(sc, WMREG_CTRL_EXT,
 			    ctrl_ext &~ CTRL_EXT_SWDPIN(3));
 			CSR_WRITE_FLUSH(sc);
 			delay(300*1000); /* XXX too long */
 			/* from 1 to 8 */
 			for (i = 1; i < 8; i++)
 				mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff,
 				    i, MII_OFFSET_ANY, MIIF_DOPAUSE);
 			/* restore previous sfp cage power state */
 			CSR_WRITE(sc, WMREG_CTRL_EXT, ctrl_ext);
+		}
 	} else {
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
 	 * If the MAC is PCH2 or PCH_LPT and failed to detect MII PHY, call
 	 * wm_set_mdio_slow_mode_hv() for a workaround and retry.
 	 */
 	if (((sc->sc_type == WM_T_PCH2) || (sc->sc_type == WM_T_PCH_LPT)) &&
 	    (LIST_FIRST(&mii->mii_phys) == NULL)) {
 		wm_set_mdio_slow_mode_hv(sc);
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	/*
 	 * (For ICH8 variants)
 	 * If PHY detection failed, use BM's r/w function and retry.
 	 */
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* if failed, retry with *_bm_* */
 		mii->mii_readreg = wm_gmii_bm_readreg;
 		mii->mii_writereg = wm_gmii_bm_writereg;
 		mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
+	}
 	if (LIST_FIRST(&mii->mii_phys) == NULL) {
 		/* Any PHY wasn't find */
 		ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
 		ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE);
 		sc->sc_phytype = WMPHY_NONE;
 	} else {
 		/*
 		 * PHY Found!
 		 * Check PHY type.
 		 */
 		uint32_t model;
 		struct mii_softc *child;
 		child = LIST_FIRST(&mii->mii_phys);
 		if (device_is_a(child->mii_dev, "igphy")) {
 			struct igphy_softc *isc = (struct igphy_softc *)child;
 			model = isc->sc_mii.mii_mpd_model;
 			if (model == MII_MODEL_yyINTEL_I82566)
 				sc->sc_phytype = WMPHY_IGP_3;
+		}
 		ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
+	}
+}
 /*
  * wm_gmii_mediastatus:	[ifmedia interface function]
+ *
  *	Get the current interface media status on a 1000BASE-T device.
  */
 static void
 wm_gmii_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	ether_mediastatus(ifp, ifmr);
 	ifmr->ifm_active = (ifmr->ifm_active & ~IFM_ETH_FMASK)
 	    | sc->sc_flowflags;
+}
 /*
  * wm_gmii_mediachange:	[ifmedia interface function]
+ *
  *	Set hardware to newly-selected media on a 1000BASE-T device.
  */
 static int
 wm_gmii_mediachange(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct ifmedia_entry *ife = sc->sc_mii.mii_media.ifm_cur;
 	int rc;
 	if ((ifp->if_flags & IFF_UP) == 0)
 		return 0;
 	sc->sc_ctrl &= ~(CTRL_SPEED_MASK | CTRL_FD);
 	sc->sc_ctrl |= CTRL_SLU;
 	if ((IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO)
 	    || (sc->sc_type > WM_T_82543)) {
 		sc->sc_ctrl &= ~(CTRL_FRCSPD | CTRL_FRCFDX);
 	} else {
 		sc->sc_ctrl &= ~CTRL_ASDE;
 		sc->sc_ctrl |= CTRL_FRCSPD | CTRL_FRCFDX;
 		if (ife->ifm_media & IFM_FDX)
 			sc->sc_ctrl |= CTRL_FD;
 		switch (IFM_SUBTYPE(ife->ifm_media)) {
 		case IFM_10_T:
 			sc->sc_ctrl |= CTRL_SPEED_10;
 			break;
 		case IFM_100_TX:
 			sc->sc_ctrl |= CTRL_SPEED_100;
 			break;
 		case IFM_1000_T:
 			sc->sc_ctrl |= CTRL_SPEED_1000;
 			break;
 		default:
 			panic("wm_gmii_mediachange: bad media 0x%x",
 			    ife->ifm_media);
+		}
+	}
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	if (sc->sc_type <= WM_T_82543)
 		wm_gmii_reset(sc);
 	if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO)
 		return 0;
 	return rc;
+}
 #define	MDI_IO		CTRL_SWDPIN(2)
 #define	MDI_DIR		CTRL_SWDPIO(2)	/* host -> PHY */
 #define	MDI_CLK		CTRL_SWDPIN(3)
 static void
 i82543_mii_sendbits(struct wm_softc *sc, uint32_t data, int nbits)
+{
 	uint32_t i, v;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= MDI_DIR | CTRL_SWDPIO(3);
 	for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
 		if (data & i)
 			v |= MDI_IO;
 		else
 			v &= ~MDI_IO;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		delay(10);
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		delay(10);
+	}
+}
 static uint32_t
 i82543_mii_recvbits(struct wm_softc *sc)
+{
 	uint32_t v, i, data = 0;
 	v = CSR_READ(sc, WMREG_CTRL);
 	v &= ~(MDI_IO|MDI_CLK|(CTRL_SWDPIO_MASK << CTRL_SWDPIO_SHIFT));
 	v |= CTRL_SWDPIO(3);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	delay(10);
 	for (i = 0; i < 16; i++) {
 		data <<= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 		delay(10);
 		if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
 			data |= 1;
 		CSR_WRITE(sc, WMREG_CTRL, v);
 		delay(10);
+	}
 	CSR_WRITE(sc, WMREG_CTRL, v | MDI_CLK);
 	delay(10);
 	CSR_WRITE(sc, WMREG_CTRL, v);
 	delay(10);
 	return data;
+}
 #undef MDI_IO
 #undef MDI_DIR
 #undef MDI_CLK
 /*
  * wm_gmii_i82543_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII (i82543 version).
  */
 static int
 wm_gmii_i82543_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	int rv;
 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	i82543_mii_sendbits(sc, reg | (phy << 5) |
 	    (MII_COMMAND_READ << 10) | (MII_COMMAND_START << 12), 14);
 	rv = i82543_mii_recvbits(sc) & 0xffff;
 	DPRINTF(WM_DEBUG_GMII,
 	    ("%s: GMII: read phy %d reg %d -> 0x%04x\n",
 	    device_xname(sc->sc_dev), phy, reg, rv));
 	return rv;
+}
 /*
  * wm_gmii_i82543_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII (i82543 version).
  */
 static void
 wm_gmii_i82543_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	i82543_mii_sendbits(sc, 0xffffffffU, 32);
 	i82543_mii_sendbits(sc, val | (MII_COMMAND_ACK << 16) |
 	    (reg << 18) | (phy << 23) | (MII_COMMAND_WRITE << 28) |
 	    (MII_COMMAND_START << 30), 32);
+}
 /*
  * wm_gmii_i82544_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the GMII.
  */
 static int
 wm_gmii_i82544_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	uint32_t mdic = 0;
 	int i, rv;
 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_READ | MDIC_PHYADD(phy) |
 	    MDIC_REGADD(reg));
 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
 		mdic = CSR_READ(sc, WMREG_MDIC);
 		if (mdic & MDIC_READY)
 			break;
 		delay(50);
+	}
 	if ((mdic & MDIC_READY) == 0) {
 		log(LOG_WARNING, "%s: MDIC read timed out: phy %d reg %d\n",
 		    device_xname(sc->sc_dev), phy, reg);
 		rv = 0;
 	} else if (mdic & MDIC_E) {
 #if 0 /* This is normal if no PHY is present. */
 		log(LOG_WARNING, "%s: MDIC read error: phy %d reg %d\n",
 		    device_xname(sc->sc_dev), phy, reg);
 #endif
 		rv = 0;
 	} else {
 		rv = MDIC_DATA(mdic);
 		if (rv == 0xffff)
 			rv = 0;
+	}
 	return rv;
+}
 /*
  * wm_gmii_i82544_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the GMII.
  */
 static void
 wm_gmii_i82544_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	uint32_t mdic = 0;
 	int i;
 	CSR_WRITE(sc, WMREG_MDIC, MDIC_OP_WRITE | MDIC_PHYADD(phy) |
 	    MDIC_REGADD(reg) | MDIC_DATA(val));
 	for (i = 0; i < WM_GEN_POLL_TIMEOUT * 3; i++) {
 		mdic = CSR_READ(sc, WMREG_MDIC);
 		if (mdic & MDIC_READY)
 			break;
 		delay(50);
+	}
 	if ((mdic & MDIC_READY) == 0)
 		log(LOG_WARNING, "%s: MDIC write timed out: phy %d reg %d\n",
 		    device_xname(sc->sc_dev), phy, reg);
 	else if (mdic & MDIC_E)
 		log(LOG_WARNING, "%s: MDIC write error: phy %d reg %d\n",
 		    device_xname(sc->sc_dev), phy, reg);
+}
 /*
  * wm_gmii_i80003_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the kumeran
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static int
 wm_gmii_i80003_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	int rv;
 	if (phy != 1) /* only one PHY on kumeran bus */
 		return 0;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return 0;
+	}
 	if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
 		    reg >> GG82563_PAGE_SHIFT);
 	} else {
 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
 		    reg >> GG82563_PAGE_SHIFT);
+	}
 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
 	delay(200);
 	rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
 	delay(200);
 	wm_put_swfw_semaphore(sc, sem);
 	return rv;
+}
 /*
  * wm_gmii_i80003_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the kumeran.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static void
 wm_gmii_i80003_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	if (phy != 1) /* only one PHY on kumeran bus */
 		return;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	if ((reg & GG82563_MAX_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT,
 		    reg >> GG82563_PAGE_SHIFT);
 	} else {
 		wm_gmii_i82544_writereg(self, phy, GG82563_PHY_PAGE_SELECT_ALT,
 		    reg >> GG82563_PAGE_SHIFT);
+	}
 	/* Wait more 200us for a bug of the ready bit in the MDIC register */
 	delay(200);
 	wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
 	delay(200);
 	wm_put_swfw_semaphore(sc, sem);
+}
 /*
  * wm_gmii_bm_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the kumeran
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static int
 wm_gmii_bm_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	int rv;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return 0;
+	}
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		if (phy == 1)
 			wm_gmii_i82544_writereg(self, phy, MII_IGPHY_PAGE_SELECT,
 			    reg);
 		else
 			wm_gmii_i82544_writereg(self, phy,
 			    GG82563_PHY_PAGE_SELECT,
 			    reg >> GG82563_PAGE_SHIFT);
+	}
 	rv = wm_gmii_i82544_readreg(self, phy, reg & GG82563_MAX_REG_ADDRESS);
 	wm_put_swfw_semaphore(sc, sem);
 	return rv;
+}
 /*
  * wm_gmii_bm_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the kumeran.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static void
 wm_gmii_bm_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	if (reg > BME1000_MAX_MULTI_PAGE_REG) {
 		if (phy == 1)
 			wm_gmii_i82544_writereg(self, phy, MII_IGPHY_PAGE_SELECT,
 			    reg);
 		else
 			wm_gmii_i82544_writereg(self, phy,
 			    GG82563_PHY_PAGE_SELECT,
 			    reg >> GG82563_PAGE_SHIFT);
+	}
 	wm_gmii_i82544_writereg(self, phy, reg & GG82563_MAX_REG_ADDRESS, val);
 	wm_put_swfw_semaphore(sc, sem);
+}
 static void
 wm_access_phy_wakeup_reg_bm(device_t self, int offset, int16_t *val, int rd)
+{
 	struct wm_softc *sc = device_private(self);
 	uint16_t regnum = BM_PHY_REG_NUM(offset);
 	uint16_t wuce;
 	/* XXX Gig must be disabled for MDIO accesses to page 800 */
 	if (sc->sc_type == WM_T_PCH) {
 		/* XXX e1000 driver do nothing... why? */
+	}
 	/* Set page 769 */
 	wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
 	wuce = wm_gmii_i82544_readreg(self, 1, BM_WUC_ENABLE_REG);
 	wuce &= ~BM_WUC_HOST_WU_BIT;
 	wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG,
 	    wuce | BM_WUC_ENABLE_BIT);
 	/* Select page 800 */
 	wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
 	    BM_WUC_PAGE << BME1000_PAGE_SHIFT);
 	/* Write page 800 */
 	wm_gmii_i82544_writereg(self, 1, BM_WUC_ADDRESS_OPCODE, regnum);
 	if (rd)
 		*val = wm_gmii_i82544_readreg(self, 1, BM_WUC_DATA_OPCODE);
 	else
 		wm_gmii_i82544_writereg(self, 1, BM_WUC_DATA_OPCODE, *val);
 	/* Set page 769 */
 	wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
 	    BM_WUC_ENABLE_PAGE << BME1000_PAGE_SHIFT);
 	wm_gmii_i82544_writereg(self, 1, BM_WUC_ENABLE_REG, wuce);
+}
 /*
  * wm_gmii_hv_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the kumeran
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static int
 wm_gmii_hv_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	uint16_t page = BM_PHY_REG_PAGE(reg);
 	uint16_t regnum = BM_PHY_REG_NUM(reg);
 	uint16_t val;
 	int rv;
 	if (wm_get_swfw_semaphore(sc, SWFW_PHY0_SM)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return 0;
+	}
 	/* XXX Workaround failure in MDIO access while cable is disconnected */
 	if (sc->sc_phytype == WMPHY_82577) {
 		/* XXX must write */
+	}
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		wm_access_phy_wakeup_reg_bm(self, reg, &val, 1);
 		return val;
+	}
 	/*
 	 * Lower than page 768 works differently than the rest so it has its
 	 * own func
 	 */
 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
 		printf("gmii_hv_readreg!!!\n");
 		return 0;
+	}
 	if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
 		wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
 		    page << BME1000_PAGE_SHIFT);
+	}
 	rv = wm_gmii_i82544_readreg(self, phy, regnum & IGPHY_MAXREGADDR);
 	wm_put_swfw_semaphore(sc, SWFW_PHY0_SM);
 	return rv;
+}
 /*
  * wm_gmii_hv_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the kumeran.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static void
 wm_gmii_hv_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	uint16_t page = BM_PHY_REG_PAGE(reg);
 	uint16_t regnum = BM_PHY_REG_NUM(reg);
 	if (wm_get_swfw_semaphore(sc, SWFW_PHY0_SM)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	/* XXX Workaround failure in MDIO access while cable is disconnected */
 	/* Page 800 works differently than the rest so it has its own func */
 	if (page == BM_WUC_PAGE) {
 		uint16_t tmp;
 		tmp = val;
 		wm_access_phy_wakeup_reg_bm(self, reg, &tmp, 0);
 		return;
+	}
 	/*
 	 * Lower than page 768 works differently than the rest so it has its
 	 * own func
 	 */
 	if ((page > 0) && (page < HV_INTC_FC_PAGE_START)) {
 		printf("gmii_hv_writereg!!!\n");
 		return;
+	}
 	/*
 	 * XXX Workaround MDIO accesses being disabled after entering IEEE
 	 * Power Down (whenever bit 11 of the PHY control register is set)
 	 */
 	if (regnum > BME1000_MAX_MULTI_PAGE_REG) {
 		wm_gmii_i82544_writereg(self, 1, MII_IGPHY_PAGE_SELECT,
 		    page << BME1000_PAGE_SHIFT);
+	}
 	wm_gmii_i82544_writereg(self, phy, regnum & IGPHY_MAXREGADDR, val);
 	wm_put_swfw_semaphore(sc, SWFW_PHY0_SM);
+}
 /*
  * wm_sgmii_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the SGMII
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static int
 wm_sgmii_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	uint32_t i2ccmd;
 	int i, rv;
 	if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return 0;
+	}
 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
 	    | I2CCMD_OPCODE_READ;
 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
 	/* Poll the ready bit */
 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
 		delay(50);
 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
 		if (i2ccmd & I2CCMD_READY)
 			break;
+	}
 	if ((i2ccmd & I2CCMD_READY) == 0)
 		aprint_error_dev(sc->sc_dev, "I2CCMD Read did not complete\n");
 	if ((i2ccmd & I2CCMD_ERROR) != 0)
 		aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n");
 	rv = ((i2ccmd >> 8) & 0x00ff) | ((i2ccmd << 8) & 0xff00);
 	wm_put_swfw_semaphore(sc, swfwphysem[sc->sc_funcid]);
 	return rv;
+}
 /*
  * wm_sgmii_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the SGMII.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static void
 wm_sgmii_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	uint32_t i2ccmd;
 	int i;
 	if (wm_get_swfw_semaphore(sc, swfwphysem[sc->sc_funcid])) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	i2ccmd = (reg << I2CCMD_REG_ADDR_SHIFT)
 	    | (phy << I2CCMD_PHY_ADDR_SHIFT)
 	    | I2CCMD_OPCODE_WRITE;
 	CSR_WRITE(sc, WMREG_I2CCMD, i2ccmd);
 	/* Poll the ready bit */
 	for (i = 0; i < I2CCMD_PHY_TIMEOUT; i++) {
 		delay(50);
 		i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
 		if (i2ccmd & I2CCMD_READY)
 			break;
+	}
 	if ((i2ccmd & I2CCMD_READY) == 0)
 		aprint_error_dev(sc->sc_dev, "I2CCMD Write did not complete\n");
 	if ((i2ccmd & I2CCMD_ERROR) != 0)
 		aprint_error_dev(sc->sc_dev, "I2CCMD Error bit set\n");
 	wm_put_swfw_semaphore(sc, SWFW_PHY0_SM);
+}
 /*
  * wm_gmii_82580_readreg:	[mii interface function]
+ *
  *	Read a PHY register on the 82580 and I350.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static int
 wm_gmii_82580_readreg(device_t self, int phy, int reg)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	int rv;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return 0;
+	}
 	rv = wm_gmii_i82544_readreg(self, phy, reg);
 	wm_put_swfw_semaphore(sc, sem);
 	return rv;
+}
 /*
  * wm_gmii_82580_writereg:	[mii interface function]
+ *
  *	Write a PHY register on the 82580 and I350.
  * This could be handled by the PHY layer if we didn't have to lock the
  * ressource ...
  */
 static void
 wm_gmii_82580_writereg(device_t self, int phy, int reg, int val)
+{
 	struct wm_softc *sc = device_private(self);
 	int sem;
 	sem = swfwphysem[sc->sc_funcid];
 	if (wm_get_swfw_semaphore(sc, sem)) {
 		aprint_error_dev(sc->sc_dev, "%s: failed to get semaphore\n",
 		    __func__);
 		return;
+	}
 	wm_gmii_i82544_writereg(self, phy, reg, val);
 	wm_put_swfw_semaphore(sc, sem);
+}
 /*
  * wm_gmii_statchg:	[mii interface function]
+ *
  *	Callback from MII layer when media changes.
  */
 static void
 wm_gmii_statchg(struct ifnet *ifp)
+{
 	struct wm_softc *sc = ifp->if_softc;
 	struct mii_data *mii = &sc->sc_mii;
 	sc->sc_ctrl &= ~(CTRL_TFCE | CTRL_RFCE);
 	sc->sc_tctl &= ~TCTL_COLD(0x3ff);
 	sc->sc_fcrtl &= ~FCRTL_XONE;
 	/*
 	 * Get flow control negotiation result.
 	 */
 	if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
 	    (mii->mii_media_active & IFM_ETH_FMASK) != sc->sc_flowflags) {
 		sc->sc_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
 		mii->mii_media_active &= ~IFM_ETH_FMASK;
+	}
 	if (sc->sc_flowflags & IFM_FLOW) {
 		if (sc->sc_flowflags & IFM_ETH_TXPAUSE) {
 			sc->sc_ctrl |= CTRL_TFCE;
 			sc->sc_fcrtl |= FCRTL_XONE;
+		}
 		if (sc->sc_flowflags & IFM_ETH_RXPAUSE)
 			sc->sc_ctrl |= CTRL_RFCE;
+	}
 	if (sc->sc_mii.mii_media_active & IFM_FDX) {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK: statchg: FDX\n", ifp->if_xname));
 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_FDX);
 	} else {
 		DPRINTF(WM_DEBUG_LINK,
 		    ("%s: LINK: statchg: HDX\n", ifp->if_xname));
 		sc->sc_tctl |= TCTL_COLD(TX_COLLISION_DISTANCE_HDX);
+	}
 	CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
 	CSR_WRITE(sc, WMREG_TCTL, sc->sc_tctl);
 	CSR_WRITE(sc, (sc->sc_type < WM_T_82543) ? WMREG_OLD_FCRTL
 						 : WMREG_FCRTL, sc->sc_fcrtl);
 	if (sc->sc_type == WM_T_80003) {
 		switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
 		case IFM_1000_T:
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
 			    KUMCTRLSTA_HD_CTRL_1000_DEFAULT);
 			sc->sc_tipg =  TIPG_1000T_80003_DFLT;
 			break;
 		default:
 			wm_kmrn_writereg(sc, KUMCTRLSTA_OFFSET_HD_CTRL,
 			    KUMCTRLSTA_HD_CTRL_10_100_DEFAULT);
 			sc->sc_tipg =  TIPG_10_100_80003_DFLT;
 			break;
+		}
 		CSR_WRITE(sc, WMREG_TIPG, sc->sc_tipg);
+	}
+}
 /*
  * wm_kmrn_readreg:
+ *
  *	Read a kumeran register
  */
 static int
 wm_kmrn_readreg(struct wm_softc *sc, int reg)
+{
 	int rv;
 	if (sc->sc_flags == WM_F_SWFW_SYNC) {
 		if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to get semaphore\n", __func__);
 			return 0;
+		}
 	} else if (sc->sc_flags == WM_F_SWFWHW_SYNC) {
 		if (wm_get_swfwhw_semaphore(sc)) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to get semaphore\n", __func__);
 			return 0;
+		}
+	}
 	CSR_WRITE(sc, WMREG_KUMCTRLSTA,
 	    ((reg << KUMCTRLSTA_OFFSET_SHIFT) & KUMCTRLSTA_OFFSET) |
 	    KUMCTRLSTA_REN);
 	delay(2);
 	rv = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
 	if (sc->sc_flags == WM_F_SWFW_SYNC)
 		wm_put_swfw_semaphore(sc, SWFW_MAC_CSR_SM);
 	else if (sc->sc_flags == WM_F_SWFWHW_SYNC)
 		wm_put_swfwhw_semaphore(sc);
 	return rv;
+}
 /*
  * wm_kmrn_writereg:
+ *
  *	Write a kumeran register
  */
 static void
 wm_kmrn_writereg(struct wm_softc *sc, int reg, int val)
+{
 	if (sc->sc_flags == WM_F_SWFW_SYNC) {
 		if (wm_get_swfw_semaphore(sc, SWFW_MAC_CSR_SM)) {
 			aprint_error_dev(sc->sc_dev,
 			    "%s: failed to get semaphore\n", __func__);